Static Timing Analysis

amey.hegde@wipro.com

Agenda
PRE-REQUISTES: Knowledge of Digital Design TOPICS COVERED : - Basic STA concepts - Basic Primetime Commands, Interpretaion of Primetime reports - Advanced STA (Mutliple clocks, Latches, OCV) - Setting up Primetime (Appendix 1)

What is Static timing Analysis?

What is static Timing Analysis (STA) ?
It is a method to determine if a circuit meets timing constraints without simulation.

Why Static Timing Analysis ?

100 % path coverage is possible because no design specific pattern is required All paths are assumed critical Process variation across die can be modeled constraints and reports are concise and easy to interpret

Place of STA in the ASIC Flow

SPEC S

Top Level Design and Architecture

Wireload models

RTL Coding

RTL Simulation/Verification

Synthesis

Cell Libraries DFT insertion

Gate level Simulation

Static Timing Analysis

Conventional Front End Back End Divide

Floor planning/P&R/Timing Closure/Design Closure

Parasitic Extraction (SPEF)

Back annotation ( SDF)

FAB Chip Testing

Basic STA concepts

Phases of STA:
Pre-Layout STA Clock skews Ideal clock assumed with estimated skew Wire load model
To verify the flow, for estimation

Post-Layout STA Actual clock delays (Propagated clock)

Parasitics (SPEF or SDF) Final Sign off

Net Delays Use

Wireload Models
Wire Loads Estimate interconnect length Statistical Analysis of Previously Routed Chips Predict the interconnect capacitance as a function of net fan-out and block size.
Wire Load Table Net Load Net Resistance

Net fanout

Net fanout

1 2

0.015 0.030 0.045 0.060

1 2

0.012 0.016

3
4

3
4

0.020
0.024

Inputs & Outputs of STA

Inputs
Netlist (verilog) : The gate level circuit description. Constraints (sdc/tcl) : The design related data Net Delays Parasitics (SPEF) : These are the parasitics of the design extracted from physical design tools. OR SDF : Standard Delay Format file containing back-annotated delays. Models (lib/db): The delay model of every cell in the library

Outputs
Reports : The timing paths report which can be used for debugging.

Basic STA concepts

Fundamental timing questions of a system
Can design work at specified clock speed ?

STA tool calculates

Arrival time (min/Early, max/Late) Required time(min/Early, max/Late) Slack

Basic STA concepts: Timing Paths

Timing Point INPUT

D Q FF1

D Q FF2

OUTPUT

CLOCK

Each path has a startpoint and an endpoint Timing path Startpoints - Input ports, - Clock pins of flip-flops Timing path Endpoints - Output ports, - all input pins of flip-flops except clock pins

Types of paths (I)

Setup time
Setup time: the time required for the data to be stable before the clock edge D1 Q1 FF1
0.4ns
Combo logic

D2 Q2 FF2

4.5ns

CLK CLK
setup violation
Launch Edge Capture Edge

D2
4.9

setup time

CLK
0 0.3 4.7 5

Hold time
Hold time: the time required for the data to remain stable after the clock edge D1 Q1 FF1 D2 Q2 FF2
0.3ns

CLK1

0.4ns

CLK2

CLK1
Launch Edge Capture Edge

CQ

D2=Q1
0.4 Hold violation hold time

CLK2

0.2

0.3 0.5

Setup and Hold time

Setup time: the time required for the data to be stable before the clock edge Hold time: the time required for the data to remain stable after the clock edge
D1 Q1 D2 Q2

FF1
CLK
hold time

FF2

CLK
setup time

Launch Edge Capture Edge

D2=Q1 Q2

CQ

CQ

Setup and Hold time in STA

Setup Requirement Hold Requirement

Clk at FF2 Data at D pin of FF2

100

Early Required Time

Late Required Time

Data should change only within this window

Important!! In STA, Setup is checked at next edge and hold is checked at same edge

Setup Check
Setup check

D Q FF1

D Q FF2

CALCULATION: Arrival time (max) = clock delay FF1 (max) +clock-to-Q delay FF1 (max) + comb. Delay( max) Required time = clock adjust + clock delay FF2 (min) - set up time FF2 Slack = Required time - Arrival time (since we want data to arrive before it is required) clock adjust = clock period (since setup is analyzed at next edge)

Hold check
Hold check
.

D Q FF1

D Q FF2

CALCULATION: Arrival time = clock delay FF1 (min) +clock-to-Q delay FF1 (min) + comb. Delay( min) Required time = clock adjust + clock delay FF2 (max) + hold time FF2 Slack = Arrival time - Required time (since we want data to arrive after it is required) clock adjust = 0 (since hold is analyzed at same edge)

Sections of a timing report

Header

Data Arrival Section

Data Required Section

Summary- Slack

Example hold report

Clocks
Slew or Transition time: Time taken for a signal to reach from 10% of VDD to 90% VDD
90%

Slew

10%

A clock is defined by its period, waveform and slew time.

Slew rise Waveform rise

Slew fall Waveform fall

Period

Clocks
Jitter - Variation in period from clock source (PLL)

Insertion Delay delay from clock source to the clock endpoint Skew - Difference in arrival time at clock endpoints

FF1

clk

FF2

clock skew = clock insertion delay of FF1 - clock insertion delay of FF2

Will Skew affect setup and hold? What about jitter?

Clocks
Source latency and Network latency

Pre vs Post Clock Tree Synthesis (CTS)

Pre vs Post Clock Tree Synthesis (CTS)

Test for Understanding (1)

Test for Understanding (2)

Master Clocks

Generated clocks: Internally divided clocks

Divided clocks (I)

create_generated_clock -name DIVIDE -source [get_ports SYSCLK] \ -divide_by 2 [get_pins FF1/Q]

Divided clocks (II)

create_generated_clock -edges { 1 5 7 } -name DIV3A -source \ [get_ports SYSCLK] [get_pins U2/Q]

Virtual Clocks

Virtual Clocks
Source latency and Network latency
Block
D Q D Q D Q D Q

On-block latency (network)

Off-block latency (source) Clock

Constraining the IOs

Input Delay

Test For Understanding

Circle the :
Input Delay constraint Input Port Name External start point clock

Output Delay

Test For Understanding

Circle the :Output Delay constraint
Why is there no library setup time in the Report?

Timing Exceptions
STA tools assume single cycle timing for all paths in design single cycle timing means that data propogates to its destination in less than one cycle timing exceptions are used to override the default single cycle constraints. False paths Multicycle paths Max delay Min delay

max_delay=1ns

False Paths
False path
- any logically false path - any register to register path which you do not wish to constrain - these paths are excluded from timing analysis

MultiCycle Paths (I)

Multi cycle path for setup: clock adjust time greater then one clock period for hold: clock adjust greater then zero time

MultiCycle Paths (II)

MultiCycle Paths (III)

Case analysis (I)

Case Analysis
Functional / Test modes of the design

specifying constant values or rise/fall transition at certain ports or pins.

Example
Test mode pin

Case analysis (II)

set_case_analysis 0 [get_ports "SCAN_MODE"]

Other Timing Checks Verified by STA

Types of paths (II)

[PrimeTime] : Path groups

PrimeTime implicitly creates a path group each time you use the create_clock command to create a new clock. clock_gating_default: paths that end on combinational elements used for clock gating async_default: paths that end on asynchronous preset/clear inputs of flipflops default: constrained paths that do not fall into any of the other implicit categories (for example, a path that ends on an output port) none: unconstrained paths

Basic STA concepts

Recovery and Removal
Recovery time is the minimum time that an asynchronous control must be stable before the clock active-edge transition. Removal time is the minimum length of time that an asynchronous control must be stable after the clock active-edge transition.

clock recovery time async_in removal time

Note:
Asynch resets are synchronized before giving to CLRZ (reset) pin of flip-flops

Gated clocks

Gated clocks
Clock gating Setup check Enable of the clock to be stable before clock assertion, to preserve the waveform Clock gating Hold check Enable of the clock to be stable after clock assertion, to preserve the waveform. Violation causes Glitch at the edge of the clock pulse. clipped clock pulse
Enable
A

Out
Z

Clock

clock clock gating setup Enable clock gating hold

Operating Conditions
Gate Delay depends on
input slew output load strength of the gate Voltage temperature

Sources of variation
process variation (P) Supply voltage (V) Operating Temperature (T)

Design corners
Best case (fast process highest voltage and lowest temperature) Worst case (slow process lowest voltage and highest temperature)

PVT Operating Conditions Maximum Operating Conditions - Worst Case

D E L A Y

7 7
0 1.0
PROCESS

D E L A Y

7
2.3

7
3.0
VOLTAGE

D E L A Y

7
7
0 12 TEMPERATURE 5

Minimum Operating Conditions - Best Case

Setup and Hold

scan enable scan chain
TI TI TE D Q QB

TE
D Q QB

functional

Most functional paths are long paths that make meeting timing during worst case operating conditions a challenge. Some functional paths, and many test paths, are very short, such as this scan chain.

Simultaneous Operating Conditions

scan enable (100ps)
TI

(350ps)
TI TE D Q

TE
D Q

(0 slack MAX)
Clk (300ps)

Clk (0ns)

QB

QB

Early mode timing needs to be aware of both minimum and maximum timing. Solution: Dont increase the loading of the Q output but use the unused QB output

On-Chip Variation
D Q QB

TEMP = 60

D Q QB

TEMP = 65

On-chip variation is minor differences on different parts of the chip within one operating condition.

On-Chip Variation
On-Chip variation (OCV)
delays vary across a single die due to variations in the maufacturing process (P), variations in the voltage (due to IR drop) and variations in the temperature (due to local hot spots etc.) This need to be modeled by scaling the coefficients

On-Chip Variation

OCV Derations
Timing analysis with on-chip variation. For cell delays, the on-chip variation is between 5 percent above and 10 percent below the SDF back-annotated values. For net delays, the on-chip variation is between 2 percent above and 4 percent below the SDF backannotated values. For cell timing checks, the on-chip variation is 10 percent above the SDF values for setup checks and 20 percent below the SDF values for hold checks.
pt_shell> read_sdf -analysis_type on_chip_variation my_design.sdf pt_shell> set_timing_derate -cell_delay -min 0.90 -max 1.05 pt_shell> set_timing_derate -net -min 0.96 -max 1.02 pt_shell> set_timing_derate -cell_check -min 0.80 -max 1.10

CRPR
Common path pessimism
It is possible to have common logic between min and max paths It is not possible to have two different delays simultaneously in a single gate or wire Common path pessimism removal removes common delays.

Primetime Report
Primetime slack report: Interpretation
-------------------------------------------------------------------------------------------------------------------------Point Incr Path -------------------------------------------------------------------------------------------------------------------------clock CLK (rise edge) 0.00 0.00 clock network delay (propagated) -> clock path delay of launch path (startpt) 1.40 1.40 FF1/CP (FD2) 0.00 1.40 r FF 1/Q (FD2) ->CLK to Q delay 0.60 2.00 f BUF1/y (BUF) -> combo delay upto the D pin of the endpt. register 3.20 5.20 f data arrival time 5.20 clock CLK (rise edge) -> includes Cycle adjust of 1 clock period 5.00 5.00 clock network delay (propagated) -> clock path delay of capture path (Endpt) 1.16 6.16 clock reconvergence pessimism -> after correction for CRPR 0.16 6.32 clock uncertainty -> post cts this is only jitter -0.10 6.22 FF2/CP (FD2) 6.22 r library setup time - 0.20 6.02 data required time 6.02 ---------------------------------------------------------------------------------------------------------------------------data required time 6.02 data arrival time -5.20 ---------------------------------------------------------------------------------------------------------------------------slack (MET) 0.82 Path slack = required time- arrival time = (6.02-5.20)=0.82

Multiple Clocks: Setup

Multiple Clocks: Hold

Multiple Clocks: Setup and Hold (I)

Multiple Clocks: Setup and Hold (II)

Setup Relationship: A Rising, B Rising

Find the Setup Relationship between A rising and B rising:
A (6 ns)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

8 B (8ns)
0 1 2 3 4 5 6

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

D Q D Q

QB QB

The setup relationship is the closest distance between the launching clock edge (A) and the receiving clock edge (B)

Hold Relationship: A Rising, B Rising

Find the Hold Relationship between A rising and B rising
A
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

0 B
0 1 2 3

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

D Q D Q

QB QB

The hold relationship is the closest distance between the launching edge (A) and the previous receiving edge (B)

Static Timing With Latches

Latches
Latches and Flip-Flops are both registers, or storage devices D
D Q

QB

Q B

Latches are level sensitive instead of edge triggered E

0 1 2 3 4 5 6 7 8

D
0 1 2 3 4 5 6 7 8

Q
0 1 2 3 4 5 6 7 8

Time Borrowing
D Q G D Q

D Q G

PHI 1 PHI 1 PHI 2

a_reg

PHI b_reg 2

c_reg

10

15

20

If these were flip flops, timing would not be met at b_reg. With time borrowing, the middle latch can borrow time from the next stage and meet timing.

Time Borrowing Example 2

D Q G

D Q G

D Q G

PHI 1 PHI 1 PHI 2

a_reg

PHI b_reg 2

c_reg

10

15

20

Q. Can time borrowing eliminate negative slack? No, the final data missed the active edge of c_reg.

Time Borrowing Example 3

D Q G

D Q G

D Q

PHI 1 PHI 1 PHI 2

a_reg

PHI b_reg 2

c_reg

10

15

20

Q. Can time borrowing eliminate negative slack? No, c_reg is a flip-flop and the data misses c_regs edge

Time Borrowing Example 4

D Q

D Q G

D Q G

PHI 1 PHI 1 PHI 2

a_reg

PHI b_reg 2

c_reg

10

15

20

Q. Can time borrowing eliminate negative slack?

Yes, in fact there is extra time before the activating edge of c_reg.

Time Borrowing Example 5

D Q G

D Q G

11

D Q G

PHI 1 PHI 1 PHI 2

a_reg

PHI b_reg 2

c_reg

10

15

20

Q. Can time borrowing eliminate negative slack?

No. The earliest b_reg can launch the data is at time 5. c_reg will receive the data too late

Latches: Time Borrowing

Latches: Time Borrowing

Latches: Time Borrowing

Constraining Multiple-Mode Designs

Multiple Mode Designs

Same physical net may be part of two clocks
The functional clock The test clock A mode input chooses which clock is propagated

Timing optimization requires that

Setup and hold violations do not occur in test or functional mode Optimizer is aware of both modes concurrently
optimizing only one mode at a time might fix a hold violation in one mode, only to cause a setup violation in the other.

Constraints must expose all timing modes concurrently

Simple Clock Scheme for Multimode

SCAN_IN
DATA_IN QB TEST_EN TEST_CLK 1 FUNC_CLK QB scan SD D Q scan SD DATA_OUT

TEST_EN signal controls which clock to propagate.

TEST_EN = 1 means TEST_CLK will propagate.
Scan chains are activated via the scan pins of registers.

TEST_EN = 0 means FUNC_CLK will propagate.

Functional paths are activated via the data pins of registers.

Solution for Simple Multimode Scheme

SCAN_IN
DATA_IN QB TEST_EN TEST_CLK 1 FUNC_CLK QB scan SD D Q scan SD DATA_OUT

A simple multimode scheme allows the timer to be aware of the propagation of both clocks in the same run.
This awareness enables single-pass implementation and optimization of both clocks and their associated timing paths.

Three Categories of Constraints

Master constraints file
Contains most constraints for all modes of operation

Overlapping clock exceptions file

Contains constraints necessary to enable multiple modes to be visible in the same pass This file is read on top of the main constraints file in Magma for all implementation/optimization runs.

Individual mode constraints files

One file for each mode of operation In this example there are two (one each for test and functional modes). These files should not contain more than constant settings. These files are not used in Magma for implementation/optimization. This type of file is read on top of the main constraints file in PrimeTime to set PrimeTime to a particular mode. The same is done in Magma for correlation-to-PrimeTime runs.

The Master Constraints File

SCAN_IN DATA_IN scan SD D Q

scan SD
D Q QB

DATA_OUT

QB
TEST_EN TEST_CLK 1 FUNC_CLK

Define both TEST_CLK and FUNC_CLK Apply timing constraints for all I/O and scan ports with respect to appropriate clock Apply all other constraints as usual (drives, loads, slews, etc.) If multiple functional clocks can drive a given clock pin, choose the clock with the highest frequency and define that clock only
This applies only to the case where the same boundary clock pin might be driven by different clocks, depending on the mode.

Do not declare all paths from/to either clock to be false, (Avoid openended false path statements on clocks). Do not set constants that choose either test mode or scan mode (Do not set TEST_EN high or low).

The Overlapping CLK Exceptions File

SCAN_IN DATA_IN scan SD D Q

scan SD
D Q QB

DATA_OUT

QB
TEST_EN TEST_CLK 1 FUNC_CLK

Declare the following as false:

Paths from FUNC_CLK to all SD pins, if these paths cannot meet timing Paths from TEST_CLK to FUNC_CLK Paths from FUNC_CLK to TEST_CLK

PrimeTime Correlation - Mode Analysis

SCAN_IN DATA_IN QB TEST_EN QB scan SD scan SD D Q DATA_OUT

TEST_CLK
1 FUNC_CLK

PrimeTime must perform mode analysis (set the design in a mode), because it cannot propagate multiple clocks on a net. For PrimeTime runs, you need one additional constraints file for each mode (mode constraints file) to set the design in a mode.
For this simple example we need two files: test mode and func mode
The test mode constraints file has the command:

set_case_analysis 1 TEST_EN
The func mode constraints file has the command:

set_case_analysis 0 TEST_EN

Combinational Loops

Combinational Loop Example

A

U1
Z

D Q QB

U0
A Z B

D Q

QB

Most STAs cant leave combinational loops in the design, because a race condition will occur.
AT

1.1 3.1 5.1

References/Resources:
Magma STA training slides VSBU STA training ppt. Primetime user guide Primetime tutorial can be used for hands on

Appendix 1

Primetime
Primetime Flow:
Read and Link Designs and Libraries

Specify Attributes, Environment,Constraints, Timing Exceptions

Perform Analysis: Reports and Visual analysis

 Setup Files :

Primetime

When primetime is invoked,it accesses .synopsys_pt.setup file in the following order

Synopsys root directory the file provided by Synopsys contains general setup information. User home directory - User can create this file for specific Primetime environment. Directory from which user starts Primetime ( current working directory ).User can create this file and customize it for a particular design.

Setup the design environment :

Set the search path and link path. Read the Libraries and Design. Link the top design. Setup the operating conditions ,wireload models,port load,drive and transition time.

Primetime
Specify the timing assertions (constraints) Define clock period,waveform,latency and uncertainty. Specify input and output port delays.

Specify timing exceptions specify multicycle path specify false path Specify minimum and maximum delays specify disabled arcs.

Perform analysis and generate reports

Check timing Generate constraint reports Generate path timing reports

Defining search path and Link path :

notifies Primetime the files to use and where to use them to perform Link process search path and link path are defined through primetime variable search_path and link_path respectively e.g: set search_path . ../../lib set link_path * vendor_lib.db

Primetime
Reading the Designs
Primetime reads following design formats Synopsys database files (.db) Verilog netlist files Electronic Data Interchange Format( EDIF) netlist files VHDL netlist files e.g : r ea d _d b ../ gt ech / cou n t er .d b r ea d _ver ilog ../ n et / cou n t er .v r ea d _ed if ../ ed if/ cou n t er .ed if r ea d _vh d l ../ n et / cou n t er .vh d l

Linking the Design

link process resolves design references it loads libraries and designs specified in the link_path variable if design is referenced and but was not explicitly loaded, linker attempts to load the design where the design is the referenced design - autoload

Primetime
Defining operating conditions
ICs exhibit different performance under different operating conditions operating conditions contains process derating factor(P), supply voltage(V),ambient temperature and interconnect model type delay calculation is affected by the operating conditions

Setting Wireload Models

predicts net capacitance and resistance after placement and routing net capacitance affects cell and net delays net resistance affects net delay wireload model is basically set of tables net fanout vs load net fanout vs resistance net fanout vs area To access the timing of a circuit as accurately as possible WLM should be specified Since WLMs are used to model the effects of layout,they should be chosen carefully based on recommendation of your vendor a tree_type attribute in operating condition tells PT to model the net there are three possible tree types worst_case_tree ( pessimistic), best_case_tree ( optimistic ), balanced_tree.