Professional Documents
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8 I 8 I
OLMC
I/O/Q
OLMC
I/O/Q
OLMC
I/O/Q
OLMC
I/O/Q
OLMC
I/O/Q
OLMC
I/O/Q
I 8 I 8 I OLMC
OE
OLMC
I/O/Q
I/O/Q
I/OE
DESCRIPTION The GAL16V8D, at 3.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times (<100ms) allow the devices to be reprogrammed quickly and efficiently. The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user. An important subset of the many architecture configurations possible with the GAL16V8 are the PAL architectures listed in the table of the macrocell description section. GAL16V8 devices are capable of emulating any of these PAL architectures with full function/fuse map/parametric compatibility. Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor guarantees 100% field programmability and functionality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are guaranteed.
PIN CONFIGURATION
DIP PLCC
I I 2 I I I I I 8 14 9 I GND 11 I/OE I/O/Q 13 6 4 I/CLK Vcc 20 18 I/O/Q I/O/Q
I/CLK I I I
20
GAL16V8
16
I/O/Q
GAL 16V8
5 15
I
I/O/Q I/O/Q I/O/Q
Top View
I I I
I/O/Q
I GND 10 11
I/OE
Copyright 1996 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 681-0118; 1-888-ISP-PLDS; FAX (503) 681-3037; http://www.latticesemi.com
16v8_02
Specifications GAL16V8
GAL16V8 ORDERING INFORMATION
Commercial Grade Specifications
Tpd (ns)
3.5 5
Tsu (ns)
2.5 3
Tco (ns)
3.0 4
Icc (mA)
115 115 11 5 GAL16V8D-3LJ
Ordering #
Package
20-Lead PLCC 20-Pin Plastic DIP 20-Lead PLCC 20-Pin Plastic DIP 20-Lead PLCC 20-Pin Plastic DIP 20-Lead PLCC 20-Pin Plastic DIP 20-Lead PLCC 20-Pin Plastic DIP 20-Lead PLCC 20-Pin Plastic DIP 20-Lead PLCC 20-Pin Plastic DIP 20-Lead PLCC 20-Pin Plastic DIP 20-Lead PLCC 20-Pin Plastic DIP 20-Lead PLCC
GAL16V8C-5LP GAL16V8C-5LJ GAL16V8C-7LP GAL16V8C-7LJ GAL16V8B-7LP GAL16V8B-7LJ GAL16V8B-10LP GAL16V8B-10LJ GAL16V8D-10QP GAL16V8D-10QJ GAL16V8D-15QP or GAL16V8B-15QP GAL16V8D-15QJ or GAL16V8B-15QJ GAL16V8D-15LP or GAL16V8B-15LP GAL16V8D-15LJ or GAL16V8B-15LJ GAL16V8D-25QP or GAL16V8B-25QP GAL16V8D-25QJ or GAL16V8B-25QJ GAL16V8D-25LP or GAL16V8B-25LP GAL16V8D-25LJ or GAL16V8B-25LJ
7.5
10
10
115 115
10
10
7.5
55 55
15
12
10
55 55 90 90
25
15
12
55 55 90 90
Tsu (ns)
7
Tco (ns)
5
Icc (mA)
130 130
Ordering #
GAL16V8C-7LPI GAL16V8C-7LJI GAL16V8B-10LPI GAL16V8B-10LJI GAL16V8D-15LPI or GAL16V8B-15LPI GAL16V8D-15LJI or GAL16V8B-15LJI GAL16V8D-20QPI or GAL16V8B-20QPI GAL16V8D-20QJI or GAL16V8B-20QJI GAL16V8D-25QPI or GAL16V8B-25QPI GAL16V8D-25QJI or GAL16V8B-25QJI GAL16V8D-25LPI or GAL16V8B-25LPI GAL16V8D-25LJI or GAL16V8B-25LJI
Package
20-Pin Plastic DIP 20-Lead PLCC 20-Pin Plastic DIP 20-Lead PLCC 20-Pin Plastic DIP 20-Lead PLCC 20-Pin Plastic DIP 20-Lead PLCC 20-Pin Plastic DIP 20-Lead PLCC 20-Pin Plastic DIP 20-Lead PLCC
10
10
130 130
15
12
10
130 130
20
13
11
65 65
25
15
12
65 65 130 130
GAL16V8D Device Name GAL16V8C GAL16V8B Speed (ns) L = Low Power Q = Quarter Power Power
Grade
Specifications GAL16V8
OUTPUT LOGIC MACROCELL (OLMC)
The following discussion pertains to configuring the output logic macrocell. It should be noted that actual implementation is accomplished by development software/hardware and is completely transparent to the user. There are three global OLMC configuration modes possible: simple , complex , and registered . Details of each of these modes are illustrated in the following pages. Two global bits, SYN and AC0, control the mode configuration for all macrocells. The XOR bit of each macrocell controls the polarity of the output in any of the three modes, while the AC1 bit of each of the macrocells controls the input/output configuration. These two global and 16 individual architecture bits define all possible configurations in a GAL16V8 . The information given on these architecture bits is only to give a better understanding of the device. Compiler software will transparently set these architecture bits from the pin definitions, so the user should not need to directly manipulate these architecture bits. The following is a list of the PAL architectures that the GAL16V8 can emulate. It also shows the OLMC mode under which the GAL16V8 emulates the PAL architecture.
PAL Architectures Emulated by GAL16V8 16R8 16R6 16R4 16RP8 16RP6 16RP4 16L8 16H8 16P8 10L8 12L6 14L4 16L2 10H8 12H6 14H4 16H2 10P8 12P6 14P4 16P2 GAL16V8 Global OLMC Mode Registered Registered Registered Registered Registered Registered Complex Complex Complex Simple Simple Simple Simple Simple Simple Simple Simple Simple Simple Simple Simple
1) Used with Configuration keyword. 2) Prior to Version 2.0 support. 3) Supported on Version 1.20 or later.
Specifications GAL16V8
REGISTERED MODE
In the Registered mode, macrocells are configured as dedicated registered outputs or as I/O functions. Architecture configurations available in this mode are similar to the common 16R8 and 16RP4 devices with various permutations of polarity, I/O and register placement. All registered macrocells share common clock and output enable control pins. Any macrocell can be configured as registered or I/O. Up to eight registers or up to eight I/O's are possible in this mode. Dedicated input or output functions can be implemented as subsets of the I/O function. Registered outputs have eight product terms per output. I/O's have seven product terms per output. The JEDEC fuse numbers, including the User Electronic Signature (UES) fuses and the Product Term Disable (PTD) fuses, are shown on the logic diagram on the following page.
CLK
Registered Configuration for Registered Mode - SYN=0. - AC0=1. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1=0 defines this output configuration. - Pin 1 controls common CLK for the registered outputs. - Pin 11 controls common OE for the registered outputs. - Pin 1 & Pin 11 are permanently configured as CLK & OE.
Q Q
XOR
OE
Combinatorial Configuration for Registered Mode - SYN=0. - AC0=1. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1=1 defines this output configuration. - Pin 1 & Pin 11 are permanently configured as CLK & OE.
XOR
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.
Specifications GAL16V8
REGISTERED MODE LOGIC DIAGRAM
DIP & PLCC Package Pinouts
1
0 0000 4 8 12 16 20 24 28 2128 PTD
OLMC
0224
19
2
0256
XOR-2048 AC1-2120
OLMC
0480
18
3
0512
XOR-2049 AC1-2121
OLMC
0736
17
4
0768
XOR-2050 AC1-2122
OLMC
0992
16
5
1024
XOR-2051 AC1-2123
OLMC
1248
15
6
1280
XOR-2052 AC1-2124
OLMC
1504
14
7
1536
XOR-2053 AC1-2125
OLMC
1760
13
8
1792
XOR-2054 AC1-2126
OLMC
2016
12
9
2191
XOR-2055 AC1-2127
OE
11
SYN-2192 AC0-2193
Specifications GAL16V8
COMPLEX MODE
In the Complex mode, macrocells are configured as output only or I/O functions. Architecture configurations available in this mode are similar to the common 16L8 and 16P8 devices with programmable polarity in each macrocell. Up to six I/O's are possible in this mode. Dedicated inputs or outputs can be implemented as subsets of the I/O function. The two outer most macrocells (pins 12 & 19) do not have input capability. Designs requiring eight I/O's can be implemented in the Registered mode. All macrocells have seven product terms per output. One product term is used for programmableoutput enable control. Pins 1 and 11 are always available as data inputs into the AND array. The JEDEC fuse numbers including the UES fuses and PTD fuses are shown on the logic diagram on the following page.
Combinatorial I/O Configuration for Complex Mode - SYN=1. - AC0=1. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1=1. - Pin 13 through Pin 18 are configured to this function.
XOR
Combinatorial Output Configuration for Complex Mode - SYN=1. - AC0=1. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1=1. - Pin 12 and Pin 19 are configured to this function.
XOR
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.
Specifications GAL16V8
COMPLEX MODE LOGIC DIAGRAM
DIP & PLCC Package Pinouts
1
2128
0
0000
12
16
20
24
28
PTD
OLMC
0224
19
2
0256
XOR-2048 AC1-2120
OLMC
0480
18
3
0512
XOR-2049 AC1-2121
OLMC
0736
17
4
0768
XOR-2050 AC1-2122
OLMC
0992
16
5
1024
XOR-2051 AC1-2123
OLMC
1248
15
6
1280
XOR-2052 AC1-2124
OLMC
1504
14
7
1536
XOR-2053 AC1-2125
OLMC
1760
13
8
1792
XOR-2054 AC1-2126
OLMC
2016
12
XOR-2055 AC1-2127 11
2191
SYN-2192 AC0-2193
Specifications GAL16V8
SIMPLE MODE
In the Simple mode, macrocells are configured as dedicated inputs or as dedicated, always active, combinatorial outputs. Architecture configurations available in this mode are similar to the common 10L8 and 12P6 devices with many permutations of generic output polarity or input choices. All outputs in the simple mode have a maximum of eight product terms that can control the logic. In addition, each output has programmable polarity. Pins 1 and 11 are always available as data inputs into the AND array. The center two macrocells (pins 15 & 16) cannot be used as input or I/O pins, and are only available as dedicated outputs. The JEDEC fuse numbers including the UES fuses and PTD fuses are shown on the logic diagram.
Vcc
Combinatorial Output with Feedback Configuration for Simple Mode - SYN=1. - AC0=0. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1=0 defines this configuration. - All OLMC except pins 15 & 16 can be configured to this function.
XOR
XOR
- SYN=1. - AC0=0. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1=0 defines this configuration. - Pins 15 & 16 are permanently configured to this function.
Dedicated Input Configuration for Simple Mode - SYN=1. - AC0=0. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1=1 defines this configuration. - All OLMC except pins 15 & 16 can be configured to this function.
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.
Specifications GAL16V8
SIMPLE MODE LOGIC DIAGRAM
DIP & PLCC Package Pinouts
1
2128
0
0000
12
16
20
24
28
PTD
OLMC
XOR-2048 AC1-2120 19
0224
2
0256
OLMC
XOR-2049 AC1-2121 18
0480
3
0512
OLMC
XOR-2050 AC1-2122 17
0736
4
0768
OLMC
XOR-2051 AC1-2123 16
0992
5
1024
OLMC
XOR-2052 AC1-2124 15
1248
6
1280
OLMC
XOR-2053 AC1-2125 14
1504
7
1536
OLMC
XOR-2054 AC1-2126 13
1760
8
1792
OLMC
XOR-2055 AC1-2127 12 11
2016
2191
SYN-2192 AC0-2193
DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating Conditions (Unless Otherwise Specified) SYMBOL PARAMETER Input Low Voltage Input High Voltage Input or I/O Low Leakage Current Input or I/O High Leakage Current Output Low Voltage Output High Voltage 0V VIN VIL (MAX.) 3.5V VIN VCC IOL = MAX. Vin = VIL or VIH IOH = MAX. Vin = V IL or V IH L-3 CONDITION MIN.
Vss 0.5
TYP.3
UNITS V V A A V V mA mA
2.0 2.4
L-15/-25 Q-10/-15/-20/-25
High Level Output Current Output Short Circuit Current VCC = 5V VOUT = 0.5V TA= 25C
30
3.2 150
mA mA
VIL = 0.5V
VIH = 3.0V
L -3 L-15/-25 Q-10/-15/-25
75 75 45
115 90 55
mA mA mA
VIL = 0.5V
VIH = 3.0V
L -15/-25 Q -20/-25
75 45
130 65
mA mA
1) The leakage current is due to the internal pull-up resistor on all pins. See Input Buffer section for more information. 2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester ground degradation. Guaranteed but not 100% tested. 3) Typical values are at Vcc = 5V and TA = 25 C
10
DESCRIPTION Input or I/O to Comb. Output Clock to Output Delay Clock to Feedback Delay 1 1
-3
MIN.
-10
MAX. MIN.
-15
-20
-25 UNITS
MAX.
MAX. MIN.
MAX. MIN.
MAX. MIN.
A A A
3.5 3 2.5
3 2 10 0 57.1
10 7.5 6
3 2 12 0 45.5
15 10 8
3 2 13 0 41.6
20 11 9
3 2 15 0 37
25 12 10
ns ns ns ns ns MHz
Setup Time, Input or Fdbk before Clk 2.5 Hold Time, Input or Fdbk after Clk Maximum Clock Frequency with External Feedback, 1/(tsu + tco) Maximum Clock Frequency with Internal Feedback, 1/(tsu + tcf) Maximum Clock Frequency with No Feedback Clock Pulse Duration, High Clock Pulse Duration, Low Input or I/O to Output Enabled OE to Output Enabled Input or I/O to Output Disabled OE to Output Disabled 0 182
fmax3
A A
200 250
62.5 62.5
50 62.5
45.4 50
40 41.6
MHz MHz
B B C C
2 2
8 8 3 2 2 1
10 10 10 10
8 8
15 15 15 15
10 10
18 18 18 18
12 12
20 20 20 20
ns ns ns ns ns ns
11
DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating Conditions (Unless Otherwise Specified) SYMBOL PARAMETER Input Low Voltage Input High Voltage Input or I/O Low Leakage Current Input or I/O High Leakage Current Output Low Voltage Output High Voltage Low Level Output Current High Level Output Current Output Short Circuit Current VCC = 5V VOUT = 0.5V TA= 25C 0V VIN VIL (MAX.) 3.5V VIN VCC IOL = MAX. Vin = VIL or VIH IOH = MAX. Vin = VIL or VIH CONDITION MIN.
Vss 0.5
TYP.3
UNITS V V A A V V mA mA mA
2.0 2.4 30
VIL = 0.5V
VIH = 3.0V
L -5/-7
75
115
mA
VIL = 0.5V
VIH = 3.0V
L -7
75
130
mA
1) The leakage current is due to the internal pull-up resistor on all pins. See Input Buffer section for more information. 2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester ground degradation. Guaranteed but not 100% tested. 3) Typical values are at Vcc = 5V and TA = 25 C
12
TEST COND1. A
-5
-7
-7 UNITS
5 4 3
3 2 7 0 83.3
7.5 7 5 3
1 1 7 0 83.3
7.5 5 3
ns ns ns ns ns ns MHz
A A
Clock to Output Delay Clock to Feedback Delay Setup Time, Input or Feedback before Clock Hold Time, Input or Feedback after Clock Maximum Clock Frequency with External Feedback, 1/(tsu + tco) Maximum Clock Frequency with Internal Feedback, 1/(tsu + tcf) Maximum Clock Frequency with No Feedback Clock Pulse Duration, High Clock Pulse Duration, Low Input or I/O to Output Enabled OE to Output Enabled Input or I/O to Output Disabled OE to Output Disabled
142.8
fmax3
A A
166 166
100 100
100 100
MHz MHz
B B C C
3 3 1 1 1 1
6 6 5 5
5 5 3 2 2 1.5
9 6 9 6
5 5 1 1 1 1
9 6 9 6
ns ns ns ns ns ns
1) Refer to Switching Test Conditions section. 2) Calculated from fmax with internal feedback. Refer to fmax Descriptions section. 3) Refer to fmax Descriptions section. Characterized initially and after any design or process changes that may affect these parameters.
13
DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating Conditions (Unless Otherwise Specified) SYMBOL PARAMETER Input Low Voltage Input High Voltage Input or I/O Low Leakage Current Input or I/O High Leakage Current Output Low Voltage Output High Voltage Low Level Output Current High Level Output Current Output Short Circuit Current VCC = 5V VOUT = 0.5V TA= 25C 0V VIN VIL (MAX.) 3.5V VIN VCC IOL = MAX. Vin = VIL or VIH IOH = MAX. Vin = VIL or VIH CONDITION MIN.
Vss 0.5
TYP.3
UNITS V V A A V V mA mA mA
2.0 2.4 30
100
10 0.5 24 3.2 150
VIL = 0.5V
VIH = 3.0V
75 75 45
115 90 55
mA mA mA
VIL = 0.5V
VIH = 3.0V
L -10/-15/-25 Q -20/-25
75 45
130 65
mA mA
1) The leakage current is due to the internal pull-up resistor on all pins. See Input Buffer section for more information. 2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester ground degradation. Guaranteed but not 100% tested. 3) Typical values are at Vcc = 5V and TA = 25 C
14
-7
MIN.
-10
MAX. MIN.
-15
-20
-25 UNITS
MAX.
MAX. MIN.
MAX. MIN.
MAX. MIN.
7.5 7 5 3
3 2 10 0 58.8
10 7 6
3 2 12 0 45.5
15 10 8
3 2 13 0 41.6
20 11 9
3 2 15 0 37
25 12 10
ns ns ns ns ns ns MHz
A A
Clock to Output Delay Clock to Feedback Delay Setup Time, Input or Fdbk before Clk Hold Time, Input or Fdbk after Clk Maximum Clock Frequency with External Feedback, 1/(tsu + tco) Maximum Clock Frequency with Internal Feedback, 1/(tsu + tcf) Maximum Clock Frequency with No Feedback Clock Pulse Duration, High Clock Pulse Duration, Low Input or I/O to Output Enabled OE to Output Enabled Input or I/O to Output Disabled OE to Output Disabled
83.3
fmax3
A A
100 100
62.5 62.5
50 62.5
45.4 50
40 41.6
MHz MHz
B B C C
5 5 3 2 2 1.5
9 6 9 6
8 8 3 2 2 1.5
10 10 10 10
8 8
15 15 15 15
10 10
20 18 20 18
12 12
25 20 25 20
ns ns ns ns ns ns
1) Refer to Switching Test Conditions section. 2) Calculated from fmax with internal feedback. Refer to fmax Descriptions section. 3) Refer to fmax Descriptions section.
15
Specifications GAL16V8
SWITCHING WAVEFORMS
VALID INPUT
tsu
INPUT or I/O FEEDBACK CLK VALID INPUT
th
tco
REGISTERED OUTPUT 1/fmax (external fdbk)
tpd
COMBINATIONAL OUTPUT
Combinatorial Output
Registered Output
OE
tdis
COMBINATIONAL OUTPUT
ten
REGISTERED OUTPUT
tdis
ten
to Output Enable/Disable
twh
CLK 1/fmax (w/o fb)
twl
tcf
REGISTERED FEEDBACK
tsu
Clock Width
16
Specifications GAL16V8
fmax DESCRIPTIONS
CLK
LOGIC ARRAY
CLK
REGISTER
LOGIC ARRAY
tsu
tco
REGISTER
t cf t pd
tsu + th
Note: tcf is a calculated value, derived by subtracting tsu from the period of fmax w/internal feedback (tcf = 1/fmax - tsu). The value of tcf is used primarily when calculating the delay from clocking a register to a combinatorial output (through registered feedback), as shown above. For example, the timing from clock to a combinatorial output is equal to tcf + tpd.
Input Pulse Levels GAL16V8B and Input Rise and Fall Times GAL16V8D-10 (and slower) GAL16V8C and GAL16V8D-3 Input Timing Reference Levels Ouput Timing Reference Levels Output Load 3-state levels are measured 0.5V from steady-state active level.
TEST POINT
R2
C L*
GAL16V8B and GAL16V8D-10/-15/-20/-25 Output Load Conditions (see figure above) Test Condition A B C Active High Active Low Active High Active Low R1 200 200 200 R2 390 390 390 390 390 CL 50pF 50pF 50pF 5pF 5pF
GAL16V8C Output Load Conditions (see figure above) Test Condition A B C Active High Active Low Active High Active Low R1 200 200 200 R2 200 200 200 200 200 CL 50pF 50pF 50pF 5pF 5pF
17
Specifications GAL16V8
SWITCHING TEST CONDITIONS, CONTINUED
GAL16V8D-3 Output Load Conditions (see figure at right) Test Condition A B C High Z to Active High at 1.9V High Z to Active Low at 1.0V Active High to High Z at 1.9V Active Low to High Z at 1.0V R1 50 50 50 50 50 CL 35pF 35pF 35pF 35pF 35pF
TEST POINT R1 +1.45V
Z0 = 50, CL = 35pF*
ELECTRONIC SIGNATURE
An electronic signature is provided in every GAL16V8 device. It contains 64 bits of reprogrammable memory that can contain user defined data. Some uses include user ID codes, revision numbers, or inventory control. The signature data is always available to the user independent of the state of the security cell. NOTE: The electronic signature is included in checksum calculations. Changing the electronic signature will alter the checksum.
SECURITY CELL
A security cell is provided in the GAL16V8 devices to prevent unauthorized copying of the array patterns. Once programmed,this cell prevents further read access to the functional bits in the device. This cell can only be erased by re-programmingthe device, so the original configuration can never be examined once this cell is programmed. The Electronic Signature is always available to the user, regardless of the state of this control cell.
INPUT BUFFERS
GAL16V8 devices are designed with TTL level compatible input buffers. These buffers have a characteristicallyhigh impedance, and present a much lighter load to the driving logic than bipolar TTL devices. The GAL16V8 input and I/O pins have built-in active pull-ups. As a result, unused inputs and I/O's will float to a TTL "high" (logical "1"). Lattice Semiconductor recommends that all unused inputs and tri-stated I/O pins be connected to another active input, VCC, or Ground. Doing this will tend to improve noise immunity and reduce ICC for the device.
LATCH-UP PROTECTION
GAL16V8 devices are designed with an on-board charge pump to negatively bias the substrate. The negative bias minimizes the potential of latch-up caused by negative input undershoots. Additionally, outputs are designed with n-channel pull-ups instead of the traditional p-channel pull-ups in order to eliminate latch-up due to output overshoots.
DEVICE PROGRAMMING
I n p u t C u r r e n t (u A )
GAL devices are programmed using a Lattice Semiconductorapproved Logic Programmer, available from a number of manufacturers. Complete programming of the device takes only a few seconds. Erasing of the device is transparent to the user, and is done automatically as part of the programming cycle.
-20
In p u t V o lt ag e ( V o lt s)
18
Specifications GAL16V8
POWER-UP RESET
Vcc
Vcc (min.)
t su
CLK
t wl t pr
Circuitry within the GAL16V8 provides a reset signal to all registers during power-up. All internal registers will have their Q outputs set low after a specified time (tpr, 1s MAX). As a result, the state on the registered output pins (if they are enabled) will always be high on power-up, regardless of the programmed polarity of the output pins. This feature can greatly simplify state machine design by providing a known state on power-up. Because of the asynchronous nature of system power-up, some
conditions must be met to guarantee a valid power-up reset of the device. First, the VCC rise must be monotonic. Second, the clock input must be at static TTL level as shown in the diagram during power up. The registers will reset within a maximum of tpr time. As in normal system operation, avoid clocking the device until all input and feedback path setup times have been met. The clock must also meet the minimum pulse width requirements.
Vcc
Active Pull-up Circuit
Active Pull-up Circuit
Vcc
ESD Protection Circuit
Vref
Vcc
Tri-State Control
Vcc
Vref
PIN
Data Output
PIN
19
Specifications GAL16V8
GAL 16V8D-3: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS
Normalized Tpd vs Vcc
1.2 1.2
Normalized Tpd
1.1
Normalized Tco
Normalized Tsu
PT H->L PT L->H
1.1
RISE FALL
1.1
PT H->L PT L->H
0.9
0.9
0.9
0.8 4.50
4.75
5.00
5.25
5.50
0.8 4.50
4.75
5.00
5.25
5.50
0.8 4.50
4.75
5.00
5.25
5.50
Normalized Tpd
Normalized Tco
-25
25
50
75
100
125
-25
25
50
75
100
125
Normalized Tsu
PT H->L PT L->H
RISE FALL
PTH->L PT L->H
-25
25
50
75
1 00
1 25
Temperature (deg. C)
Temperature (deg. C)
Temperature (deg. C)
-0.1
-0.1
-0.2
-0.2
RISE FALL
-0.3
-0.3
RISE FALL
-0.4 1 2 3 4 5 6 7 8
-0.4 1 2 3 4 5 6 7 8
10 8 6 4 2 0 -2 0 50
RISE FALL
10 8 6 4 2 0 -2
RISE FALL
100
150
200
250
3 00
50
100
150
200
250
3 00
20
Specifications GAL16V8
GAL 16V8D-3: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS
Vol vs Iol
1 5
Voh vs Ioh
3.25
Voh vs Ioh
0.75
4 3
Voh (V)
Vol (V)
0.5
Voh (V)
0 10 20 30 40 50
2.75
0.25 1
0 0 10 20 30 40
2.5 0 1 2 3 4
1.2
Normalized Icc
Normalized Icc
Normalized Icc
-25 0 25 50 75 100 125
1.1
1.1
0.9
0.9
0.8 4.50
4.75
5.00
5.25
5.50
0.8 -55
Frequency (MHz)
20
Iik (mA)
30 40 50 60 70 80
90 -2
-1.5
-1
-0.5
Vin (V)
Vik (V)
21
Specifications GAL16V8
GAL 16V8D-10 (and Slower): TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS
Normalized Tpd vs Vcc
1.2 1.2 RISE FALL
Normalized Tpd
1.1
PT H->L PT L->H
Normalized Tco
Normalized Tsu
1.1
1.1
PT H->L PT L->H
0.9
0.9
0.9
0.8 4.50
4.75
5.00
5.25
5.50
0.8 4.50
4.75
5.00
5.25
5.50
0.8 4.50
4.75
5.00
5.25
5.50
Normalized Tpd
Normalized Tco
Normalized Tsu
PT H->L PT L->H
1.2
RISE FALL
PT H->L PT L->H
-25
25
50
75
100
125
-25
25
50
75
100
125
-25
25
50
75
100
125
Temperature (deg. C)
Temperature (deg. C)
Temperature (deg. C)
RISE FALL
RISE FALL
8 6 4 2 0 -2 -4 -6 0 50
RISE FALL
8 6 4 2 0 -2 -4
RISE FALL
100
150
200
250
300
50
100
150
200
250
300
22
Specifications GAL16V8
GAL 16V8D-10 (and Slower): TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS
Vol vs Iol
0.6 5 4
Voh vs Ioh
4
Voh vs Ioh
3.8
Voh (V)
Voh (V)
0 10 20 30 40 50
0.4
Vol (V)
3 2
3.6
3.4 3.2
0.2
1 0 0 10 20 30 40
3 0 1 2 3 4
Normalized Icc
Normalized Icc
Normalized Icc
-25 0 25 50 75 100 125
1.1
0.9
0.8 4.50
4.75
5.00
5.25
5.50
0.7 -55
Temperature (deg. C)
Frequency (MHz)
Iik (mA)
0 0.5 1 1.5 2 2.5 3 3.5 4
20 30 40 50
60 -2 -1.5 -1 -0.5 0
Vin (V)
Vik (V)
23
Specifications GAL16V8
GAL 16V8C-5/-7: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS
Normalized Tpd vs Vcc
1.2 1.2
Normalized Tpd
Normalized Tco
1.1
Normalized Tsu
PT H->L PT L->H
1
PT H->L
1.1
PT L->H
1
0.9
0.9
0.9
Normalized Tpd
Normalized Tco
Normalized Tsu
PT H->L PT L->H
RISE FALL
PT H->L PT L->H
-55
-25
-55
-25
25
50
75
25
50
100
125
75
100
125
100
Temperature (deg. C)
Temperature (deg. C)
Temperature (deg. C)
-0.25
-0.25
-0.5
-0.5
RISE
-0.75
RISE
-0.75
FALL
-1 1 2 3 4 5 6 7 8
FALL
-1 1 2 3 4 5 6 7 8
FALL
4 2 0 -2 0 50 100 150 200 250 300
RISE
6 4 2 0 -2 0 50
RISE FALL
100
150
200
250
300
24
125
-55
-25
50
25
75
Specifications GAL16V8
GAL 16V8C-5/-7: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS
Vol vs Iol
2 5 4
Voh vs Ioh
4.25
Voh vs Ioh
1.5
Voh (V)
3 2 1 0
Voh (V)
Vol (V)
3.75
0.5
3.5
3.25 10.00 20.00 30.00 40.00 50.00 0.00 1.00 2.00 3.00 4.00
0.00
Iol (mA)
Ioh(mA)
Ioh(mA)
Normalized Icc
Normalized Icc
1.10
Normalized Icc
1.00
0.90
-55
-25
25
50
75
100
125
25
50
75
100
Temperature (deg. C)
Frequency (MHz)
10
Iik (mA)
Vin (V)
Vik (V)
25
Specifications GAL16V8
GAL 16V8B-7/-10: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS
Normalized Tpd vs Vcc
1.2 1.2
Normalized Tpd
Normalized Tco
1.1
Normalized Tsu
PT H->L PT L->H
1
PT H->L
1.1
PT L->H
1
0.9
0.9
0.9
Normalized Tpd
Normalized Tco
Normalized Tsu
PT H->L PT L->H
RISE FALL
PT H->L PT L->H
-55
-25
25
50
75
100
100
125
125
-55
-25
25
50
75
100
Temperature (deg. C)
Temperature (deg. C)
Temperature (deg. C)
-0.5
-0.5
-1
-1
RISE
-1.5
RISE
-1.5
FALL
-2 1 2 3 4 5 6 7 8
FALL
-2 1 2 3 4 5 6 7 8
6 4 2 0 -2 0 50
FALL
RISE
8 6 4 2 0 -2
RISE FALL
100
150
200
250
300
50
100
150
200
250
300
26
125
-55
-25
25
50
75
Specifications GAL16V8
GAL 16V8B-7/-10: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS
Vol vs Iol
1 5 4
Voh vs Ioh
4.5
Voh vs Ioh
0.75
4.25
Voh (V)
3 2 1 0
0.5
Voh (V)
Vol (V)
0.25
3.75
3.5 10.00 20.00 30.00 40.00 50.00 60.00 0.00 1.00 2.00 3.00 4.00
0.00
Iol (mA)
Ioh(mA)
Ioh(mA)
Normalized Icc
Normalized Icc
1.10
1.1
Normalized Icc
-55 -25 0 25 50 75 100 125
1.00
0.90
0.9
0.8
Temperature (deg. C)
Frequency (MHz)
Iik (mA)
Vin (V)
Vik (V)
27
Specifications GAL16V8
GAL 16V8B-15/-25: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS
Normalized Tpd vs Vcc
1.2 1.2
Normalized Tpd
1.1
Normalized Tco
Normalized Tsu
PT H->L PT L->H
1
PT H->L
1.1
PT L->H
1
0.9
0.9
0.9
Normalized Tpd
Normalized Tco
Normalized Tsu
PT H->L PT L->H
RISE FALL
PT H->L PT L->H
25
50
75
100
125
-55
-25
25
50
75
100
125
-55
-25
25
50
75
100
125
Temperature (deg. C)
Temperature (deg. C)
Temperature (deg. C)
-0.5
-0.5
-1
-1
RISE
-1.5
RISE
-1.5
FALL
-2 1 2 3 4 5 6 7 8
FALL
-2 1 2 3 4 5 6 7 8
RISE FALL
10 8 6 4 2 0 -2
RISE FALL
8 6 4 2 0 -2 0 50
100
150
200
250
300
50
100
150
200
250
300
28
Specifications GAL16V8
GAL 16V8B-15/-25: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS
Vol vs Iol
2 5 4
Voh vs Ioh
4.25
Voh vs Ioh
1.5
Voh (V)
3 2 1 0
Voh (V)
Vol (V)
3.75
0.5
3.5
3.25 10.00 20.00 30.00 40.00 50.00 60.00 0.00 1.00 2.00 3.00 4.00
0.00
Iol (mA)
Ioh(mA)
Ioh(mA)
Normalized Icc
Normalized Icc
1.10
1.1
Normalized Icc
-55 -25 0 25 50 75 100 125
1.00
0.90
0.9
0.8
Temperature (deg. C)
Frequency (MHz)
10
Iik (mA)
Vin (V)
Vik (V)
29
Copyright 1996 Lattice Semiconductor Corporation. E2CMOS, GAL, ispGAL, ispLSI, pLSI, pDS, Silicon Forest, UltraMOS, Lattice Logo, L with Lattice Semiconductor Corp. and L (Stylized) are registered trademarks of Lattice Semiconductor Corporation (LSC). The LSC Logo, Generic Array Logic, InSystem Programmability, In-System Programmable, ISP, ispATE, ispCODE, ispDOWNLOAD, ispGDS, ispStarter, ispSTREAM, ispTEST, ispTURBO, Latch-Lock, pDS+, RFT, Total ISP and Twin GLB are trademarks of Lattice Semiconductor Corporation. ISP is a service mark of Lattice Semiconductor Corporation. All brand names or product names mentioned are trademarks or registered trademarks of their respective holders. Lattice Semiconductor Corporation (LSC) products are made under one or more of the following U.S. and international patents: 4,761,768 US, 4,766,569 US, 4,833,646 US, 4,852,044 US, 4,855,954 US, 4,879,688 US, 4,887,239 US, 4,896,296 US, 5,130,574 US, 5,138,198 US, 5,162,679 US, 5,191,243 US, 5,204,556 US, 5,231,315 US, 5,231,316 US, 5,237,218 US, 5,245,226 US, 5,251,169 US, 5,272,666 US, 5,281,906 US, 5,295,095 US, 5,329,179 US, 5,331,590 US, 5,336,951 US, 5,353,246 US, 5,357,156 US, 5,359,573 US, 5,394,033 US, 5,394,037 US, 5,404,055 US, 5,418,390 US, 5,493,205 US, 0194091 EP, 0196771B1 EP, 0267271 EP, 0196771 UK, 0194091 GB, 0196771 WG, P3686070.0-08 WG. LSC does not represent that products described herein are free from patent infringement or from any third-party right. The specifications and information herein are subject to change without notice. Lattice Semiconductor Corporation (LSC) reserves the right to discontinue any product or service without notice and assumes no obligation to correct any errors contained herein or to advise any user of this document of any correction if such be made. LSC recommends its customers obtain the latest version of the relevant information to establish, before ordering, that the information being relied upon is current. LSC warrants performance of its products to current and applicable specifications in accordance with LSCs standard warranty. Testing and other quality control procedures are performed to the extent LSC deems necessary. Specific testing of all parameters of each product is not necessarily performed, unless mandated by government requirements. LSC assumes no liability for applications assistance, customers product design, software performance, or infringements of patents or services arising from the use of the products and services described herein. LSC products are not authorized for use in life-support applications, devices or systems. Inclusion of LSC products in such applications is prohibited. LATTICE SEMICONDUCTOR CORPORATION 5555 Northeast Moore Court Hillsboro, Oregon 97124 U.S.A. Tel.: (503) 681-0118 FAX: (503) 681-3037 http://www.latticesemi.com
November 1996