VLSI Testing

Introduction I t d ti

Virendra Singh
Indian Institute of Science Bangalore
virendra@computer.org

E0 286: Testing & Verification of SoC Design Lecture 3 (Jan 15, 2011)
Jan 15, 2010 E0-286@SERC 1

Importance of Formal Verification

Simulation
Can be applied in any design level But quality of verification fully depends on Simulation Patterns
Corner cases may be missed Random is just random and does not cover corner cases

Emulation
Implement on FPGA or other programmable device need lot of preparation Still verification quality fully depends on Simulation Patterns corner cases problem remains P tt bl i Famous bug: Pentium Floating point bug - $500 m
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Design Verification
Specification

Automatic Implementation (Synthesis)

Simulation with Checkers/ drivers S u at o Simulation Based ased Verification

Formal Specification Property checking Equivalence Checking Formal Verification

Correct by Correct-by Construction Implementation

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Simulation-Based Verification

Bug

Bug

Bug

Bug g

Bug Bug

Initial State

Bug

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Simulation Vs Formal Verification

Simulation/emulation Formal Verification

o Cannot cover all cases o C Corner cases may be b missed o Essential method and good for initially debugging
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Equivalent to all case simulation No N corner case w.r.t t given property

Simulation vs Formal Verification

Program testing can be used to show the presence of the bugs, but never to show the absence! (E.W. Dijkstra)

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Simulation Vs Formal Verification

Example: p
Exclusive-OR circuit z = (~x & y) + (x & ~y)

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Simulation Vs Formal Verification

Transform the formulae for circuit to the one for specification by mathematical reasoning z = ~b + ~c b b = ~x + ~a c = ~a + ~y y a = ~x + ~y z = ~b + ~c = ~(~x + ~a) + ~(~x + ~y) ( x a) ( x y) =a&x+a&y = (~x + ~y) & x + (~x + ~y )& y = x & ~y + ~x & y All transformation are based on axioms and theorems Mathematical proof of correctness of design
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Formal Verification
Techniques Deductive Verification (Theorem proving)
Uses axioms, rules to prove system correctness Difficult and time consuming

Model Checking
Automatic technique to prove correctness of concurrent systems Symbolic algorithms (using BDD)

Equivalence Checking
Check if two circuits are equivalent

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Verification vs. Test

Verification
Verifies V ifi correctness of f design. Performed by simulation, hardware emulation, or h d l ti formal methods.

Test
Verifies V ifi correctness of f manufactured hardware. Two-part process: 1. Test generation: software process executed once during design 2. Test application: electrical tests applied to hardware Test application performed on every manufactured device. Responsible for quality of devices.
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Performed once prior to p manufacturing. Responsible for quality of design. g

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Problems of Ideal Tests

Ideal tests detect all defects produced in th i the manufacturing process. f t i Ideal tests pass all functionally good devices. Very large numbers and varieties of y g possible defects need to be tested. Difficult to generate tests for some real defects. Defect-oriented testing is an open problem problem.
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Real Tests
Based on analyzable fault models, which may not map on real defects. defects Incomplete coverage of modeled faults due to high complexity. Some good chips are rejected. The fraction (o percentage) of such chips s called the (or pe ce tage) o suc c ps is ca ed t e yield loss. p p ( Some bad chips pass tests. The fraction (or percentage) of bad chips among all passing chips is called the defect level.
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Thank You
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