Pattern Recognizer: 01110

Verilog Code for Device

`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 15:51:40 01/09/2013 // Design Name: // Module Name: PatternRecognizer // Project Name: PatternRecognizer // Target Devices: Any // Tool versions: // Description: You may use information at // http://www.asic-world.com/tidbits/verilog_fsm.html // Using Single Always For Sequential, Combo And Output Logic // // Dependencies: Johannah :D // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module PatternRecognizer( input clock, input pattern, input reset, input enable, output recognizer );

parameter parameter parameter parameter parameter

IDLE STATE0 STATE1 STATE2 STATE3

= = = = =

5'b00001; 5'b00010; 5'b00100; 5'b01000; 5'b10000;

reg recognizer; reg[4:0] state; always @(posedge clock) begin if (enable && !reset) begin case (state) IDLE: if (!pattern) begin state <= STATE0; recognizer <= 0; end else begin recognizer <= 0; end STATE0: if (pattern) begin state <= STATE1; recognizer <= 0; end else begin recognizer <= 0; state <= STATE0; end STATE1: if (pattern) begin state <= STATE2; recognizer <= 0; end else begin recognizer <= 0; state <= STATE0; end STATE2: if (pattern) begin state <= STATE3; recognizer <= 0; end else begin recognizer <= 0; state <= STATE0; end STATE3: if (pattern) begin state <= IDLE; recognizer <= 1; end else begin state <= STATE0; recognizer <= 1; end default: state <= IDLE; endcase end else begin state <= IDLE; recognizer <= 0; end end endmodule

Verilog Code for Test Bench

`timescale 1ns / 1ps //////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 16:15:31 01/09/2013 // Design Name: PatternRecognizer

// Module Name: D:/ACADS/ECE 195/PatternRecognizer/PatternRecognizer_tb.v // Project Name: PatternRecognizer // Target Device: // Tool versions: // Description: // // Verilog Test Fixture created by ISE for module: PatternRecognizer // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // //////////////////////////////////////////////////////////////////////////////// module PatternRecognizer_tb; // Inputs reg clock; reg pattern; reg reset; reg enable; // Outputs wire recognizer; // Instantiate the Unit Under Test (UUT) PatternRecognizer uut ( .clock(clock), .pattern(pattern), .reset(reset), .enable(enable), .recognizer(recognizer) ); initial begin // Initialize Inputs clock = 0; pattern = 0; reset = 0; enable = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here #20 pattern = 0; #20 pattern = 1; #20 pattern = 0; #20 pattern = 1; #20 pattern = 0; #20 pattern = 1; #20 pattern = 1; #20 pattern = 1; #20 pattern = 0; #20 pattern = 1; #20 pattern = 1; #20 pattern = 0; #20 pattern = 1; #20 pattern = 1; #20 pattern = 0; #20 pattern = 1; #20 pattern = 1; #20 pattern = 1; #20 pattern = 0; #20 pattern = 0; #20 pattern = 0;

#20 #20 #20 #20 #20 #20 #20 #20 #20 #20 #20 #20 #20 #20 #20 #20 #20 #20

pattern pattern pattern pattern pattern pattern pattern pattern pattern pattern pattern pattern pattern pattern pattern pattern pattern pattern

= = = = = = = = = = = = = = = = = =

1; 0; 1; 0; 1; 1; 1; 0; 1; 1; 1; 0; 0; 0; 0; 1; 1; 1;

enable = 1; reset = 0;

// Add stimulus here #20 pattern = 0; #20 pattern = 1; #20 pattern = 0; #20 pattern = 1; #20 pattern = 0; #20 pattern = 1; #20 pattern = 1; #20 pattern = 1; #20 pattern = 0; #20 pattern = 1; #20 pattern = 1; #20 pattern = 0; #20 pattern = 1; #20 pattern = 1; #20 pattern = 0; #20 pattern = 1; #20 pattern = 1; #20 pattern = 1; #20 pattern = 0; #20 pattern = 0; #20 pattern = 0; #20 pattern = 1; #20 pattern = 0; #20 pattern = 1; #20 pattern = 0; #20 pattern = 1; #20 pattern = 1; #20 pattern = 1; #20 pattern = 0; #20 pattern = 1; #20 pattern = 1; #20 pattern = 1; #20 pattern = 0; #20 pattern = 0; #20 pattern = 0; #20 pattern = 0; #20 pattern = 1; #20 pattern = 1; #20 pattern = 1; reset = 1; enable = 0;

// Add stimulus here #20 pattern = 0; #20 pattern = 1; #20 pattern = 0; #20 pattern = 1; #20 pattern = 0; #20 pattern = 1; #20 pattern = 1; #20 pattern = 1; #20 pattern = 0; #20 pattern = 1; #20 pattern = 1; #20 pattern = 0; #20 pattern = 1; #20 pattern = 1; #20 pattern = 0; #20 pattern = 1; #20 pattern = 1; #20 pattern = 1; #20 pattern = 0; #20 pattern = 0; #20 pattern = 0; #20 pattern = 1; #20 pattern = 0; #20 pattern = 1; #20 pattern = 0; #20 pattern = 1; #20 pattern = 1; #20 pattern = 1; #20 pattern = 0; #20 pattern = 1; #20 pattern = 1; #20 pattern = 1; #20 pattern = 0; #20 pattern = 0; #20 pattern = 0; #20 pattern = 0; #20 pattern = 1; #20 pattern = 1; #20 pattern = 1; $finish; end always begin #10 clock = !clock; end endmodule

References http://www.asic-world.com/tidbits/verilog_fsm.html Using Single Always For Sequential, Combo And Output Logic http://www-inst.eecs.berkeley.edu/~cs150/Documents/FSM.pdf http://www.cse.nd.edu/courses/cse20221/www/handouts/L17_FSM%20Design%20Example%20with%20Verilo g.pdf