Design of 8-Bit Serial Real-time Decoder Based on Complex Programmable Logic Device

Xiao Wang* Baiyang Cao North China Institute of Aerospace Engineering, Langfang, Hebei, China, 065000 Abstract
This paper is aimed at the practical design method of 8-Bit Serial Real-time Decoder Based on Complex Programmable Logic Device (CPLD). The design method is simple and novel. The decoder decodes the serial instruction-code from the land control center to the test system in the water adopting the Serial Peripheral interface agreement, in order to control various functions modules among the test system in the water, which include seven functions modules and each module control 8 kind of instructions real time. In the 8-Bit Serial code, the low four bits are the addresses, and the high four bits are instruction. Through the computer simulation and the actual system use, it achieves the design requirement of low error rate, stable operation, and high reliability.[1,2,3] Key words: Real-time Encoder/Decoder ; Programmable Logic Device; interface Serial; Complex Serial Peripheral
Fig.1. The design schematic diagram of 8-Bit Serial Real-time Decoder

technology of FPGA and CPLD, the design of 8-Bit Serial Real-time Decoder Based on Complex Programmable Logic Device affords us an important way to solve the actual problem.[4,5,6]

2. Principle
The design schematic diagram of 8-Bit Serial Real-time Decoder Based on Complex Programmable Logic Device shows in figure 1:

1. Introduction
In the application of the under-water test system, it requires a design of decoder, which receives the serial instruction to control the seven functions modules in the test system from the forward computer. Each functions module includes 8 kinds of instructions and it requests the decoder volume to be small, can fast real-time complete the decoding function, however, selecting the ready-made decoder is not able to satisfy the request. The development direction of number system design is facing the quick speed, the big capacity, the small volume, and the light weight. With the rapid development of ASIC, especially the
* Corresponding author. Tel.:+86 316 2202807; E-mail address:w_wxx@163.com (W. Xiao).

This decoder receives the serial data instruction, therefore must consider how accepts this number that is to say that which serial general agreement is adopted. The Serial Peripheral interface is accepted because its one kind high speed, entire duplex, synchronized correspondence main line. After the definite communication way, then turns the serial data to the parallel data through the data transformation and the data latch. The latch outputs the eight-bits data, the low four bits may produce 16 kinds of pin choose signals (this article only choose 7 kinds) to select various functions module by the decoder, and the high four bits is elected to pass the function module as the

978-1-4244-4131-0/09/$25.00 2009 IEEE

instruction-code, may produce 16 kind of instructioncodes (this article only use 8 kinds) to pass to receive real-time the instruction-code, and completes the control of land control center to he system various functions module in the water tests system. CPLD component interior work succession shows like figure 2.

Fig.2. CPLD component interior work sequence in time

As show in figure 2, when pin signal for low level, the data starts to transmit, the transformation module change 8-bits serial data to 8-bits parallel data; When pin signal for high level, the low 4-bits of the parallel data are transmitted to the decoding module, after the decoding process, the output signal is took as the chip selected signal of each concrete work module, which is effective for the low level; and the high 4-bits are transmitted to the selected module to complete the real-time control to the assigned module. The CPLD component schematic diagram in the design of 8-bits serial codes real-time decoders shows in the following figure 3.

process(clk,indata) begin if (clk'event and clk='1') then if (pin='1') then pianxuan(6 downto 0)<="ZZZZZZZ"; data (3 downto 0)<="ZZZZ"; else q(0)<=d_in; for i in 1 to 7 loop q(i)<=q(i-1); end loop; end if; end if; if (pin='1') then data(3 downto 0)<=q(3downto 0); indata(3 downto 0)<=q(7 downto 4); end if; case indata is when"0001"=>pianxuan<="1111110"; when"0010"=>pianxuan<="1111101"; when"0101"=>pianxuan<="1111011"; when"1001"=>pianxuan<="1110111"; when"0011"=>pianxuan<="1101111"; when"0110"=>pianxuan<="1011111"; when"1100"=>pianxuan<="0111111"; when"0000"=>pianxuan<="1111111"; when"1111"=>pianxuan<="0000000"; when others=>pianxuan<="XXXXXXX"; end case; end process; end jincheng;

3.2 Result of Simulation

Result of Simulation shows like figure 4 and figure 5.

Fig.3. The CPLD component schematic diagram

3. Design and Simulation

3.1 Code Design
Library ieee; use ieee.std_logic_1164.all; entity zhengti is port (d_in,pin,clk:in std_logic; data: out std_logic_vector(3 downto 0); pianxuan:out std_logic_vector(6 downto 0)); end zhengti; architecture jincheng of zhengti is signal q:std_logic_vector(7 downto 0); signal indata:std_logic_vector(3 downto 0); begin

Fig.4. Result of Simulation

actual system application confirmation, it has achieved the request of the low error rate, stable work, and reliable design. This article aims at the command decoder which points at the concrete practical application designs, and has its particularity, but also provides one simple, novel, reliable design mentality and design method.

5. References
[1]ZOU Yisong, LIU Yufeng, and BAI Tingzhu. Photoelectric Imaging Principle[M] . Beijing: Pressing House of Beijing Science and Technology University,1997. [2] Weisfield R L , Hartney M A , Street R A , et al. New amorphous silicon image sensor for X- ray diagnostic medical imaging applications . Proceedings of SPIE , 1998 , 3336 : 444 452. [3] Samei E. Image quality in two phosphor- based flat panel digital radiographic detectors . Medical Physics , 2003 , 30 (7) : 1747 1757. [4] Kundel R L. Van M. Physics and psychophysics in handbook of medical imaging [M]. American: SPIE Press, 2000. 269 [5] LU Hongnian, ZHENG Zhaorui. Signal and Testing System[M] . Beijing: National Protection Pressing House,1988. [6] Kenneth R , Leman C. Digital image processing[M] . Beijing: Tsinghua University Pressing House, 1998.

Fig.5. Result of Simulation

Through the above two profiles, pin pulls are pulled low and high many times, under the function of the latch, may output the integrality order, not appear the mistranslation, the designed program achieve the function of 8-bits serial codes real-time decoders.

4. Conclusions
This article has designed 8-bits serial codes realtime decoders using the CPLD component, and has carried on the top layer module programming using the VHDL language. Through the simulation and experiment of each part of modules, as well as the