By Rodger H.

Hosking
Field programmable gate arrays (FPGAs) are allowing the use of open-architecture, board-level DSP products in application areas that previously required custom board designs. Few areas of DSP technology have been more affected by this trend than software radio. In this article Rodger shows how FPGA technology can be used in the design of digital radio systems, to allow the processing of faster sampling rates, and to allow the radio system to handle more simultaneous channels. communications standard. The proliferation of sophisticated digital voice and data protocols requires: s s s s s decoding convolution framing error correction vocoding encounters a problem that cant be solved within the software, the hardware engineer is contacted and asked to make the necessary changes to the underlying logic design. However, newer FPGAs can now be designed at a much higher level However, during the last five years, FPGA gate density has nicely followed Moores law doubling approximately every year and a half, and recently-announced devices are now boasting 10 million gates! These new FPGAs are typically structured as logic cells, which are equipped with memory, and can be combined to perform the math functions needed to implement DSP operations. The high-density of these logic cells permits the design of a wide range of basic cores that support: s fast multiplication, by computing partial products in parallel s fast FFT processing, using block memory s fast FIR filtering, using distributed memory The tools provided to users of these new high-density FPGAs support parameterizable cores that accept bit-width definitions, and automatically generate customized core architectures. By adjusting the parameters, a user can tune the core to provide the signal processing accuracy needed for any particular application thus making optimum use of the available gates in the FPGA. The design and debug tools can be used by software engineers, as well as hardware engineers A wide range of front-end design tools is now available to suit the input preferences of both hardware and software engineers. These include: s block diagram system generators s schematic processors s high-level language compilers for Verilog and VHDL The time spent debugging FPGA designs has also been drastically reduced by new simulators that: s execute faster s are more accurate s are easier to use Copyright 2000 / All rights reserved

Adding further to the DSP processing load is the steady increase in the sampling rate requirements. To support new high-bandwidth applications, such as wideband CDMA: s DSP chips are being moved closer and closer to the antenna s DSP chip clock rates have been increased to over 200 MHz s DSP chips are now being equipped with multiple hardware multipliers However, these techniques have made DSP chips very expensive (and very power-hungry) and engineers are now looking for ways to reduce the workload on the DSP chips. Programmable logic has traditionally been designed at the gate and register level Programmable logic devices (PLDs) and programmable gate arrays (PGAs) have been widely used in both COTS and custom designs for over 20 years, as a convenient and flexible replacement for gates, control logic, registers, memory, and state machines. In these applications the most important design issues are typically: s critical propagation delay path analysis s pin locking s synchronization of input signals s the development of suitable test vectors. Because hardware engineers understand these issues better than most software engineers, PLD and PGA design, simulation, optimization and testing has typically been done by hardware engineers in the project team. Once the hardware design is completed, the programmable logic firmware is not changed, unless some new hardware feature is needed. If a software engineer

n traditional software radio receiver systems, the incoming radio signal is translated and filtered to produce a baseband signal. This baseband signal is then sampled to produce a stream of complex samples that represents its time domain waveform, and that sample stream is sent to a DSP that handles the demodulation task, as well as the analysis of the signal being received. Use of DSPs in military intelligence The DSP in a signal intelligence receiver is typically used to: s classify a signal, by first performing a spectral analysis to estimate what type of modulation was used s apply demodulation algorithms, to determine if useful information is extracted such as intelligible speech or a meaningful data stream Other important tasks for the DSP include: s s s s s s decryption data storage channel switching signal routing to other systems logging activity routing of audio or digital data streams to an operator, for listening or display

Use of DSPs in cellular base stations The DSP in a cellular base station might perform any of these tasks plus some additional ones. In fact, the number of additional tasks grows with each new Reprinted from VMEbus Systems / June 2000

Third-parties are now offering cores Third-party vendors are now offering high-level cores to complement the standard cores supplied by the FPGA vendors. These cores range from complete DSP processors to application-specific blocks, such as high-speed internet modems. Using FPGAs to do signal processing faster Of even greater significance, the digital signal processing capability of an FPGA is often greater than a general purpose DSP chip. For example, if a wideband FIR digital filter requires 32 MACs (multiply/accumulate operations) within a single clock cycle, a general purpose DSP with only 2 multipliers will fall far short of the mark. However, an FPGA can easily be configured to provide 32 MAC cores, thus allowing all 32 MAC operations to be done in parallel, in a single clock cycle. Inside a software radio system Figure 1 shows the basic elements of a typical software radio system. The front end consists of an analog RF stage that performs a frequency translation from high frequencies down to frequencies that can be sampled with an A/D converter. The digital sample stream from the A/D converter is then further translated down to DC, using: s a digital local oscillator s a digital mixer The digital local oscillator The local oscillator is a direct digital frequency synthesizer, sometimes called a numerically controlled oscillator. It uses a digital phase accumulator and sine/cosine lookup tables to generate streams of digital samples that represent sine and cosine signals. The sample rate of the local oscillators output is exactly equal to the A/D sample clock frequency. The local oscillators output frequency is determined by setting the amount of phase advance per sample, and is programmable from DC up to half of the A/D sample frequency, with excellent resolution. The digital mixer The digital mixer employs a complex digital multiplier to compute the product of: s the stream of samples from the A/D converter s the stream of sine/cosine samples from the local oscillator Copyright 2000 / All rights reserved

This produces a single-sideband, complex frequency translation down to DC. The FIR low-pass filter The FIR low-pass filter accepts the output stream from the digital mixer and uses decimation to pass all signals from 0 Hz up to a programmable cutoff frequency or bandwidth rejecting all signals above that cutoff frequency. The demodulator The output of the FIR filter then enters the DSP section, where it encounters a DSPbased demodulator that demodulates the baseband signal, executing different algorithms to handle AM, FM or PSK signals. The decoder The demodulated signal must often be further processed by the DSP to: s decode digital data s perform error correction s apply decompression The analyzer Once the received signal content is extracted, the DSP can perform analysis and make decisions about recording, forwarding or playing the signal into an operators headphone. Software radio is very versatile The extreme versatility of being able to apply new demodulation, decoding, analysis and control functions (by simply reprogramming the DSP chip) has made software radio technology welcome in virtually every type of communications system.
Antenna Digital down converter FIR low pass filter

Using FPGAs to replace DSP software Figure 2 shows an FPGA that has been added to the block diagram of Figure 1 to replace the demodulator and decoder functions that were previously performed by the DSP chip. Examples of cores that might be used to support these functions include: s s s s s Reed-Solomon Viterbi, and convolutional decoders XF-DES encryption blocks FFT processors A-law and -law decoders

With this approach, the FPGA can be used to handle tasks that are beyond the capabilities of a DSP chip. This allows the general-purpose DSP chip (or possibly a RISC chip) to be most effectively deployed to handle complex decision making during the subsequent analysis portion of the processing. Using FPGAs to replace ASICs Not only are FPGAs capable of performing mathematical operations previously performed by DSP chips, new FPGA cores are now becoming available to replace some (or all) of the operations previously provided by ASICs. These include: s s s s s complete digital receivers frequency synthesizers mixers and multipliers FIR and comb filters interpolation and resampling filters

Programmable DSP

RF translator

A/D converter

Digital mixer

Demod

Decode

Analysis/ control

A/D clock

Digital local oscillator

Figure 1

Antenna Digital down converter FIR low pass filter FPGA

Programmable DSP

RF translator

A/D converter

Digital mixer

Demod

Decode

Analysis/ control

A/D clock

Digital local oscillator

Figure 2
Reprinted from VMEbus Systems / June 2000

or HF analog signals with bandwidths up to 35 MHz. The 4 sample streams from each of these 4 A/D converters can be routed to one or more of eight Graychip GC4016 digital down converter chips. Each of these down converters provides 4 narrowband digital receivers, for a total of 32 receivers. Each of these receivers is independently-tunable (over a range from DC to 35 MHz) and can deliver output bandwidths between 4 kHz and 2 MHz. The output streams from the GC4016 digital receivers are then routed to a pair of Xilinx Virtex-E FPGAs, which format the data streams, and then pack them into 32bit-wide data words, for transfer to the VMEbus DSP board. The VMEbus board Output data from the FPGAs is transferred (as packed 32-bit words) through the VIM (Velocity Interface Mezzanine) interface to synchronous bidirectional FIFOs (BiFIFOs) on the Model 4291 VMEbus DSP board, at rates up to 100 MHz . This Quad C6701 DSP processor board features 4 independent processing nodes, each equipped with: s a Texas Instruments TMS320C6701 DSP s a private, dedicated 100-Mbyte/sec VIM interface

Figure 3 shows how an FPGA can be used to replace all of the digital receiver ASIC functions, including the local oscillator, mixer and FIR filter. The newest FPGAs can handle input sampling rates over 100 MHz exceeding that of many of the commercial digital receiver ASIC chips now on the market. In this system, the FPGA handles all
Antenna

FPGA digital receiver system for COTS Figure 4 shows a new COTS VMEbus board from Pentek that demonstrates how standard off-the-shelf products can take full advantage of digital receiver ASICs, FPGAs, and high-performance DSPs. This board product consists of:

FPGA FIR low pass filter

Programmable DSP

RF translator

A/D converter

Digital mixer

Demod

Decode

Analysis/ control

A/D clock

Digital local oscillator

Figure 3
of the signal processing tasks between the A/D converter and the high-level processor. Indeed, the tight coupling between the digital receiver section and the demodulation function can be extremely useful for implementing synchronous demodulation schemes. s a Model 6230 VIM-4 mezzanine board s a Model 4291 quad DSP VMEbus board The mezzanine board The mezzanine module has 4 Analog Devices AD6644 80 MHz, 14-bit A/D converters each of which can sample RF

Model 6230 32-channel digital receiver mezzanine

Ch 1 input Amp & filter 80 MHz 14-bit A/D Ch 2 input Amp & filter 80 MHz 14-bit A/D Ch 3 input Amp & filter 80 MHz 14-bit A/D Ch 4 input Amp & filter 80 MHz 14-bit A/D

4-channel narrow band receiver

4-channel narrow band receiver

4-channel narrow band receiver

4-channel narrow band receiver

4-channel narrow band receiver

4-channel narrow band receiver

4-channel narrow band receiver

4-channel narrow band receiver

Xilinx Virtex-E FPGA

Xilinx Virtex-E FPGA

VIM mezzanine interface

VIM mezzanine interface

VIM mezzanine interface

VIM mezzanine interface

Control C6701 DSP

32 Mezzanine I/O BI-FIFO C6701 DSP

Control

32 Mezzanine I/O BI-FIFO C6701 DSP

Control

32 Mezzanine I/O BI-FIFO C6701 DSP

Control

32 Mezzanine I/O BI-FIFO

Model 4291 Quad C6701 DSP VMEbus board (partial diagram)

Figure 4
Reprinted from VMEbus Systems / June 2000 Copyright 2000 / All rights reserved

A separate VIM control path allows each DSP to: s program the operating modes and the parameters of the digital down converter parameters on the mezzanine s reconfigure the FPGAs on the mezzanine Three sizes of FPGA are available with the Model 6230 mezzanine board, ranging from 300K gates to 600K gates enough resources to add: s custom demodulation s decoding s signal processing functions Note: This would allow implementation of the architecture shown earlier, in Figure 2. Note: As shown in Figure 4, the Model 6230 mezzanine includes direct connections between the A/D converters and the Xilinx FPGAs. These paths allow the FPGAs to process the A/D samples directly, completely bypassing the digital receiver ASICs. This allows implementation of the architecture shown in Figure 3, allowing the radio system to handle synchronous demodulation schemes. Flexibility and re-usability This COTS software radio architecture shown in Figure 4 supports a wide range

of applications. By using new FPGA design tools and core libraries, system designers can eliminate the need for custom boards. Since FPGA hardware can be radically reconfigured (with no board redesign) the same boards used in a current project could be easily retooled for future projects. As new software radio algorithms are developed, they could first be implemented in software and tested on a DSP chip. This allows the engineer to take full advantage of the wide range of DSP code generation, simulation and optimization tools that are currently available. When the algorithm has been fully tested, it can then be ported to an FPGA. The FPGA would provide faster execution, and would be able to support many parallel channels. Finally (for the transition to high-volume production) the FPGA design could be converted into mask tooling, for a custom ASIC. Reprogramming the FPGAs to handle new functions is more complicated than writing software for a DSP chip. However, this level-of-effort gap is closing. No longer the exclusive domain of the hardware engineer, FPGA design tools are now being used more extensively by software engineers, ensuring that FPGAs will become the mainstream paradigm for future DSP embedded designs.

Rodger H. Hosking is Vice President of Pentek, and was one of the cofounders of the company in 1986. With over 25 years experience in the electronics industry, he previously held the position of engineering manager at Rockland Systems, and its successor company Wavetek Rockland. While there, he was responsible for the development of digital frequency synthesizers, FFT spectrum analyzers, and digital filter products. He designed the first commercial direct digital frequency synthesizer in 1971, and holds patents in frequency synthesis and FFT spectrum analysis techniques. Rodger has a BS degree in Physics from Allegheny College, and a BS and MS in electrical engineering from Columbia University. If you have questions about this article, or if you would like more information about Penteks products, you can contact Pentek at: Pentek 55 Walnut Street Norwood, CA 07648 Tel: 201-818-5900 Fax: 201-818-5904 Email: rodger@pentek.com Web: www.pentek.com

Copyright 2000 / All rights reserved

Reprinted from VMEbus Systems / June 2000