Louisiana State University Department of Electrical & Computer Engineering Updated August 8, 2012 EE4242: VLSI Design Dr.

A. Srivastava, Professor (Email: ashok@ece.lsu.edu) Fall 2012

Objective: The course involves introduction to the design of very large scale integrated circuits based on integration of various disciplines such as MOS devices and processing technology, integrated electronic circuits, digital logic, design disciplines and tools, architectures and algorithms. Every student will be required to complete a chip-level design project in current CMOS technology based on this kind of integrated approach. Prerequisites: EE 2720: Digital Logic II and EE3220 and EE3221: Electronics II Note: Your name will be removed if you do not meet the course requirement and have a letter grade D in any of the prerequisites. Text Book: 1. Jan M. Rabaey, Anantha Chandrakasan and Borivoje Nikolic, Digital Integrated Circuits, Prentice Hall/Pearson, 2003, 2nd edition 2. Class Handouts (to be given during lecture hours only) Reference Books: Neil Weste and David Harris, CMOS VLSI Design A Circuits and Systems Perspective, Pearson/Addison-Wesley, 2011, 4th edition. R. Jacob Baker, CMOS Circuit Design, Layout, and Simulation, IEEE/Wiley Inter -Science, Revised 2nd Edition, 2008. Lab Manual: A. Srivastava, VLSI Design A Laboratory Manual, Rev. 7/09. Other lab instructions and handouts will be given during laboratory hours only. Note: Inform the instructor if you miss the lab due to some reason. You are responsible for any changes and upgrades that are given during lecture hours. Course Syllabus: 1. Introduction (Chapter 1) 2. The Manufacturing Process (Chapter 2) 3. Design Methodology - IC Layout 4. The Devices (Chapter 3) 5. Design Methodology Circuit Simulation 6. The Wire (Chapter 4) 7. The CMOS Inverter (Chapter 5) 8. Designing Combinational Logic Gates in CMOS (Chapter 6) 9. Design Methodology Complex Logic Gates Simulation 10. Design Methodology Layout Techniques for Complex Gates 11. Designing Sequential Logic Circuits (Chapter 7) 12. Design Methodology Characterizing Logic and Sequential Cells 13. Design Methodology Design Verification 14. Design Methodology Verification and Test of Manufactured Circuits

Homework, Project and Laboratory: Regular homework assignments will be given. Every student will be required to work on a well-defined team (minimum two) project. The design project will be implemented during laboratory hours. Every group will be required to class room presentation of the project. Note: The laboratory is an integral part of the course. Homework and project will require an extensive use of L-EDIT, B2LOGIC (or equivalent available Logic Simulator) and Cadence/PSPICE programs. The VLSI Lab as you may notice has been upgraded with very high performance Dell Optiplex 755 PCs and 24 inch high resolution monitors. Please keep the lab and working area clean. No food or drink will be allowed in this lab. Lectures and Lab Hours: Lecture (MW): 8.30 - 9.20 AM (2149 Patrick Taylor) Lab (#2 T): 10.30 AM- 12.20 PM (EE125), Lab (#3 T): 1:00 2:50 PM (EE125) and Lab (#4 T): 3:00 4:50 PM (EE125) Grading: Test I: 20% (Midterm Exam: M 10/08/12) Test II: 20% (M: 11/19/12) Final Exam: 20% (Friday Dec 7, 2012; 12.30 2.30 PM) HW: 5% Lab: 35% (Due Date: T 11/27/12 or earlier) _______________ Total: 100% Note: No Make-up test/exam will be given. Office Hours: M W: 1.30 3.30 PM, W: 10.30 11.30 AM (PFTH 3104C, E-mail: ashok@ece.lsu.edu) Project report should be written either individually or jointly in the following format. - Title and Project Description - Full Logic Level Block Diagram - Cell Level Description/Cell library - Logic Level Diagrams and Truth Tables - Logic Level Simulations - Circuit Level Diagram with Relevant Node Numbers - Cadence/PSPICE Simulation Results - Plots of Cell Libraries - Pad Frame with I/O Pin Numbers - Electronic Files in TDB & CIF Extension The project report must be word-processed and submitted in original form (preferably softcopy). The report should also include your power point presentation slides. You may wish to keep a copy of the report for your record.