GOJAN SCHOOL OF BUSINESS & TECHNOLOGY

EDPALAYAM, REDHILLS, CHENNAI-52.

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

MODEL EXAMINATION VL 9212 VLSI DESIGN TECHNIQUES

M.E. - Applied Electronics

Time : Three hours

Maximum : 100 Marks Answer ALL questions

PART A (10 2 = 20 Marks) 1. 2. 3. 4. 5. 6. 7. 8. 9. Give two reasons as to why polysilicon is used as Gate material in VLSI. What is pinch - off? What is its effect? Give Noise margin 0 and Noise margin 1 of a CMOS gate. Mention the drawbacks of pass transistor logic. What is body effect? Show the same for PMOSFET. Placement and routing have to be optimal in VLSI design, why? What is DFT? What is its philosophy? Indicate any two ways to reduce power in a CMOS IC. Differentiate concurrent statements from sequential statements.

10. List the operators used in Verilog. PART B (5 16 = 80 Marks) 11. (a) (i) With the help of structure and transfer characteristic differentiate the working of an enhancement type N-MOSFET from depletion type N-MOSFET. (ii) Briefly explain all the terms. Or (b) (i) (ii) 12. (a) (i) (ii) Explain any two secondary effects of a MOSFET. Illustrate the fabrication steps involved in a twin-tub CMOS IC. (10) Compare the design of a 4 : 1 MUX built using transmission gates with the one built using static CMOS gates. structures.2-I/P (8) Implement the following Boolean gates using static CMOS AND gate, 2-I/P OR gate, 2-I/P Ex-OR gate and 2-I/P Ex-NOR gate. (8) (6) (8) (8) Write the expression for the threshold voltage of a NMOSFET.

Or (b) (i) (ii) 13. (a) (i) (ii) Explain the working of a domino logic. What is meant by transmission gate? Design a 2 1 mux using transmission gate. Comment on the same. it done? Or (b) (i) (ii) 14. (a) (i) (ii) (b) (i) (ii) Discuss the different scaling models that are prevalent in VLSI. Illustrate them with examples. What are the limitations of scaling? Explain. Explain the working of a 4 4 multiplier with examples. Or What is Physical design in VLSI? Elaborate the same. (8) For the circuit shown in Fig. 14 (b), generate, test vectors to detect the s-a-1 and s-a-0 faults shown. Also indicate the other faults covered by the test vectors generated. (8) s-a-1 A B Y C D E s-a-0 (10) (6) (8) (10) (10) (6) Derive an expression for dynamic power dissipation of a CMOS IC. What do you mean by transistor sizing? Clearly answer as to why is (6)

Starting from basics, design and explain a 4 bit high speed adder.(8)

Fig. 14 (b) 15. (a) (i) (ii) Explain functions with suitable examples, with respect to Verilog.(8) Write a Verilog Code for 3 to 8 decoder using gate level primitives.(8) Or (b) (i) (ii) Write a Verilog Code for +ve edge triggered D-Flip-Flop using data flow modeling. Show the waveforms also. (8) Explain the complete flow diagram of digital system design using Verilog (HDL).(8)