SUBJECT CODE: MC9211

SUBJECT NAME: Computer Organization

I M.C.A I SEMESTER REGULATION -2009

UNIT I AND II Part - A & B (Questions and Answers)

STAFF NAME: R.SASIKALA. M.C.A., M.Phil.,

HOD

PRINCIPAL

MC9211 COMPUTER ORGANIZATION UNIT I DIGITAL FUNDAMENTALS Number Systems and Conversions Boolean Algebra and Simplification Minimization of Boolean Functions Karnaugh Map, Logic Gates NAND NOR Implementation.

UNIT II COMBINATIONAL AND SEQUENTIAL CIRCUITS Design of Combinational Circuits Adder / Subtracter Encoder Decoder MUX /DEMUX Comparators, Flip Flops Triggering Master Slave Flip Flop State Diagram and Minimization Counters Registers.

UNIT III BASIC STRUCTURE OF COMPUTERS Functional units Basic operational concepts Bus structures Performance and Metrics Instruction and instruction sequencing Hardware Software Interface Addressing modes Instructions Sets RISC and CISC ALU design Fixed point and Floating point operation.

UNIT IV PROCESSOR DESIGN Processor basics CPU Organization Data path design Control design Basic concepts Hard wired control Micro programmed control Pipeline control Hazards Super scalar operation. UNIT V MEMORY AND I/O SYSTEM Memory technology Memory systems Virtual memory Caches Design methods Associative memories Input/Output system Programmed I/O DMA and Interrupts I/O Devices and Interfaces. TEXT BOOKS: 1. Morris Mano, Digital Design, Prentice Hall of India, 1997. 2. Carl Hamacher, Zvonko Vranesic and Safwat Zaky, Firth Edition, Computer Organization, Tata McGraw Hill, 2002. REFERENCES: 1. Charles H. Roth, Jr., Fundamentals of Logic Design, Jaico Publishing House,

Mumbai, Fourth Edition, 1992. 2. William Stallings, Computer Organization and Architecture Designing for Performance, Sixth Edition, Pearson Education, 2003. 3. David A. Patterson and John L. Hennessy, Computer Organization and Design: The Hardware/Software interface, Second Edition, Morgan Kaufmann, 2002. 4. John P. Hayes, Computer Architecture and Organization, Thrid Edition, Tata McGraw Hill, 1998. PART - A 1. Define Computer organization. Computer organization is concerned with the way the hardware components operate & the way they are connected together to form the computer system. The computer system consists of hardware & software.

2. Define Computer architecture. Computer architecture is concerned with the structure and behavior of the computer as seen by the user It is concerned with the specification of the various functional modules such as processors, memories and structuring them together into a computer system

3. Define Computer design. Computer design is concerned with the hardware of the computer It is concerned with the determination of what hardware should be used and how the parts should be connected.

4. What is a data type? All type of data are represented in the computer registers in the form of binary code The data type found in registers of digital computers may be classified as Numbers used in the arithmetic computations Letters or alphabets used in data processing Discrete symbols 5. What is meant by gray code? Give properties of gray code. A modified binary code in which sequential numbers are represented by expressions that differ only in one bit, to minimize errors. Also known as reflective binary code. Properties : Gray codes are widely used to facilitate error correction in digital communications such as digital terrestrial television and some cable TV systems. 6. How to calculate a Excess-3 code? To convert decimal number into excess-3 form add the number 3 to each decimal digit and then convert the sum to a BCD number.

Excess 3 of 12 is as follows: 12 0001 0010

0011 0011 0100 0101

7. What is error deduction code? Binary information transmitted through some form of communication medium is subjected to external noise that could change bits from 1 to 0 and vise versa. An error detection code is a binary code that detects digital errors during transmission of data. The technique used here is parity bit.

8. What is a Boolean algebra? It is a simple mathematical tool that allows us to describe the relationship between logic circuits outputs and its inputs as an algebraic equation.

9. List the entities of Boolean algebra identities. A+ B = B +A AB = BA A + (B + C) = (A + B) + C A.(BC) = (AB).C A.( B + C ) = AB + AC A+ BC = (A + B) . (A + C) A+ 0 =A A.1=A A+1=1 A.0=0 A+A = 1 A.A = 0 A=A (A+B) = A.B (AB) = A + B A+AB = A+B A+AB = A A(A+B) A A(AB) = AB

10. What are Basic Boolean operations or logic operations AND OR NOT

11. Define K-map.

A karnaugh map is a visual display of the fundamental products solution.

products needed for a sum of

12. Define flip flops Flip flops are binary cells capable of storing one bit of information A flip flop circuit has two outputs: one for the normal value one for the complement value

13. What is combinational circuit? When logic gates are connected together to produce specified output for certain specified combination of input variables with no storage involved the resulting circuit is called combinational logic. A combinational circuit transforms consists of input variable, logic gates and output variable.

14. What is sequential circuit? A sequential circuit is an interconnection of flip flops and gates. The gates by themselves constitute a combinational circuit, but when included with the flip-flops, the overall circuit is classified as a sequential circuit. A sequential circuit consists of a combinational circuit to which memory elements are connected to form a feedback path. The memory elements are devices capable of storing binary information within them. 15. What are the two types of sequential circuit? Synchronous sequential circuit Asynchronous sequential circuit 16. What is synchronous sequential circuit? A synchronous sequential circuit is a system whose behavior can be defined from the knowledge of each signals at discrete instants of time. 17. What is asynchronous sequential circuit? A asynchronous sequential circuit depends upon the order in which each input signal change, and can be affected at any instance of time.

18. What is a state table? A sequential circuit is specified by a state table that relates outputs and next states as a function of inputs and present state to next state is activated by the presence of a clock signal.

19. What does a state table consist of? A state table consist of four sections, they are: Present state This section shows the states of flip-flops A and B at any given time t.

Input section This gives a value of x for each possible present state. Next State This shows the states of the filp=flops one clock period later at time t+1. Output This gives the value of y for each present state and input condition.

20. What is a state diagram? The information available in a state table can be represented graphically in a state diagram. In this type of diagram, a state is represented by a circle, and the transition between states is indicated by directed lines connecting the circles.

21. Given a computer that has a word size of 6-bits, what is the smallest negative number and the largest positive number can represent in each of the following representations? 1. Ones complement 2. Twos complement (a) Largest positive: 011111 (31) (b) Smallest negative: 100000 (-31)

22. Using the basic identities of Boolean algebra, show that xy + xz + yz = xy + xz XY + XZ + YZ = XY + XZ + (1) YZ = XY + XZ + (X+X) YZ = XY + XZ + XYZ + XYZ = XY (1 + Z) + XZ (1 + Y) = XY + XZ 23. Simplify the expression F = ABC + ABC + AC F = ABC + ABC +AC F = AB (C+C) + AC F = AB(1) +AC F = AB + AC 24. What is a half adder? The digital circuit that forms the arithmetic sum of two digits and a previous carry is called a half adder.

25. What is meant by full adder? The digital circuit that forms the arithmetic sum of three digits and a previous carry is called a full adder. 26. What is a multiplexer? Multiplexer is a combinational circuit that receives binary information from one of 2 n input data lines and directs it to a single output line. The selection of a particular input data line is controlled by a set of selection lines. There are 2n input lines and n selection lines whose bit combinations determine which input is selected. A device that combines multiple inputs into an aggregate signal to be transported via a single transmission channel. Synonym multiplexing equipment. 27. What is a demux? The demultiplexer is the inverse of the multiplexer, in that it takes a single data input and n address inputs. It has 2n outputs. The address input determine which data output is going to have the same value as the data input. The same circuit can also be used as a decoder, by using the address inputs as a binary number and producing an output signal on the single output that matches the binary address input. In this application, the data input line functions as a circuit enabler if the circuit is disabled, no output will show activity regardless of the binary input number.

28. What is a register? A register is a group of flip-flops and gates that effect their transition.The flip-flops hold the binary information and the gates control when and how new information is transferred into the register. An n-bit register has a group of n flip-flops and is capable of storing any binary information of n bits.

29. What is meant by shift register? A register capable of shifting its binary information in one or both direction is called a shift register. It consists of a chain of flip-flop in cascade, with output of one flip-flop connected to the input of the next flip-flop. 30. What is a counter and give its uses. A register that goes through a predetermined sequence of states upon the application of input clock pulse is called a counter. Counter are used for: Counting the number occurrences of an event Generating timing signals to control the sequence of operations in digital computers. 31. What is meant by binary counter? A counter that follows the binary number sequence is called a binary counter. An n-bit binary counter is a register of n-flip-flop and gates that follows a sequence of states.

32. What is Overflow Detection? An overflow condition can de detected by observing the carry into the sign bit position and carry out of the sign bit position. If these two carries are not equal, an overflow condition produced.

33.

Define Parity bit? The most common error detection code used is the parity bit. A parity bit is a extra bit included with a binary message to make the total number of 1s either odd or even. The message, including the parity bit is transmitted and then checked at the receiving and for errors.

34.

What is Parity Generator? During transfer of information from one location to another, the parity bit is handled. At the sending end, the message is applied to the parity generator, where the required parity bit is generated.

35.

Define Binary Code? A binary code is a group of n bits that assume up to 2 distinct combinations of 1s and 0s with one combination representing one element of the set that is encoded.

36.

What is Boolean Function? A Boolean function can be expressed algebraically with binary variables, the logic operation symbols, parenthesis and equal sign. For a given value of a variable the Boolean function can be either 1 or 0.

37.

Draw the block diagram for Combinational Circuits?

Combinational Circuit

38.

Why complementing a number representation is needed? Complementing a number becomes as in digital computer for simplifying the subtraction operation and for logical manipulation complements are used.

39.

State the limitations of karnaugh map. i) Generally it is limited to six variable maps (i.e.) more then six variable involving

expressions are not reduced. ii) The map method is restricted in its capability since they are useful for simplifying only Boolean expression represented in standard form.

40.

What are the needs for binary codes? a. Code is used to represent letters, numbers and punctuation marks. b. Coding is required for maximum efficiency in single transmission. c. Binary codes are the major components in the synthesis (artificial generation) of speech and video signals. d. By using error detecting codes, errors generated in signal transmission can be detected. e. Codes are used for data compression by which large amounts of data are transmitted in very short duration of time.

41.

Mention the different type of binary codes?

The various types of binary codes are, 1. BCD code (Binary Coded decimal). 2. Self-complementing code. 3. The excess-3 (Xs-3) code. 4. Gray code. 5. Binary weighted code. 6. Alphanumeric code. 7. The ASCII code. 8. Extended binary-coded decimal interchange code (EBCDIC). 9. Error-detecting and error-correcting code. 10. Hamming code.

42.

List the any two advantages of BCD code?

The advantages of BCD code are a. Any large decimal number can be easily converted into corresponding binary number b. A person needs to remember only the binary equivalents of decimal number from 0 to 9.

43.

List the any two disadvantages of BCD code?

The disadvantages of BCD code are a. The code is least efficient. It requires several symbols to represent even small numbers. b. Binary addition and subtraction can lead to wrong answer.

44. What is the truth table? A truth table lists all possible combinations of inputs and the corresponding outputs.

45. What is half-subtractor? The combinational circuit that performs the subtraction of two bits are called a half-sub tractor.

46. What is a full-subtractor? The combinational circuit that performs the subtraction of three bits are called a half- sub tractor.

47.

What is Binary parallel adder? A binary parallel adder is a digital function that produces the arithmetic sum of two binary numbers in parallel.

48. What is BCD adder? A BCD adder is a circuit that adds two BCD digits in parallel and produces a sum digit also in BCD.

49. What is decoder? A decoder is a combinational circuit that converts binary information from n input lines to a maximum of 2n unique output lines.

50.

List different types of flip-flops.

i) SR flip-flop ii) Clocked RS flip-flop iii) D flip-flop

iv) T flip-flop v) JK flip-flop vi) JK master slave flip-flop.

51

Write the uses of a shift register.

i) Temporary data storage ii) Bit manipulations.

EXPLAIN BOOLEAN ALGEBRA List the advantages and disadvantages of BCD code. The advantages of BCD code are a. Any large decimal number can be easily converted into corresponding binary number b. A person needs to remember only the binary equivalents of decimal number from 0 to 9. c. Conversion from BCD into decimal is also very easy. The disadvantages of BCD code are a. The code is least efficient. It requires several symbols to represent even small numbers. b. Binary addition and subtraction can lead to wrong answer. c. Special codes are required for arithmetic operations. d. This is not a self-complementing code. e. Conversion into other coding schemes requires special methods.

Explain Karnaugh Map with Examples? Simplifying Circuits with Karnaugh Maps The way of finding the simplest solution to a logic gate problem is the use of the Karnaugh map. Here is a truth table for an output with four different inputs, or a four-bit word. A word is a set of binary digits. Computers use sixteen or thirty-two bit words, which means that they process groups of 16 or 32 binary digits. 8 binary digits is called a byte. Here we have a group of four digits, not a very good medium for a computer. A bit is a binary digit, 1 or 0 (ON or OFF) Look at this truth table: A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Q 0 1 0 1 0 1 0 1 0 0 1 1 1 0 0 0

There are seven rows in this truth table where the output is 1. So we can write the Boolean expression:

we can simplify it using the methods we saw above, but Karnaugh maps are much more helpful in this case. Notice the order of the letters. D is the most significant bit, and A is the least. In the Karnaugh map we split up the truth table into a 4 x 4 matrix, with the rows identified by DC, and the columns identified with BA. Notice the order of the two bit words. One bit is the same as the neighbors. The sum of adjacent bits has to be different.

If you cant remember these, just learn the order, 00, 01, 11, 10. We need to fill the table from the truth table above. For example 00, 01 (Black arrows) gives a 1 and 01, 10 (Blue arrows) gives a 0.

So we fill the table:

We can identify clusters of 1s:

These clusters have been marked P, R, S. Let us look at group P. We get a 1 in both cells when DC is 10. We get a 1 in one of the cells when BA = 11, or when BA = 10. So we can write the Boolean expression for cluster P as:

We can rewrite this as:

Now we can put P, R, and S together: Design a Binary adder Subtractor Circuit. The addition and subtraction operations can be combined into one common circuit by including a exclusive OR gate with each full adder. A 4 bit adder subtractor circuit A3 A2 A1 A0

The mode input M controls the operation. When M=0 the circuit is an adder. When M=1 the circuit becomes a subtractor.Each exclusive or gate receives input M and one of the inputs of B. When M=0, we have B+0=B. The Full Adder receives the value of the input carry will be 0,and the circuit performs A plus B. When M=1,we have B+1=B and Co=1.The B inputs are all complemented and a 1 is added through the input carry. The circuit performs the operation A plus the 2s complement of B. For unsigned numbers, this gives A-B if A>=B or the 2s complement of (B-A) if A<B.For signed numbers, the result is A-B provided that there is no Overflow

EXPLAIN DIFFERENT NUMBER SYSTEMS IN DETAIL.

Here's the decimal number system as an example:

Digits (or symbols) allowed: 0-9 Base (or radix): 10 the order of the digits is significant 345 is really 3 x 100 + 4 x 10 +5 x1

3 x 10**2 + 4 x 10**1 + 5 x 10**0 3 is the most significant symbol (it carries the most weight) 5 is the least significant symbol (it carries the least weight)

Binary number system: digits (symbols) allowed: 0, 1 base (radix): 2 each binary digit is called a BIT

the order of the digits is significant numbering of the digits msb n-1 lsb 0

where n is the number of digits in the number

1001 (base 2) is really 1 x 2**3 + 0 x 2**2 + 0 x 2**1 + 1 x 2**0 9 (base 10)

11000 (base 2) is really 1 x 2**4 + 1 x 2**3 + 0 x 2**2 + 0 x 2**1 + 0 x 2**0 24 (base 10)

Octal number system:

digits (symbols) allowed: 0-7 base (radix): 8

the order of the digits is significant

345 (base 8) is really 3 x 8**2 + 4 x 8**1 + 5 x 8**0 192 + 32 + 5

229 (base 10)

1001 (base 8) is really 1 x 8**3 + 0 x 8**2 + 0 x 8**1 + 1 x 8**0 512 + 0 + 0 + 1

513 (base 10)

Hexadecimal number system: digits (symbols) allowed: 0-9, A-F base (radix): 16 the order of the digits is significant

hex decimal 0 1 0 1 . . . 9 a b c d e f 9 10 11 12 13 14 15

a3 (base 16) is really a x 16**1 + 3 x 16**0 160 + 3

163 (base 10)

given all these examples, here's a set of formulas for the general case.

N-bit number (in weighted positional notation):

. . . S 2

S 1

S 0

n-1 n-2

given a base b, this is the decimal value

the summation (from i=0 to i=n-1) of S x b**i

TRANSFORMATIONS BETWEEN BASES -----------------------------

any base --> decimal just use the definition give above.

decimal --> binary divide decimal value by 2 (the base) until the value is 0

example: 36/2 = 18 r=0 <-- lsb 18/2 = 9 r=0 9/2 = 4 r=1 4/2 = 2 r=0 2/2 = 1 r=0 1/2 = 0 r=1 <-- msb

36 (base 10) == 100100 (base 2)

14/2 = 7 r=0 <-- lsb 7/2 = 3 r=1 3/2 = 1 r=1 1/2 = 0 r=1 <-- msb

14 (base 10) == 1110 (base 2)

binary --> octal 1. group into 3's starting at least significant symbol

(if the number of bits is not evenly divisible by 3, then add 0's at the most significant end) 2. write 1 octal digit for each group

example:

100 010 111 (binary) 4 2 7 (octal)

10 101 110 (binary) 2 5 6 (octal)

binary --> hex (just like binary to octal!) 1. group into 4's starting at least significant symbol (if the number of bits is not evenly divisible by 4, then add 0's at the most significant end)

2. write 1 hex digit for each group example:

1001 1110 0111 0000 9 e 7 0

1 1111 1010 0011 1 f a 3

hex --> binary (trivial!) just write down the 4 bit binary code for each hexadecimal digit

example:

0011 1001 1100 1000

octal --> binary (just like hex to binary!) (trivial!) just write down the 8 bit binary code for each octal digit

hex --> octal do it in 2 steps, hex --> binary --> octal

decimal --> hex do it in 2 steps, decimal --> binary --> hex

on representing nonintegers ---------------------------

what range of values is needed for calculations very large: Avogadro's number 6.022 x 10 ** 23 atoms/mole mass of the earth 5.98 x 10 ** 24 kilograms speed of light 3.0 x 10 ** 8 meters/sec very small: charge on an electron -1.60 x 10 ** (-19)

scientific notation a way of representing rational numbers using integers (used commonly to represent nonintegers in computers)

exponent number = mantissa x base

mantissa == fraction == significand base == radix point is really called a radix point, for a number with a decimal base, its called a decimal point. all the constants given above are in scientific notation

normalization to keep a unique form for every representable noninteger, they are kept in NORMALIZED form. A normalized number will follow the following rule:

1 <= mantissa < base

In this form, the radix point is always placed one place to the right of the first significant symbol (as above).

on precision, accuracy, and significant digits

These terms are often used incorrectly or ignored. They are important!

A measurement (in a scientific experiment) implies a certain amount of error, depending on equipment used. Significant digits tell about that error. For example, a number given as 3.6 really implies that this number is in the range of 3.6 +- .05, which is 3.55 to 3.65 This is 2 significant digits. 3.60 really implies that this number is in the range of

3.6 +- .005, which is 3.595 to 3.605 This is 3 significant digits.

So, the number of significant digits given in a number tells about how accurately the number is known. The larger the number of significant digits, the better the accuracy.

Computers (or calculators, a more familiar machine) have a fixed precision. No matter what accuracy of a number is known, they give lots of digits in an number. They ignore how many significant digits are involved.

For example, if you do the operation 1.2 x 2.2. given that each number has 2 significant digits, a correct answer is 1.2 x 2.2 ----24 + 24 ----264 --> 2.64 --> 2.6 or 2.6 +- .05 a calculator will most likely give an answer of 2.640000000, which implies an accuracy much higher than possible. The result given is just the highest precision that the calculator. It has no knowledge of accuracy -- only precision. BINARY FRACTIONS

f . . . f f f . f f f ... 2 1 0 -1 -2 -3

n-1 n-2 binary point

The decimal value is calculated in the same way as for non-fractional numbers, the exponents are now negative.

example: 101.001 (binary)

1 x 2**2 + 1 x 2**0 + 1 x 2**-3 4 + 1 + 1/8

5 1/8 = 5.125 (decimal) 2**-1 = .5 2**-2 = .25 2**-3 = .125 2**-4 = .0625 etc. converting decimal to binary fractions Consider left and right of the decimal point separately. The stuff to the left can be onverted to binary as before. Use the following algorithm to convert the fraction: fraction fraction x 2 digit right of point

.8 .6 .2 .4

1.6 1.2 0.4 0.8

1 <-- most significant (f ) 1 0 0 -1

.8 (it must repeat from here!)

---.8 is .1100

NON-BINARY FRACTIONS same as with binary, only the base changes! f f . . . f f f . f f f ... 2 1 0 -1 -2 -3

n-1 n-2

radix point The decimal value is calculated in the same way as for non-fractional numbers, the exponents are now negative.

example: 101.001 (octal) 1 x 8**2 + 1 x 8**0 + 1 x 8**-3

64

+ 1

+ 1/512

65 1/512 = 65.0019 (approx) 13.a6 (hexadecimal) 1 x 16**1 + 3 x 16**0 + a x 16**-1 + 6 x 16**-2 16 + 3 + 10/16 + 6/256

19 166/256 = 19.64 (approx)

CONVERSION WITH OTHER BASES --------------------------another base to decimal: Just plug into the summation. 134 (base 5) 1 x 5**2 + 3 x 5**1 + 4 x 5**0 25 + 15 + 4

44 (base 10)

Decimal to another base: Keep dividing by the base, same algorithm. 100 (base 10) to base 5

rem 100/5 20 0 20/5 4/5 4 0 0 4

100 (base 10) = 400 (base 5) EXPLAIN LOGIC GATES IN DETAIL.

Type

Distinctive shape

Rectangular shape

Boolean algebra between A & B

Truth table

INPUT OUTPUT A B A AND B AND symbol AND symbol 0 0 0 AND 0 1 0 1 0 0 1 1 1 INPUT OUTPUT OR symbol OR symbol A B A OR B 0 0 0 OR A+B 0 1 1 1 0 1 1 1 1 INPUT OUTPUT NOT symbol NOT symbol A NOT A NOT 0 1 1 0 In electronics a NOT gate is more commonly called an inverter. The circle on the symbol is called a bubble, and is used in logic diagrams to indicate a logic negation between the external logic state and the internal logic state (1 to 0 or vice versa). On a circuit diagram it must be accompanied by a statement asserting that the positive logic convention or negative logic convention is being used (high voltage level = 1 or high voltage level = 0, respectively). The wedge is used in circuit diagrams to directly indicate an active-low (high voltage level = 0) input or output without requiring a uniform convention throughout the circuit diagram. This is called Direct

Polarity Indication. See IEEE Std 91/91A and IEC 60617-12. Both the bubble and the wedge can be used on distinctive-shape and rectangular-shape symbols on circuit diagrams, depending on the logic convention used. On pure logic diagrams, only the bubble is meaningful. INPUT OUTPUT A NAND A B NAND symbol B NAND symbol 0 0 1 NAND 0 1 1 1 0 1 1 1 0 NOR symbol NOR INPUT OUTPUT A B A NOR B 0 0 1 0 1 0 1 0 0 1 1 0 INPUT OUTPUT A B A XOR B 0 0 0 0 1 1 1 0 1 1 1 0 INPUT OUTPUT A XNOR A B B 0 0 1 0 1 0 1 0 0 1 1 1

NOR symbol

XOR symbol XOR

XOR symbol

XNOR symbol XNOR

XNOR symbol or

Two more gates are the exclusive-OR or XOR function and its inverse, exclusive-NOR or XNOR. The two input Exclusive-OR is true only when the two input values are different, false if they are equal, regardless of the value. If there are more than two inputs, the gate generates a true at its output if the number of trues at its input is odd ([2]). In practice, these gates are built from combinations of simpler logic gates.

Universal logic gates

Charles Sanders Peirce (winter of 188081) showed that NOR gates alone (or alternatively NAND gates alone) can be used to reproduce the functions of all the other logic gates, but his work on it was unpublished until 1933. The first published proof was by Henry M. Sheffer in 1913, so the NAND logical operation is sometimes called Sheffer stroke; the logical NOR is sometimes called Peirce's arrow. Consequently, these gates are sometimes called universal logic gates.

De Morgan equivalent symbols

By use of De Morgan's theorem, an AND function is identical to an OR function with negated inputs and outputs. Likewise, an OR function is identical to an AND function with negated inputs and outputs. Similarly, a NAND gate is equivalent to an OR gate with negated inputs, and a NOR gate is equivalent to an AND gate with negated inputs. This leads to an alternative set of symbols for basic gates that use the opposite core symbol (AND or OR) but with the inputs and outputs negated or inverted. Use of these alternative symbols can make logic circuit diagrams much clearer and help to show accidental connection of an active high output to an active low input or vice-versa. Any connection that has logic negations at both ends can be replaced by a negationless connection and a suitable change of gate or vice-versa. Any connection that has a negation at one end and no negation at the other can be made easier to interpret by instead using the De Morgan equivalent symbol at either of the two ends. When negation or polarity indicators on both ends of a connection match, there is no logic negation in that path (effectively, bubbles "cancel"), making it easier to follow logic states from one symbol to the next. This is commonly seen in real logic diagrams - thus the reader must not get into the habit of associating the shapes exclusively as OR or AND shapes, but also take into account the bubbles at both inputs and outputs in order to determine the "true" logic function indicated. All logic relations can be realized by using NAND gates (this can also be done using NOR gates). De Morgan's theorem is most commonly used to transform all logic gates to NAND gates or NOR gates. This is done mainly since it is easy to buy logic gates in bulk and because many electronics labs stock only NAND and NOR gates.

Data storage
Logic gates can also be used to store data. A storage element can be constructed by connecting several gates in a "latch" circuit. More complicated designs that use clock signals and that change only on a rising or falling edge of the clock are called edge-triggered "flip-flops". The combination of multiple flip-flops in parallel, to store a multiple-bit value, is known as a register. When using any of these gate setups the overall system has memory; it is then called a sequential logic system since its output can be influenced by its previous state(s). These logic circuits are known as computer memory. They vary in performance, based on factors of speed, complexity, and reliability of storage, and many different types of designs are used based on the application.

Three-state logic gates

A tristate buffer can be thought of as a switch. If B is on, the switch is closed. If B is off, the switch is open. Three-state, or 3-state, logic gates are a type of logic gates that have three states of the output: high (H), low (L) and high-impedance (Z). The high-impedance state plays no role in the logic, which remains strictly binary. These devices are used onbuses also known as the Data Buses of the CPU

to allow multiple chips to send data. A group of three-states driving a line with a suitable control circuit is basically equivalent to a multiplexer, which may be physically distributed over separate devices or plug-in cards. In electronics, a high output would mean the output is sourcing current from the positive power terminal (positive voltage). A low output would mean the output is sinking current to the negative power terminal (zero voltage). High impedance would mean that the output is effectively disconnected from the circuit.

Draw the circuit for Full Adder from the truth table using K-Map.

A Full Adder is a combinational circuit that forms the arithmetic sum of three input bits.it consist of 3 inputs and 2 outputs. Two of the input variable denoted by x and y represent the two significant bits to be added.Third input Z represents the carry. Two inputs are necessary because the arithmetic sum of three binary digits ranges in values from 0 to 3,and binary 2 or 3 needs two digits. The two outputs are designated by symbols S for sum and C for Carry. Block diagram for Full Adder.

FA x y z

Logic Diagram for Full Adder

Truth table for Full Adder Inputs X 0 0 0 0 1 1 1 1 Y 0 0 1 1 0 0 1 1 Z 0 1 0 1 0 1 0 1 C 0 0 0 1 0 1 1 1 S 0 1 1 0 1 0 0 1 Outputs

The eight row under the input variables designates all possible combinations that the binary variables may have. The value of the output variable determined from the arithmetic sum of the input bits. When all the input bits are 0 the input bit also 0. The S output is equal to 1 when only one input is equal to1 or when all the inputs are equal to 1.The C output has a carry of 1 if two or three inputs are equal to 1.

Explain different types of Flip Flops A Flip-flop is a binary cell capable of storing one bit of information.

It has two outputs, one for the normal value and one for the complement value of the bit stored in it.

Flip-flops are storage elements utilized in synchronous sequential circuits.

Synchronous sequential circuits employ signals that effect storage elements only at discrete instances of time.

A timing device called a clock pulse generator that produces a periodic train of clock pulses achieves synchronization.

Values maintained in the storage elements can only change when the clock pulses.

Hence, a flip-flop maintains a binary state until directed by a clock pulse to switch states.

The difference in the types of flip flops is in the number of inputs and the manner in which the inputs affect the binary state.

Flip-flops can be described by a characteristic table which permutates all possible inputs (just like a truth table).

The characteristic table of a flip-flop describes all possible outputs (called the next state) at time Q(t+1) over all possible inputs and the present state at time Q(t).

The most common types of flip flops are:

v. SR Flip-Flop

v. D Flip-Flop

v. JK Flip-Flop

v. T Flip-Flop

SR Flip-Flop

A SR Flip-Flop is an arrangement of logic Gates that maintains a stable input even after the inputs are turned off.

o Inputs:

S (for set)

R (for reset)

C (for clock)

o Outputs:

Q'

Characteristic Table for SR Flip-Flop S 0 0 1 1 R 0 1 0 1 Q(t+1) Q(t) 0 1 1 Description No Change Clear to 0 Set to 1 Indeterminate

D Flip Flop

Inputs: D (for data) C (for clock) Outputs: Q Q' Characteristic Table for D Flip Flop

D 0 1

Q(t+1) 0 1

Description Clear to 0 Set to 1

JK Flip Flop Inputs: J K C (for clock) Outputs: Q Q'

Characteristic Table For JK Flip Flop J K Q(t+1) Description

0 0 1 1 Flip-Flop Inputs: T (for toggle) C (for clock) Outpus: Q Q'

0 1 0 1

Q(t) 0 1 Q'(t)

No change Clear to 0 Set to 1 Complement]

Characteristic Table T 0 1 Q(t+1) Q(t) Q'(t) Description No change Complement

Most flip-flops are edge-triggered flip-flops, which means that the transition occurs at a specific level of the clock pulse. A positive-edge transition occurs on the rising edge of the clock signal. A negative-edge transition occurs on the falling edge of the clock signal. Another type of flip-flop is called a master-slave flip-flop that is basically two flip-flops in series. Flip-flops can also include special input terminals for setting or clearing the flip-flop asynchronously. These inputs are usually called preset and clear and are useful for initialing the flip-flops before clocked operations are initiated.

7. Give short notes on multiplexers? (Or) Explain the operations of multiplexers? (8 marks)

Multiplexing means transmitting a large number of information units over a smaller number of channels of lines. A digital multiplexer is a combinational circuit that selects binary information from one of many input lines and directs it to a single output line the selection of particular input lines is controlled by a set of selection lines. Normally, there are 2n input lines and n selection lines whose bit combinations determine which input is selected. A 4-line to 1-line multiplexer is shown below.

Each of the four input lines I0 to I3, is applied to one input of an AND gate. Selection lines s1 and s0 are decoded to select a particular AND gate. The function table in the fig. lists the input to output path for each possible bit combination of the selection lines, When the MSI function is used in the design of a digital system, it is represented in the block diagram. To demonstrate the circuit

operation, of its input equal to1 and the third input connected to I2. The other three AND gates have at least one input equal to 0, which makes their output equal to0, the OR gate output is now equal to the value of I2, thus providing a path from the selected input to the output. A multiplexer is also called a data selector, since it selects one of many inputs and steers the binary information to the output line. The AND gates and inverters in the multiplexer resemble a decoder circuit and, indeed they decode the input selection lines, in general a 2n decoder by adding to it 2n input lines, one to each AND gate. The outputs of the AND gates are applied to a single OR gate to provide the i-line output. The size of the multiplexer is specified by the number 2n of it input lines, one to each AND gate. The outputs of the AND gates are applied to a single OR gate to provide the i-line output. The size of the multiplexer is specified by the number 2n of its input lines and the single output line. It is then implied that it also contains n selection lines. A multiplexer is often abbreviated as MUX. As in decoder, multiplexer ICs may have an enable input to control the operation of the unit. When the enable input in a given binary state, the outputs are disabled, and when in the other state, the circuits as a normal, multiplexer. At the enable input can be used to expand two or more multiplexer ICs to a digital multiplexer with a large number of inputs. In some cases two or more multiplexers are enclosed with one IC package. The selection and the enable inputs in multiple unit ICs may be common to all multiplexers.

1. Explain about registers in detail (or) Define registers? Explain its usage. (8 marks).
A register is a group of binary cells suitable for holding binary information. A group of flip flops constitutes a register, since each flip-flop is a binary cell capable of storing one bit of information. Similarly an n-bit register has a group of n flip flop without any external gates. The following diagram shows a registered constructed with four D type flip flops p and a common pulse The clock pulse input Cp enables all flip flops so that the information presenting available at the four inputs can transferred into 4 bit registers. The output can be transferred into 4 bit registers. The outputs can be sampled to obtain the information presently stored in the register. The way that the flip flop in the register are triggered is of primary importance. If the flip flops are constructed with gated D latched, the information present at a data (D) input the transferred to the Q o/p, when the enable clock pulse is 1 Q Q Q o/p follows the o/p data as long as the Cp signal remains. When Cp goes to o, i/p just separate the transition is retained at the Q o/p.A register that responds, to pulse duration is commonly called a global latch the Cp input is frequently labeled with the variable. A flip flop can be used in the design of clocked sequential circuit provided; it is sensitive to the pulse transition rather than the pulse duration. This means that the flip flops in the register must be of the edge triggered or master slave type. A group of flip flop sensitive to the pulse transition in a register.A register can always replace a latch, but the converse should be done with caution.

2. Give Short notes on Shift Registers (Or)

Explain about shift registers (8 marks)

A register capable of shifting its binary information in one or both directions is called a shift register. The logical configuration of a shift register consist of a chain of flip flops connected in cascade with the o/p of one flip flop connected to the flip of the next flip-flop. All the flip flop receives the common clock pulse which causes the shift from one stage to the next.The simplest possible register is one that uses only flip flops as shown in the fig. The Q o/p of the given flip flop is connected to the D input of the flip flop at its right.Each clock pulse shifts the contents of the register one bit possible to the right. The serial i/p determines what goes into the left most flip flop duly the shift.The social o/p is taken from the o/p of the rightmost flip flop prior to the application of the flip flop. Function Table for Shift Register Mode Control

Mode Control S1 0 0 1 1 S0 0 1 0 1

Register operation No Change Shift right (down) Shift left (up) Parallel load

3. Give short notes on Binary Counters Write about binary counters (8 Marks ) A register that goes through a predetermined sequence of states upon the application of input pulses is called a counter.

The input pulses may be clock pulses or may originate from an external source. They may occur at uniform times or at random.

A counter that follows a binary sequence is called a binary counter. An n-bit binary counter is a register of n flip-flops along with a combinational circuit that continually produces a binary count of n bits having a value from 0 to 2n-1. The most general binary counter register has the following capabilities: An input for clock pulses to synchronize all operations. An increment operation that signals the register to increment its value by 1. A parallel clear operation that sets all the flip-flop values to 0. A parallel load operation that sets all the flip-flop values according to the values of n input lines associated with the parallel load. N parallel output lines. A control state that leaves the information in the register unchanged even though clock pulses are applied continuously.

Function Table for Binary Counter Register Clear 0 0 0 1 Load 0 0 1 X Increment 0 1 X X Operation No Change Increment count by 1 Load inputs I0-In-1 Clear outputs

3. Explain Decoders with example? (Or) Explain 3 to 8 line decoder with example? (Or) Describe BCD to decimal decoder? (8 Marks). A binary code of n bits is capable of representing up to 2 n distinct elements in coded information. Consider the 3 to 8 line decoder circuit. has three inputs are decoded into eight outputs ,each output representing one of the minterms of the 3 input variables, the three inverters provide the complement of the particular application of this decoder would be a binary to octal conversion. The input variables may represent a binary number, and the outputs will then represent the eight digits in the octal number system

A decoder is a combinational circuit that converts binary information from the n coded inputs to a maximum of 2n unique outputs. 3 to 8 line decoder

The output variables are mutually exclusive because only one output can be equal to 1 at any one time. The output line whose values is equal to 1 represents the minterms equivalent to the binary number presently available in the input lines .Since the circuit has ten inputs, it would be necessary to draw ten maps to simplify each one of the output functions there are six dont care conditions here, and they must be taken into consideration when we simplify each of the output functions, instead of draw it en maps, we will draw only one map and write each of the output variables, D 0 to D 9, inside its corresponding minterms square. Six input combinations will never occur, so we make their corresponding minterm squares with Xs. It is the designers responsibility to decide on how to treat the dont care conditions. Assume the decided to use them in such a way as to simplify the functions to the minimum number of literal D 0 and D 1 cannot be combined with any dont care minterms,D 2 can be combined with the dont care minterm M10 to give: D 2=xyz The square with D 9 can be combined with three other dont care squares to give D 9=wz

Truth Table for 3-to-8-Line Decoder Enable E Inputs Y D7 D6 D5 Outputs D4 D3 D2 D1 D0

0 1 1 1 1 1 1 1 1

X 0 0 0 0 1 1 1 1

X 0 0 1 1 0 0 1 1

X 0 1 0 1 0 1 0 1

0 0 0 0 0 0 0 0 1

0 0 0 0 0 0 0 1 0

0 0 0 0 0 0 1 0 0

0 0 0 0 0 1 0 0 0

0 0 0 0 1 0 0 0 0

0 0 0 1 0 0 0 0 0

0 0 1 0 0 0 0 0 0

0 1 0 0 0 0 0 0 0

Thus the dont care terms cause a reduction in the number of inputs in most of the AND. ENCODER A encoder is a combinational circuit that performs the inverse operation of a decoder. The output lines generate the binary code corresponding to the input values An encoder has 2n (or less) unique inputs and n outputs.

Truth Table for 8-to-3-Line Encoder

The output of the 8-to-3-line encoder can be expressed by the following binary functions: A0 = D 1 + D 3 + D 5 + D 7 A1 = D 2 + D 3 + D 6 + D 7 A2 = D 4 + D 5 + D 6 + D 7 .