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Introduction to computer architecture

Lecture 6 Feb 16th

32 bit computer Memory addressed in bytes 64 instructions 128 registers SWAPM dir1, dir2 swaps the contents of locations dir1 and dir2 in memory.

Exercise

What is the addressable memory range? What is the SWAPM instruction format? Give a MIPS 32 instruction sequence which achieves the same result.

Solution

32 bit word 64 instructions 128 registers SWAPM dir1, dir2

32 bits -> 232 addresses Memory is addressed in bytes -> 232 bytes = 4 GB

Solution
Instruction format

Assume unique instruction format

6 bits

13 bits 32 bits

13 bits

Solution
Instruction sequence in MIPS
la \$t0 dir1 lw \$t1 (\$t0) la \$t2 dir2 lw \$t3 (\$t2) sw \$t3 (\$t0) sw \$t1 (\$t2)

32 bit word 64 instructions 128 registers SWAPM dir1, dir2

are either:
Part of the instruction itself Of a register in RF Of memory Of an I/O unit

The addressing mode tells the CU how to get to operands

Implicit Immediate Direct

Indirect

Register Indexed

x++ x- ++x --x

The operand is not explicitly specified as part of the instruction. E.g. beqz \$a0 label1 I type
If register \$a0 is zero jump to label1. \$a0 is one of the source operands, 0 is the other one.
op rs 16 bits

: fast. No memory access to fetch data. : not available for the general case.

The operand is part of the instruction. E.g. li \$a0 0x00004f51 I type
Load register \$a0 with immediate value 0x00004f51.
op rd 16 bits

: fast. No memory access to fetch data. : the value doesnt always fit. Limited range.
E.g. 32 bit values need multiple loads.

Exercise
Two numbers in \$t0 and \$t1. Write a program which stores a 0 in \$t2 if \$t0 is greater than \$t1 and a 1 otherwise.

Solution
bgt \$t0 \$t1 greater # if \$t0 > \$t1 jump to label li \$t2 1 # otherwise (less or equal) b done # jump over greater branch greater: li \$t2 0 done:

Alternative
li \$t2 1 bgt \$t0 \$t1 done li \$t2 0 done:

The operands are held in registers named in address fields. The registers are specified explicitly. E.g. move \$a0 \$a1 I type
Copy value from register \$a1 to register \$a0.
op rs rt 16 bits
Operand

RF : Limited number of registers. : Fast. No memory access to fetch data. Need small address field: short instruction.

Load register r1 with value at location DIR in memory.
Operand

MM
op rs rt 16 bits

: large address space (>> RF)

Direct: field specifies where the operand is located (what register or memory address).

Indirect: field specifies where the address of the operand is located.

Memory cell pointed to by field contains the address of the operand in memory: EA = (A). E.g. LD R1 [DIR] (IEEE 694)
operand

Look at address DIR in memory for EA. Read content of memory at EA and load it into register R1.

MM

op

rs

rt

16 bits

: slow. May require several memory accesses to find operands.
E.g. ld R1 [[[.R1]]]

Register specified in the field contains the address of the operand in memory: EA = (R). E.g. lw \$a0 (\$a1)

Load value from address pointed to by register a1 into register a0. RF

op

rs

rt

16 bits

MM

: larger address space than direct addressing. : one less memory access than indirect memory addressing. Very small address field needed: shorter instructions, faster fetch.

Displacement addressing (indirect relative to register)

E.g. lw \$a0 12(\$t1)
Load register \$a0 with the value in memory at the location given by \$t1 to which add 12 Types: EA = A + (R) base-register addressing (R may be implicit) EA = A + (PC) relative addressing EA = (A) + R indexing

Opcode Register R

Instruction
MM

RF +

Operand

Indexed addressing / Indexing (indirect relative to index register)

E.g. lw \$a0 (++\$t1)
\$t1 <- \$t1 + 1 \$a0 <- MM[\$t1]

lw \$a0 12(\$t1--)
\$a0 <- MM[\$t1 + 12] \$t1 <- \$t1 1 Types:
Auto-pre-increment Auto-post-increment Auto-pre-decrement Auto-post-decrement ++dir dir++ --dir dir--

Operand is (implicitly) on top of stack E.g.

Immediate Direct
Absolute Register

#value
/dir

.dir
[dir]

Indirect
Register Base register
Indexed Relative to PC Base page desp[.reg] or [.reg,desp] \$dir !dir

[.3]
3
Memory location whose address is in reg
reg 3

#[.3] ![.5]
reg 5

Base page location whose address is in

A[.2] M(A+ reg 2) A[.3,#10] M(A + reg 3 +10) A[B[.2,#12]] M(A + M(b + reg 2 +12)) A[.2++] M(A + reg 2), reg 2 = reg 2 +1 A[.3--:#2] M(A + reg 3), reg 3 = reg 3 -2

MIPS
Immediate Direct
Absolute Register value
dir \$r (dir)

Indirect
Register Base register
Indexed Relative to stack displacement(\$r) displacement(\$sp)

CICS
Complex Instruction Set Computer Many instructions Complex instructions
More than one word Complex CU Large execution time

Note:

Approx. 20% of instructions take 80% of total execution time. 80% of instructions almost never used. 80% of silicon underused, complex, and costly.

RISC
Reduced Instruction Set Computer

Small ISA Instructions are simple and have uniform format

One word CU simple and fast Same addressing modes for all instructions

Compact design:
Extra registers Extra cache

Identical general purpose registers Space for:

Execution models
Stack Register-Register:
All operands in registers Common for RISC

Register-Memory:
Operands in memory or registers

Memory-Memory:
All operands in memory

Exercise
32 bit data bus, 32 bit registers
opcode (8 bits) reg (8 bits) address (16 bits)

a) Maximum number of instructions? b) Maximum number of registers? c) With direct addressing, what is the addressable memory range? d) With indirect addressing, what is the addressable memory range?

8 bits

8 bits reg

Solution

opcode

a) 8 bit opcode -> 28 = 256 nr of instructions. b) 8 bit register field -> 28 = 256 registers.
instruction itself -> addressing range 0 to (216 1) = 65535. the location in memory given in the instruction. When reading the data from memory at the location given by instruction we read 32 bits of memory address! -> 232 addresses!!

Exercise
Add 63 and 127 on 8 bits in C(2)

Solution
63 in C(2) on 8 bits: 00111111 127 in C(2) on 8 bits: 01111111
Sum: 10111110 Overflow!!

Quizz 1 Feb 10th

1. The relative performance of two processors with same instruction set can be judged by the clock rate. True or false? Justify your answer with at least two examples. 2. Convert step-by-step -338 to binary in 2s complement notation using 10 bits. 3. Using 5 bits, add in 1s complement 7 and 10.