CD4051B Q1, CD4052B Q1, CD4053B Q1 CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERS WITH LOGIC-LEVEL CONVERSION

SCHS354 AUGUST 2004

Features

D Matched Switching Characteristics, D

D Qualification in Accordance With D D D

D D D

AEC-Q100 Qualified for Automotive Applications Customer-Specific Configuration Control Can Be Supported Along With Major-Change Approval Wide Range of Digital and Analog Signal Levels Digital: 3 V to 20 V Analog: 3 20 VP-P Low ON Resistance, 125 (Typ) Over 15 VP-P Signal Input Range for VDD VEE = 18 V High OFF Resistance, Channel Leakage of +100 pA (Typ) at VDD VEE = 18 V Logic-Level Conversion for Digital Addressing Signals of 3 V to 20 V (VDD VSS = 3 V to 20 V) to Switch Analog Signals to 20 VP-P (VDD VEE = 20 V)

D D D D D

ron = 5 (Typ) for VDD VEE = 15 V Very Low Quiescent Power Dissipation Under All Digital-Control Input and Supply Conditions, 0.2 W (Typ) at VDD VSS = VDD VEE = 10 V Binary Address Decoding on Chip 5-V, 10-V, and 15-V Parametric Ratings 100% Tested for Quiescent Current at 20 V Maximum Input Current of 1A at 18 V Over Full Package Temperature Range, 100 nA at 18 V and 25C Break-Before-Make Switching Eliminates Channel Overlap

Applications

D Analog and Digital Multiplexing and

Demultiplexing

D Analog-to-Digital (A/D) and D

Digital-to-Analog (D/A) Conversion Signal Gating

Contact factory for details. Q100 qualification data available on request.

description/ordering information
The CD4051B, CD4052B, and CD4053B analog multiplexers are digitally-controlled analog switches that have low ON impedance and very low OFF leakage current. Control of analog signals up to 20 VP-P can be achieved by digital signal amplitudes of 4.5 V to 20 V (If VDD VSS = 3 V, a VDD VEE of up to 13 V can be controlled; for VDD VEE level differences above 13 V, a VDD VSS of at least 4.5 V is required). For example, if VDD = 4.5 V, VSS = 0 V, and VEE = 13.5 V, analog signals from 13.5 V to 4.5 V can be controlled by digital inputs of 0 V to 5 V. These multiplexer circuits dissipate extremely low quiescent power over the full VDD VSS and VDD VEE supply-voltage ranges, independent of the logic state of the control signals. When a logic high (H) is present at the inhibit (INH) input, all channels are off. ORDERING INFORMATION
TA SOIC M TSSOP PW SOIC M 40C to 125C TSSOP PW SOIC M TSSOP PW PACKAGE Reel of 2500 Reel of 2000 Reel of 2500 Reel of 2000 Reel of 2500 Reel of 2000 ORDERABLE PART NUMBER CD4051BQM96Q1 CD4051BQPWRQ1 CD4052BQM96Q1 CD4052BQPWRQ1 CD4053BQM96Q1 CD4053BQPWRQ1 TOP-SIDE MARKING CD4051Q CM051BQ CD4052Q CD4052Q CD4053Q CD4053Q

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Product Preview Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303

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SCHS354 AUGUST 2004

CD4051B Q1, CD4052B Q1, CD4053B Q1 CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERS WITH LOGIC-LEVEL CONVERSION
description/ordering information (continued)
The CD4051B is a single eight-channel multiplexer that has three binary control inputs (A, B, and C) and an inhibit input. The three binary signals select one of eight channels to be turned on and connect one of the eight inputs to the output. The CD4052B is a differential four-channel multiplexer that has two binary control inputs (A and B) and an inhibit input. The two binary input signals select one of four pairs of channels to be turned on and connect the analog inputs to the outputs. The CD4053B is a triple two-channel multiplexer with three separate digital control inputs (A, B, and C) and an inhibit input. Each control input selects one of a pair of channels, which are connected in a single-pole, double-throw configuration. When these devices are used as demultiplexers, the CHANNEL IN/OUT terminals are the outputs, and the common (COM OUT/IN) terminals are the inputs.
CD4051 M OR PW PACKAGE (TOP VIEW) CD4052 M OR PW PACKAGE (TOP VIEW)

CHANNEL I/O 4 CHANNEL I/O 6 COM OUT/IN CHANNEL I/O 7 CHANNEL I/O 5 INH VEE VSS

1 2 3 4 5 6 7 8

16 15 14 13 12 11 10 9

VDD CHANNEL I/O 2 CHANNEL I/O 1 CHANNEL I/O 0 CHANNEL I/O 3 A B C

Y CHANNEL I/O 0 Y CHANNEL I/O 2 COM Y OUT/IN Y CHANNEL I/O 3 Y CHANNEL I/O 1 INH VEE VSS

1 2 3 4 5 6 7 8

16 15 14 13 12 11 10 9

VDD X CHANNEL I/O 2 X CHANNEL I/O 1 COM X OUT/IN X CHANNEL I/O 0 X CHANNEL I/O 3 A B

CD4053 M OR PW PACKAGE (TOP VIEW)

IN/OUT by IN/OUT bx IN/OUT cy OUT/IN CX OR CY IN/OUT CX INH VEE VSS

1 2 3 4 5 6 7 8

16 15 14 13 12 11 10 9

VDD OUT/IN bx or by OUT/IN ax or ay IN/OUT ay IN/OUT ax A B C

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CD4051B Q1, CD4052B Q1, CD4053B Q1 CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERS WITH LOGIC-LEVEL CONVERSION
SCHS354 AUGUST 2004

Function Tables
CD4051 INPUTS INH L L L L L L L L H C L L L L H H H H X B L L H H L L H H X A L H L H L H L H X ON CHANNEL 0 1 2 3 4 5 6 7 None

X = dont care CD4052 INPUTS INH L L L L H X = dont care CD4053 INPUTS INH L L H X = dont care A OR B OR C L H X ON CHANNEL ax or bx or cx ay or by or cy None B L L H H X A L H L H X ON CHANNEL 0x, 0y 1x, 2y 2x, 2y 3x, 3y None

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CD4051B Q1, CD4052B Q1, CD4053B Q1 CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERS WITH LOGIC-LEVEL CONVERSION
logic diagram (positive logic)
CD4051B CHANNEL I/O
7 16 VDD 4 6 2 5 5 4 1 3 12 2 15 1 14 0 13

TG TG A 11 TG B 10 Logic-Level Conversion C 9 Binary to 1-of-8 Decoder With Inhibit TG

3

COM OUT/IN

TG TG TG TG

INH 6

VSS

VEE

All inputs are protected by CMOS protection network. CD4052B X CHANNEL I/O
3 11 2 15 1 14 0 12

TG
16

VDD

TG TG TG
13 COM X 3

A 10 B 9 INH 6 Logic-Level Conversion

OUT/IN

Binary to 1-of-4 Decoder With Inhibit

TG TG TG TG
1 0 5 1 2 2 4 3

COM Y OUT/IN

VSS

VEE

Y CHANNEL I/O

All inputs are protected by CMOS protection network.

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CD4051B Q1, CD4052B Q1, CD4053B Q1 CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERS WITH LOGIC-LEVEL CONVERSION
SCHS354 AUGUST 2004

logic diagrams (positive logic) (continued)

CD4053B

IN/OUT 16 VDD cy 3 Logic-Level Conversion Binary to 1-of-2 Decoders With Inhibit cx 5 by 1 bx 2 ay 13 ax 12 TG TG TG TG TG TG COM OUT/IN xc or xy 4 COM OUT/IN bc or by 15 COM OUT/IN ac or ay 14

A 11

B 10

INH 6 VDD

8 VSS

VEE

All inputs are protected by standard CMOS protection network.

absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, V+ to V (voltages referenced to VSS terminal) . . . . . . . . . . . . . . . . . . . . . 0.5 to 20 V DC input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VDD + 0.5 V DC input current, any one input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA Package thermal impedance, JA (see Note 1): M package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108C/W Maximum junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150C Lead temperature (during soldering): At distance 1/16 1/32 inch (1,59 0,79 mm) from case for 10 s max . . . . . . . . . . . . . . . . . . . . . . . 265C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65C to 150C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7.

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CD4051B Q1, CD4052B Q1, CD4053B Q1 CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERS WITH LOGIC-LEVEL CONVERSION
recommended operating conditions
MIN VDD TA Supply voltage Operating free-air temperature 5 40 MAX 20 125 UNIT V C

electrical characteristics, VSUPPLY = 5 V, AV = 1 V, RL = 100 , unless otherwise noted (see Note 2)

VDD (V) 5 IDD Quiescent device current 10 15 20 Signal Input (Vis) and Output (Vos) 5 ron Drain-to-source ON-state resistance ON-state resistance difference between any two switches Input/output leakage current (switch off) Cis Cos Input capacitance VEE = 0 V, VSS = 0 V, VIS = 0 to VDD 10 15 5 VEE = 0 V, VSS = 0 V Any channel OFF (MAX) or all channels OFF (COM OUT/IN) (Max), VEE = 0 V, VSS = 0 V, See Note 3 VEE = 5 V, VSS = 5 V CD4051 Output capacitance Feedthrough capacitance Propagation delay (signal input to output) VEE = 5 V, VSS = 5 V CD4052 CD4053 Cios VEE = 5 V, VSS = 5 V VIS(p-p) = VDD, RL = 200 k k, CL = 50 pF, tr, tf = 20 ns 5 5 10 15 5 10 15 18 5 0.1 1 850 330 210 1300 550 320 470 180 125 15 10 5 105 5 30 18 9 0.2 30 15 10 60 30 20 ns pF pF 0.1 A pF 1050 400 240 LIMITS AT INDICATED TEMPERATURES 25C 40C 5 10 20 100 125C 150 300 600 3000 MIN TYP 0.04 0.04 0.04 0.08 MAX 5 10 20 100 A A UNIT

PARAMETER

TEST CONDITIONS

ron

tpd

NOTES: 2. Peak-to-peak voltage symmetrical about VDD VEE 2 3. Determined by minimum feasible leakage measurement for automatic testing

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SCHS354 AUGUST 2004

electrical characteristics, VSUPPLY = 5 V, AV = 1 V, RL = 100 , unless otherwise noted (see Note 2) (continued)
VEE (V) VDD (V) LIMITS AT INDICATED TEMPERATURES 25C 40C 125C MIN TYP MAX UNIT

PARAMETER

TEST CONDITIONS

Control (Address or Inhibit), VC VIL Input low voltage VIL = VDD through 1k , 1k, VIH = VDD through 1k , 1k, RL = 1k to VSS, Iis < 2 A on all OFF channels VIL = VDD through 1k , 1k, VIH = VDD through 1k , 1k, RL = 1k to VSS, Iis < 2 A on all OFF channels VIN = 0 V, 18 V tr, tf = 20 ns, CL = 50 pF, RL = 10 k, VSS = 0 V, See Figure 10, Figure 11, and Figure 14 0 0 0 5 0 tr, tf = 20 ns, CL = 50 pF, RL = 1 k, VSS = 0 V, V See Figure 11 0 0 10 0 tr, tf = 20 ns, CL = 50 pF, RL = 10 k, VSS = 0 V, V See Figure 15 0 0 10 VSS VSS VSS VSS VSS VSS 5 10 15 5 10 15 18 5 10 15 5 5 10 15 5 5 10 15 5 1.5 3 4 3.5 7 11 0.1 1.5 3 4 3.5 7 11 1 3.5 7 11 105 450 160 120 225 400 160 120 200 200 90 70 130 5 0.1 720 320 240 450 720 320 240 400 450 210 160 300 7.5 pF ns ns ns A V 1.5 3 4 V

VIH IIN

Input high voltage

Input current Address-to-signal OUT (channels ON or OFF) propagation delay Inhibit-to-signal OUT (channel turning ON) propagation delay Inhibit-to-signal OUT (channel turning OFF) propagation delay Input capacitance, any address or inhibit input

tpd1

tpd2

tpd3

CIN

NOTES: 2: Peak-to-peak voltage symmetrical about VDD VEE 2 3: Determined by minimum feasible leakage measurement for automatic testing

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CD4051B Q1, CD4052B Q1, CD4053B Q1 CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERS WITH LOGIC-LEVEL CONVERSION
electrical specifications
LIMITS AT INDICATED TEMPERATURES 25C MIN 3-dB cutoff frequency, channel ON (sine-wave input) RL = 1 k, k , VOS at COM OUT/IN, See Note 2, VOS at COM OUT/IN VEE = VSS, 20log VOS/VIS = 3 dB, VOS at any channel RL = 10 k, See Note 2 VEE = VSS, fis = 1-kHz sine wave 40-dB feedthrough frequency (all channels OFF) RL = 1 k, VOS at COM OUT/IN, See Note 2 VEE = VSS, 20log VOS/VIS = 40 dB, VOS at any channel RL = 1 k, between any two channels, See Note 2 VEE = VSS, 20log VOS/VIS = 40 dB, Between sections, Measured on common VEE = VSS, 20log VOS/VIS = 40 dB, Between sections, Measured on any channel VEE = VSS, 20log VOS/VIS = 40 dB, Between any two sections, In pin 2, Out pin 14 VEE = VSS, 20log VOS/VIS = 40 dB, Between any two sections, In pin 15, Out pin 14 Address or inhibit to signal crosstalk RL = 10 k, See Note 4 VEE = 0 V, VSS = 0 V, tr, tf = 20 ns, VCC = VDD VSS (square wave) CD4053 6 10 65 65 mVPEAK CD4052 10 MHz 2.5 5 10 CD4053 CD4052 CD4051 5 5 5 10 10 10 CD4053 CD4052 CD4051 5 5 5 10 10 10 TYP 30 25 20 60 2 THD Total harmonic distortion 3 5 5 10 15 0.3 0.2 0.12 0.12 8 10 12 8 3 6 MHz % MHz MAX

PARAMETER

TEST CONDITIONS

VIS (V)

VDD (V)

UNIT

40-dB signal crosstalk frequency

NOTES: 2. Peak-to-peak voltage symmetrical about VDD VEE 2 4. Both ends of channel

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TYPICAL CHARACTERISTICS
CHANNEL ON-STATE RESISTANCE vs INPUT SIGNAL VOLTAGE
ron Channel ONState Resistance W ron Channel ONState Resistance W 600 500 400 300 25C 200 55C 100 0 4 Supply Voltage (VDD VEE) = 5 V TA = 125C 300 250 TA = 125C 200 25C 150 55C 100 50 0 10 7.5 5 2.5 0 2.5 5 7.5 10

CHANNEL ON-STATE RESISTANCE vs INPUT SIGNAL VOLTAGE

Supply Voltage (VDD VEE) = 10 V

Vis Input Signal Voltage V

92CS-27326RI

Vis Input Signal Voltage V

92CS-27327RI

Figure 1
CHANNEL ON-STATE RESISTANCE vs INPUT SIGNAL VOLTAGE
ron Channel ONState Resistance W TA = 25C 300 250 200 150 100 10 V 50 0 10 7.5 5 2.5 0 2.5 5 7.5 10
92CS-27330RI

Figure 2
CHANNEL ON-STATE RESISTANCE vs INPUT SIGNAL VOLTAGE
ron Channel ONState Resistance W Supply Voltage (VDD VEE) = 15 V 300 250 200 TA = 125C 150 100 50 0 10 7.5 5 2.5 0 2.5 5 7.5 10 Vis Input Signal Voltage V 25C 55C

Supply Voltage (VDD VEE) = 5 V

15 V

Vis Input Signal Voltage V

92CS-27329RI

Figure 3

Figure 4

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CD4051B Q1, CD4052B Q1, CD4053B Q1 CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERS WITH LOGIC-LEVEL CONVERSION
TYPICAL CHARACTERISTICS
DYNAMIC POWER DISSIPATION vs SWITCHING FREQUENCY (CD4051B)
PD Power Dissipation Per Package mW
10 5 TA = 255C Alternating O and I Pattern 10 4 CL = 50 pF VDD = 15 V f Test Circuit VDD B/D CD4029 A B C

ON CHARACTERISTICS FOR 1-OF-8 CHANNELS (CD4051B)

6

Vos Output Signal Voltage V

VDD = 5 V VSS = 0 V 4 VEE = 5 V TA = 255C 2

RL = 100 kW, RL = 10 kW

1 kW 500 W 100 W

VDD 100 11 10 9

10 3

VDD = 10 V 10 2 VDD = 5 V

13 14 15 12 CD4051 1 5 3 2 4 8 7 6 CL 100

10 5

CL = 15 pF 10 1 10 10 2 10 3 10 4

6 6 4 2 0 2 4 6

Vis Input Signal Voltage V

f Switching Frequency kHz

Figure 5
DYNAMIC POWER DISSIPATION vs SWITCHING FREQUENCY (CD4052B)
PD Power Dissipation Per Package mW
10 5 TA = 255C Alternating O and I Pattern 10 4 CL = 50 pF VDD = 15 V f VDD 10 5

Figure 6
DYNAMIC POWER DISSIPATION vs SWITCHING FREQUENCY (CD4053B)
TA = 255C Alternating O and I Pattern 10 4 CL = 50 pF

PD Power Dissipation Per Package mW

VDD = 15 V VDD = 10 V

Test Circuit CD4029 B/D A B 3 CL 13 12 14 15 11

10 3 VDD = 10 V 100 10 2 VDD = 5 V CL = 15 pF 10 1 10 10 2

100 10 9 1 5 2 4 CD4052 6 7 8

VDD f
10 3

Test Circuit 9 3 5

100 W

10 2

VDD = 5 V CL = 15 pF

10 3 10 4 10 5

4 CL 12 13 100 W CD4053 2 10 1 11 15 6 14 7 8
10 4 10 5

10 1 10 10 2 10 3

f Switching Frequency kHz

f Switching Frequency kHz

Figure 7

Figure 8

10

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PARAMETER MEASUREMENT INFORMATION

VDD = 15 V VDD = 7.5 V VDD = 5 V 5V 16 VSS = 0 V 16 VSS = 0 V VDD = 5 V 5V 16

16

7.5 V

VSS = 0 V VEE = 0 V VSS = 0 V 7 8 (A) 7 8 (B)

VEE = 7.5 V

VEE = 10 V

7 8 (C)

VEE = 5 V

7 8 (D)

NOTE: The A, B, C, and INH input logic levels are L = VSS and H = VDD. The analog signal (through the TG) may swing from VEE to VDD.

Figure 9. Typical Bias-Voltage Test Circuits

tr = 20 ns 90% 50% 10% 90% 50% 10% Turn-Off Time 90% 50% Turn-On Time

tf = 20 ns

tr = 20 ns 90% 50% 10% 90% 90% 50%

tf = 20 ns

10%

10%

10% Turn-Off Time tPHZ

10% Turn-On Time

Figure 10. Channel Turned ON Waveforms (RL = 1 k)

Figure 11. Channel Turned OFF Waveforms (RL = 1 k)

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CD4051B Q1, CD4052B Q1, CD4053B Q1 CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERS WITH LOGIC-LEVEL CONVERSION
PARAMETER MEASUREMENT INFORMATION
VDD VDD VDD

1 2 3 4 5 6 7 8

16 15 14 13 12 11 10 9

IDD

1 2 3 4 5 6 7 8

16 15 14 13 12 11 10 CD4052 9

IDD

1 2 3 4 5 6 7 8

16 15 14 13 12 11 10 9

IDD

CD4051

CD4052

CD4053

Figure 12. OFF Channel Leakage Current, Any Channel OFF

VDD VDD VDD

IDD

1 2 3 4 5 6 7 8

16 15 14 13 12 11 10 9

IDD

1 2 3 4 5 6 7 8

16 15 14 13 12 11 10 9

1 2 3 4 5 6 7 8

16 15 14 13 12 11 10 9

IDD

CD4051

CD4052

CD4053

Figure 13. OFF Channel Leakage Current, All Channels OFF

VDD 1 2 3 4 5 6 7 8 VSS 16 15 14 13 12 11 10 9 VSS VDD Output Output 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD Output 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 RL CL

RL

CL VEE

VDD

CL

RL VDD

VEE VDD VSS Clock In

VDD VSS Clock In

VEE

VEE

VEE

VEE VDD VSS VSS Clock In VSS

VSS

CD4051

CD4052

CD4053

VSS

Figure 14. Propagation Delay, Address Input to Signal Output

Output 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD Output 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD Output 50 pF VEE VDD VDD VSS Clock In VEE VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD

RL

50 pF VEE VDD Clock In VEE VSS

RL

50 pF VEE VDD

RL

VDD VSS

VDD VSS

Clock In

VEE VSS

tPHL and tPLH VSS

tPHL and tPLH VSS

tPHL and tPLH VSS

CD4051

CD4052

CD4053

Figure 15. Propagation Delay, Inhibit Input to Signal Output

12

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PARAMETER MEASUREMENT INFORMATION

VDD VDD A 1K 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VIL VIH VDD

1K VIH VIL

VIH

VIL

1 2 3 4 5 6 7 8

16 15 14 13 12 11 10 9

1K

A VIH VIL VIH VIL

1K

1K

1 2 3 4 5 6 7 8

16 15 14 13 12 11 10 9

1K

mA

VIH VIL

CD4052B

CD4053B

CD4051B

Measure <2 mA on All OFF Channels (e.g., Channel 6)

Measure <2 mA on All OFF Channels (e.g., Channel 2x)

Measure <2 mA on All OFF Channels (e.g., Channel by)

Figure 16. Input-Voltage Test Circuit (Noise Immunity)

VDD 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9

VDD 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9

CD4051 CD4053

CD4052

Figure 17. Quiescent Device Current

Keithley 610 Digital Multimeter TG On 1-kW Range

VDD

10 kW VSS

Y XY Plotter

H.P. Moseley 7030A

Figure 18. Channel ON-Resistance Test Circuit

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CD4051B Q1, CD4052B Q1, CD4053B Q1 CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERS WITH LOGIC-LEVEL CONVERSION
PARAMETER MEASUREMENT INFORMATION
VDD 1 2 3 4 5 6 7 8 VSS 16 15 14 13 12 11 10 9 CD4051 CD4053 1 2 3 4 5 6 7 8 VSS 16 15 14 13 12 11 10 9 CD4051 CD4053 VDD

VDD

VDD

VSS

VSS

NOTE: Measure inputs sequentially to both VDD and VSS. Connect all unused inputs to either VDD or VSS.

NOTE: Measure inputs sequentially to both VDD and VSS. Connect all unused inputs to either VDD or VSS.

Figure 19. Input Current

Channel ON 5 VPP VDD 6 7 8 OFF Channel RF VM 1K Channel OFF RL Common RL

5 VPP

Channel OFF

RF VM

RF VM RL

Channel ON

RL

Figure 20. Feedthrough

5 VPP

Figure 21. Crosstalk Between Any Two Channels

Channel In X ON or OFF RL

Channel In Y ON or OFF RL

RF VM

Figure 22. Crosstalk Between Duals or Triplets (CD4052B, CD4053B)

Differential Signals

CD4052

CD4052

Communications Link

Differential Amplifier/Line Driver Differential Multiplexing

. Differential Receiver

Demultiplexing

Figure 23. Typical Time-Division Application of the CD4052B

14

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APPLICATION INFORMATION
In applications where separate power sources drive VDD and the signal inputs, the VDD current capability should exceed VDD/RL (RL = effective external load). This provision avoids permanent current flow or clamp action on the VDD supply when power is applied or removed from the CD4051B, CD4052B, or CD4053B.
A B C A B CD4051B C INH A B E 1/2 CD4556 Q0 Q1 Q2 A B CD4051B C INH A B CD4051B C INH

D E

Common Output

Figure 24. 24-to-1 Multiplexer Addressing

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MECHANICAL DATA
MTSS001C JANUARY 1995 REVISED FEBRUARY 1999

PW (R-PDSO-G**)
14 PINS SHOWN

PLASTIC SMALL-OUTLINE PACKAGE

0,65 14 8

0,30 0,19

0,10 M

0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 A 7 0 8 0,75 0,50

Seating Plane 1,20 MAX 0,15 0,05 0,10

PINS ** DIM A MAX

14

16

20

24

28

3,10

5,10

5,10

6,60

7,90

9,80

A MIN

2,90

4,90

4,90

6,40

7,70

9,60

4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153

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