1.

INTRODUCTION
1. A matrix reordering method for reordering elements of a coefficient matrix whose structure corresponds tocoefficients Of linear simultaneous equations whose solutions areto be produced by parallel processing of processors of a computer in accordance with Gaussian elimination, said matrix reordering method comprising the steps of: based on a number of non-zero elements included in the coefficient matrix and an accumulative processing time of the Gaussian elimination of the coefficient matrix, determining a first combination of row and column and a second combination of row and column, which are selected from among rows and columns of the coefficient matrix; and performing replacement of elements between the first combination of row and column and the second combination of row and column within the coefficient matrix using the coefficient matrix for solving the linear simultaneous equations. 2. A matrix reordering method for reordering elements of a coefficient matrix whose structure corresponds to coefficients of linear simultaneous equations whose solutions are to be produced by parallel processing of processors of a computer inaccordance with Gaussian elimination, said matrix reordering method comprising the steps of: based on a number of non-zero elements included in the coefficient matrix and lengths of critical paths created by the Gaussian elimination of the coefficient matrix, determining a first combination of row and column and a second combination of row and column, which are selected from among rows and columns of the coefficient matrix; and performing replacement of elements between the first combination of row and column and the second combination of row and column within the coefficient matrix using the coefficient matrix for solving the linear simultaneous equations. 3. A matrix reordering method according to claim 1 or 2 further comprising the step of: in accordance with a prescribed condition, selectively performing either the replacement of elements between the first and second combinations of rows and columns or secondary replacement of elements between a third combination of row and column and a fourth combination of row and column, which are selected based on symmetry of the coefficient matrix. 4. A matrix reordering method according to claim 3 further comprising the step of: creating a symmetric coefficient matrix by transposition of a non-symmetric coefficient matrix that is given as the coefficient matrix, so that the secondary replacement is performed on elements of the symmetric coefficient matrix between the third and fourth combinations of rows and columns, which are selected based on symmetry of the symmetric coefficient matrix. 5. A matrix reordering apparatus for reordering elements of a coefficient matrix whose structure corresponds to coefficients of linear simultaneous equations whose solutions are to be produced by parallel processing of processors of a computer in accordance with Gaussian elimination, said matrix reordering apparatus comprising: a determining means for based on a number of non-zero elements included in the coefficient matrix and an accumulative processing time of the Gaussian elimination of the coefficient matrix, determining a first combination of row and column and a second combination of row and column, which are selected from among rows and columns of the coefficient matrix; and a replacing means for performing replacement of elements between the first combination of row and column and the second combination of row and column within the coefficient matrix wherein the apparatus is operable to use the coefficient matrix for solving the linear simultaneous equations. 6. A matrix reordering apparatus for reordering elements of a coefficient matrix whose structure corresponds to coefficients of linear simultaneous equations whose solutions are to be produced by parallel processing of processors of a computer in accordance with Gaussian elimination, said matrix reordering apparatus comprising: a determining means for based on a number of non-zero elements included in the coefficient matrix and lengths of critical paths created by the Gaussian elimination of the coefficient matrix, determining a first combination of row and column and a second combination

of row and column, which are selected from among rows and columns of the coefficient matrix; and a replacing means for performing replacement of elements between the first combination of row and column and the second combination of row and column within the coefficient matrix wherein the apparatus is operable to use the coefficient matrix for solving the linear simultaneous equations. 7. An electronic circuit simulation method using matrix reordering for reordering elements of a coefficient matrix that represents electronic elements of a given electronic circuit by linear simultaneous equations whose solutions are to be produced by parallel processing of processors of a computer in accordance with Gaussian elimination, said electronic circuit simulation method comprising the steps of: based on a number of non-zero elements included in the coefficient matrix and an accumulative processing time of the Gaussian elimination of the coefficient matrix, determining a first combination of row and column and a second combination of row and column, which are selected from among rows and columns of the coefficient matrix; and performing replacement of elements between the first combination of row and column and the second combination of row and column within the coefficient matrix using the coefficient matrix for solving the linear simultaneous equations. 8. An electronic circuit simulation method using matrix reordering for reordering elements of a coefficient matrix that represents electronic elements of a given electronic circuit by linear simultaneous equations whose solutions are to be produced by parallel processing of processors of a computer in accordance with Gaussian elimination, said electronic circuit simulation method comprising the steps of: based on a number of non-zero elements included in the coefficient matrix and lengths of critical paths created by the Gaussian elimination of the coefficient matrix, determining a first combination of row and column and a second combination of row and column, which are selected from among rows and columns of the coefficient matrix; and performing replacement of elements between the first combination of row and column and the second combination of row and column within the coefficient matrix using the coefficient matrix for solving the linear simultaneous equations. 9. An electronic circuit simulation method according to claim 7 or 8 further comprising the step of: in accordance with a prescribed condition, selectively performing either the replacement of elements between the first and second combinations of rows and columns or secondary replacement of elements between a third combination of row and column and a fourth combination of row and column, which are selected based on symmetry of the coefficient matrix. 10. An electronic circuit simulation method according to claim 9 further comprising the step of: creating a symmetric coefficient matrix by transposition of a non-symmetric coefficient matrix that is given as the coefficient matrix, so that the secondary replacement is performed on elements of the symmetric coefficient matrix between the third and fourth combinations of rows and columns, which are selected based on symmetry of the symm11. An electronic circuit simulation apparatus using matrix reordering for reordering elements of a coefficient matrix that represents electronic elements of a given electronic circuit by linear simultaneous equations whose solutions are to be produced by parallel processing of processors of a computer in accordance with Gaussian elimination, said electronic circuit simulation apparatus comprising: a determining means for based on a number of non-zero elements included in the coefficient matrix and an accumulative processing time of the Gaussian elimination of the coefficient matrix, determining a first combination of row and column and a second combination of row and column, which are selected from among rows and columns of the coefficient matrix; and a replacing means for performing replacement of elements between the first combination of row and column and the second combination of row and column within the coefficient matrix wherein the apparatus is operable to use the coefficient matrix for solving the linear simultaneous equations. 12. An electronic circuit simulation apparatus using matrix reordering for reordering elements of a coefficient matrix that represents electronic elements of a given electronic circuit by linear simultaneous equations whose solutions are to be produced by parallel processing of processors of a computer in accordance with Gaussian elimination, said electronic circuit simulation apparatus

comprising the steps of: a determining means for based on a number of non-zero elements included in the coefficient matrix and lengths of critical paths created by the Gaussian elimination of the coefficient matrix, determining a first combination of row and column and a second combination of row and column, which are selected from among rows and columns of the coefficient matrix; and a replacing means for performing replacement of elements between the first combination of row and column and the second combination of row and column within the coefficient matrix wherein the apparatus is operable to use the coefficient matrix for solving the linear simultaneous equations. 13. A matrix reordering method for reordering elements of a coefficient matrix created based on coefficients of linear simultaneous equations whose solutions are to be produced by parallel processing of processors of a computer in accordance with Gaussian elimination, said matrix reordering method comprising the steps of: selecting from among pivots included in the coefficient matrix a first pivot whose degree corresponding to a number of non-zero elements is under a threshold; selecting from among the pivots included in the coefficient matrix a second pivot whose critical path length is minimum; performing replacement of elements between the first pivot and the second pivot within the coefficient matrix; and adding new non-zero elements, which are newly produced by the Gaussian elimination of the first pivot, to the coefficient matrix using the coefficient matrix for solving the linear simultaneous equations. 14. A matrix reordering method according to claim 13 further comprising the step of: performing reordering of a partial matrix whose elements are not eliminated and are selected from among the elements of the coefficient matrix in accordance with a nested dissection method, so that non-zero elements, which are newly produced by the Gaussian elimination of the partial matrix, are added to the coefficient matrix. 15. A matrix reordering method according to claim 14 further comprising the step of: creating a symmetric coefficient matrix by transposition of a non-symmetric coefficient matrix that is given as the coefficient matrix, so that the reordering is performed on the symmetric coefficient matrix. 16. A matrix reordering method according to claim 14 wherein the reordering is started if a degree or a parameter of theMatrices Applied to Electric Circuits

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It took me a bit to figure this out, partly due to the fact of no really good explanation of it. So, I'm going to have a crack at it. Basically, I wanted to understand how keyboard matrices work. Specifically, I wanted to know why keyboard "ghosting" and "masking" happen, and how to prevent them. . This article may be reproduced in whole or in part, without fee, subject to the following restrictions: The copyright notice above and this permission notice must be preserved complete on all complete or partial copies. Any translation or derived work must be approved by the author in writing before distribution. If you distribute this work in part, instructions for obtaining the complete version of this manual must be included, and a means for obtaining a complete version provided. Small portions may be reproduced as illustrations for reviews or quotes in other works without this permission notice if proper citation is given. Exceptions to these rules may be granted for

academic purposes. Write to the author and ask. These restrictions are here to protect us as authors, not to restrict you as learners and educators.

Fundamentals Ohm's Law states the voltage across a resistor, R (or impedance, Z) is directly proportional to the current passing through it (the resistance/impedance is the proportionality constant)

Kirchhoff's Voltage Law (KVL): the algebraic sum of the voltages around any loop of N elements is zero (like pressure drops through a closed pipe loop)

Kirchhoff's Current Law (KCL): the algebraic sum of the currents entering any node is zero, i.e., sum of currents entering equals sum of currents leaving (like mass flow at a junction in a pipe)

s fixes the masking problem for the same reason, the diode stops the current.

2. The Matrix Circuit

Keyboards use a matrix with the rows and columns made up of wires. Each key acts like a switch. When a key is pressed, a column wire makes contact with a row wire and completes a circuit. The keyboard controller detects this closed circuit and registers it as a key press. Here is a simple keyboard matrix:
Figure 1. Conceptual Matrix Circuit

This keyboard only has 4 keys: A, B, C, and D. Each key has a unique grid location, much like points on a graph. Key A is at node C1R1, key B is at node C2R1, key C is at node C1R2, and key D is at node C2R2. In reality this is pretty useless which is why real keyboards use many more rows and columns. However, I want to keep it simple. The electronic circuit for this matrix looks something (not exactly) like this:
Figure 2. Switch Open

3. Scanning to Detect Key Presses

In order to detect key presses, the keyboard controller will scan all columns, activating each one by one. When a column is activated, the controller detects which rows are "activated". In order to detect key presses, the keyboard controller will scan all columns, activating each one by one. When a To step through this procedure, the controller activates column C1 and checks rows R1 and R2: Figure 3. Scanning Column 1

Neither key A nor C are pressed, so neither row R1 nor R2 is activated. The controller now knows that both nodes C1R1 and C1R2 are deactivated. Then it activates column C2 and checks rows R1 and R2 again: Figure 4. Scanning Column 2

Neither key B nor D are pressed so neither row R1 nor R2 is activated. The controller now knows that both nodes C2R2 and C2R2 are deactivated.

4. Single Key Presses

Now, let's say the the A key is pressed. The matrix will look like this: Figure 5. The A Key is Pressed

Key A corresponds to node C1R1. By going back to the circuit, we can see how C1R1 is detected. First, here is the circuit with switch A closed: Figure 6. The A Switch is Closed

Walking through the scanning procedure again, the controller activates column C1 and detects which rows are activated: Figure 7. Row 1 is Activated

This time, row R1 is activated. So the controller now knows that node C1R1 is pressed. Since C1R1 corresponds to the A key, the controller knows that the A key is pressed. When the controller activates column C2, neither row R1 nor R2 are activated. Both switches B and D are open: Figure 8. Neither Row is Activated

When the A key is released, the circuit goes back to the original, and the controller detects the node C1R1 is no longer activated.

5. Multiple Key Presses

Now we will cover multiple key presses. Let's say that both keys A and D are pressed at the same time. The matrix will look like this: Figure 9. The A and D Keys are Pressed

Both nodes C1R1 and C2R2 should be detected. Here is the circuit with both switches A and D closed: Figure 10. The A and D Switches are Closed

Scanning column C1 then column C2 produces an outcome like this: Figure 11. Row 1 is Activated

Figure 12. Row 2 is Activated

When column C1 is activated, row R1 is active, hence node C1R1 is activated. When column C2 is activated, row R2 is activated, hence node C2R2 is activated.

6. Three Simultaneous Key Presses and Ghosting

When three keys are pressed at the same time, ghosting may occur. In this example, keys A, B, and D are pressed. The matrix looks like this: Figure 13. The A, B, and D Keys are Pressed

If everything goes well, nodes C1R1, C2R1, and C2R2 will be detected. Let's look at the circuit view again: Figure 14. The A, B, and D Switches are Closed

When activating column C1, the circuit now looks like this: Figure 15. Rows 1 and 2 are Activated

If you get the feeling something is not right, you are correct! This is where the ghosting problem comes to play. Row R1 is activated as well as row R2, so both nodes C1R1 and C1R2 are activated. Node C1R1 is expected as it corresponds to the A key that is pressed. However, node C1R2 corresponds to the C key. Switch C is open, so the key is not really pressed. The keyboard controller does not know this and incorrectly generates a C key press. What happens is that closing switch B and switch D at the same time creates an electrical path from C1 to R2, bypassing the open switch C. The keyboard does not know that switch C is open and generates a "ghost" key press. Ghosting will show up when any 3 corners of a rectangle in the matrix are pressed at once. In my simple example, any 3 keys causes ghosting, but in a bigger matrix only 3 corners of a rectangle cause it. Just for completion, here is the circuit when activating column C2: Figure 16. Rows 1 and 2 are Activated

As expected, nodes C2R1 and C2R2 are activated corresponding to the B and D keys.

7. The Masking Problem

Take the scenario above where keys A, B, and D are all pressed. Now press the C key. Given the ghosting affect, nothing changes as the controller already thought that C was pressed. Release the B key. Aha! The same problem occurs. The key release is not detected because switch B is bypassed by the closed switches A and C.

8. Getting Rid Of Ghosting and Masking

By using diodes, both the ghosting and masking problems are eliminated. Just put diodes in series with each switch, like so: Figure 17. Schematic with Diodes

Let's go back to the scenario where A, B, and D are pressed simultaneously. Activating columns C1 and C2 now look like this:
Figure 18. Only Row 1 is Activated

Figure 19. Row 1 and 2 are Activated

Voila! The diodes stop the current from flowing in the "wrong" direction back up switch B. When column C1 is activated, only node C1R1 is activated and C1R2 is not. Also, when column C2 is activated, both R1 and R2 as expected.

9. What Diode Parts to Use

Now that the theory has been explained, you need to know how to actually build a circuit with diodes to fix this problem. Unfortunately, this is where my knowledge fades. I know the theory but not the practice (that's what happens when you take a college class but never use that information outside the classroom. :-) Nonetheless, I will explain what I do know (or think I know). Thanks goes out to a reader who would like to remain anonymous for clearing up much this information for me. There are many kinds of diodes for all different purposes. In this case, you need what is called a switching diode. Other common types of diodes are rectifier diodes to rectify AC current to DC, power diodes, which can handle more current without breaking down and/or melting, and everyone's favorite, light emitting diodes If you go looking at an electronics store, you will probably stumble across a diode by the name of 1N4001. I was going to use these, but when I went to buy them, the clerk said that I should use the 1N4148 due to faster switching time. For over a year, I was unsure if the 1N4001s would actually work, until a reader clarified this issue. The 1N4001s were designed to rectify the AC wall current. Since the wall current "switches" at 60 times per second, the 1N4001 must be within a 60Hz tolerance. This is plenty fast for a keyboard switch unless you can press a button faster than 60 times per second (doubtful :). The 1N4148s are designed for fast switching and have a switching time of 4 nanoseconds. Since this is much faster than the 1N4001, this is what the clerk was talking about. This makes the 1N4148 the more "proper" and economical choice, even if it is overkill. Since the 1N4148 sell for $0.90 for a pack of 30, this is my recommendation.

Matrix Methods for Electrical Systems

Summary: This module introduces matrix algebra as a tool for solving multivariable problems. Setting up a model for a nerve cell, we use matrices to simply express the electrical properties of the nerve cell, and utilize matrix algebra to solve for the potential differences across nodes and axial and membrane current. By working several examples, we also introduce and reinforce a general problem modeling methodology, and demonstrate the usefulness of matrix algebra for realizing a solution to these problems Nodal Analysis Example

1. 2.

Label the nodal voltages. Apply KCL. a. KCL at top node gives IS = IL + IC b. Supernode constraint eq. of VL = VS

c. Solve for VT for instance.

10. Conclusion
It's pretty simple: Use diodes in series with your switches! What kind of diodes, you may ask? Use 1N4148 switching diodes and you'll have no problems!
A tutorial on how mathema

tics, matrices in particular, are applied to model electric circuits. There are two closed loops in the above circuit. loop 1: e1, R1 and R3 and loop 2: e2, R2 and R3. e1 and e2 are sources of voltages. R1, R2 and R3 are resistors. i1 is the current flowing across R1 and i2 is the current flowing across R2. We now apply Kichhoff's law to each loop. loop 1: e1 = R1 i1 + R3 (i1 - i2) loop 2: e2 = R2 i2 + R3 (i2 - i1) Question: If e1, e2, R1, R2 and R3 are known, how do you calculate i1 and i2? This circuit is simple

involvesand only two equations. However electric cicuits can be much more complicated that the one above and matrices are suitable to answer the above question. Let us group like terms in the above system of equations e1 = i1 (R1 + R3) - i2 R3 e2 = - i1 R3 + i2(R2 + R3) and then write it in matrix form as follows

The above is a matrix equation that may be solved using any known method to solve systems of equations. Let e, R and i be matrices given by

The solution to the above matrix equation is given by

where R -1 is the inverse matrix of R and is given by.

REFERENCES The source is internet. The sites are

www.dribin.org/dave/keyboard-html www.wikipidia.org www.analyzemath.com www.matrixelectronicmeasuring.in www.books.google.co.in www.portal.acm.org www.asu.shams.edu.eg

www.stmarys.ca