Logic Gates

Logic Functions NMOS & CMOS Technologies Logic Gates

The Inverter The NAND Gate The NOR Gate Compound Gates

Binary Logic
Open Off Closed On

Logic 0

Logic 1

A Single switch to represent:

Logic 0 ( OFF, Open, Logic Low, 0 Volts) Logic 1 ( ON, Closed, Logic High, 5 Volts)

AND Function
A B

AND F=A B
A B

Off

On
A B

A 0 0 1 1

B Light 0 Off 1 Off 0 Off 1 On

OR Function
A B

Off

OR F=A + B
A B
A

A 0 0 1 1

B 0 1 0 1

Light Off On On On

On

Switch Implementation of a Logic Function

F = a d + a b c + a b d + c d
a + F b c d Open

Closed

Switch Implementation
F = a b c + d ( a + b + c )

NMOS Technology

Logic gates are built using

A single Depletion mode NNtype Pull up transistor between Vdd and gate output (Always ON) A Number of Enhancement mode N-type transistors Nbetween gate output and Enhancement ground (Vss). mode N-type NTransistors

Vdd
Depletion mode N-type Transistor

Out Gnd

NMOS Inverter
Depletion mode Transistor gate is connected to its source ie Vgs = 0 N-type Depletion mode is ON

Vdd
D

Depletion mode Tr

Out
E

A 0 1

D On On

E Off On

Out Vdd Low

A
Enhancement mode Tr

Gnd

Inverters Low output

When A=1 Pull-down Tr is ON i = Vdd/(R + r) Vout =i*r = (Vdd * r) / (R+r)

Vdd
Pull-up i R

Out

A= 1

r Pull-down

If Vdd=5V and R = 4r Then Vout=1V (Vlow)

Gnd

NMOS Inverter

N-Type Transistors Out = not ( A ) Suffers from power dissipation when A=1 Good 1, poor 0 Ratio Logic

Vdd
N-type

Depletion mode Tr

Out Gnd

A
Enhancement mode Tr

Pull up/Pull down must be 4 or more

CMOS Technology
Only Enhancement mode transistors P-type as pull-ups between Vdd and Out pin N-type as pull-downs between Out pin and GND
Enhancement mode N-type Transistors Enhancement mode P-type Transistors

Vdd
Pull-ups

Out
Pull-down

Gnd

CMOS Inverter

Use enhancement NNand P-type Trs POut = not ( A ) Zero static power dissipation Good 1 and 0 Ratioless Logic

Vdd A
Enhancement n-type Tr

Enhancement p-type Tr

Out Gnd

CMOS Inverter

P+ P+ P+ N+

N+

N+

NMOS NAND Gate

Use N-Depletion and NEnhancement Trs Out = not ( A B) Suffers from power dissipation when both A and B =1 Good 1, poor 0 Ratio Logic

Vdd

Depletion mode Tr

Out A B Gnd
Enhancement mode Tr

Pull-up/Pull-down must be 4 or more

CMOS NAND Gate

Use P- and N-type Enhancement Trs Out = not ( A B) Zero static power dissipation Good 1 and 0 Ratioless Logic

Vdd A A B

Enhancement p-type Trs

B Out
Enhancement mode Trs

Gnd

2-input NAND Gate

N-Well

N+

P+

NMOS NOR Gate

Use N-Depletion and NEnhancement Trs Out = not ( A + B) Suffers from power dissipation when either A or B =1 Good 1, poor 0 Ratio Logic

Vdd

Depletion mode Tr

Out A
Enhancement mode Tr

B
Gnd

Pull-up/Pull-down must be 4 or more

CMOS NOR Gate

Use P- and N-type Enhancement Trs Out = not ( A + B) Zero static power dissipation Good 1 and 0 Ratioless Logic

Vdd
Enhancement P-type Trs

B A
Enhancement N-type Tr

Out B
Gnd

2-input NOR Gate

Design of Combination Gate

Designing with NMOS technology

Minimise the given function F Invert F ---G = NOT ( F ) simplify the resultant G function Implement G circuit using enhancement mode Ntype Transistors and connect it between ground and output node Connect the output node through Depletion mode to Vdd and calculate the size of the transistor.

Designing with CMOS technology -- starting with P-circuit

Minimise the given function F and implement it as P-type circuit and invert all inputs -- Connect this Pcircuit between the Vdd and the output node the N-type circuit is the complement of the P-circuit connected to the same inputs as P-circuit. This circuit must be connected between the output and the Ground.

Designing with CMOS technology -- starting with N-circuit

Compute the complement of F { G = NOT(F) } Simplify G and implement it as N-type circuit -Connect it between the output node and the Ground. The P-circuit is the complement of the N-circuit using the same inputs. Connect the P-circuit between the output node and Vdd.

Design Problem
F = A + B.C
Implement F using NMOS technology -- Calculate the pull-up transistor size assuming the minimum size for pull-down devices CMOS Technology Start with the P-circuit first Start with the N-circuit first

Clocked CMOS

Clocking the input(s) Perfect switch for each input

Vdd
C

a
C

Out Gnd

Clocked CMOS

2MOS) (C

Clocking the output stage Only two transistors are needed at the output stage of the device. Therefore less transistor count than the last CCMOS

Vdd
C

A
C

Clocked output

Out

Gnd

Dynamic CMOS (Domino technology)

Vdd L
N-type circuit

Out Function F When Crl = 0 (Charge Cycle) L = Vdd Out = 0 Vss When Crl = 1 (Evaluate Cycle) Out = F L = F

Crl

Dynamic CMOS (Domino technology)

Vdd When Crl = 1 (Ground Cycle) L = GND Out = 1
P-type circuit

Function F

When Crl = 0 (Evaluate Cycle) Out = F L=F

Crl Vss

Out

IC Technologies -- CMOS

Highest density-- suitable for memories Lowest power per gate, only during logic transition - suitable for memories Adequate for analogue Slower than GaAs and Bipolar The cheapest to manufacture for highdensity digital circuits with moderate analogue requirement

CMOS Technology -- Continued

available design tools and cell libraries low design cost encourages regular and easily automated layout styles static CMOS requires 2n for n inputs function - disadvantage dynamic CMOS requires n+4 for n inputs function

CMOS Technology -- Continued

Rise and fall times are of the same order Transmission gates pass both logic levels well, suitable for logic structures, eg latches, registers and multiplexers Voltage required to switch a gate is a fixed percentage of Vdd. Variable range is 1.5 to 15 volts.

Other IC Technologies

GaAs

The fastest raw gate speed -- suitable for communication applications Most expensive to manufacture Design is expensive -- full customed Next to GaAs in speed -- Comms applications High power consumption -- Low integration

Bipolar

Types of pull-ups

N-Depletion mode Tr N-type enhancement mode Tr P-type enhancement mode Tr Resistor

Vdd

Vdd

Vdd Rpu

Vdd

MOS Transistor
L
L Channel Length W Channel Width

W
Z = Impedance
Direction of flow of carriers

Z ~ L/W

Implementation of Functions

Implement F using NMOS, CMOS, C2MOS and dynamic CMOS technologies

F=AB+CD

Design of Multiplexers

Switch S to select between inputs A&B

A Out When S=0 Out=A When S=1 Out=B

B S

Two input Mux Circuit

S Switch 1 A S B S Switch 2 Output Output signal is connected to A or B and hence never floating Output = S A + S B

Pass-Transistor Logic
c a b C=1 a b on on z D=1 If C=D=1 N-Type Pass Transistors are ON z = a or b or in between. This is called charge sharing . If a=1 & b=0 short circuit and circuit is dead d z Z=ac + bd

Pass-Transistors
c a b d=c z Implement this logic as a multiplexer circuit Let d=c z = a c + b c

The output must be connected to one and only one input signal

NAND Pass-Transistor
A B 0 1 0 1 Z 1 1 1 0 Pass Function A' + B' A' + B A + B' A' + B'

A B B A 0 1
A' B' A B' A' B'

0 0 1 1

0
A'

1
B

Modified Karnaugh Map

NAND Pass Transistor gate

B A 0 1
A' B' A B' A' B'

0
A'

1
B

Assume B as a control signal for the Mux circuit and A as the input variable Z = B(AB + AB) + B(AB + AB) = B(B) + B(A) = B(1) + B(A) B B z

Note B + BA = B + A = (BA) NAND

1 A

AND Pass-Transistor
A B B A 0 1
A B A' B A B

A 0 0 1 1

B 0 1 0 1

Z 0 0 0 1

Pass Function A+ B A + B' A' + B A+ B

0
A

1
B'

Modified Karnaugh Map

AND Pass Transistor gate

B A 0 1
A B A' B A B

0
A

1
B'

Assume B as a control signal for the Mux circuit and A as the input variable Z = B(AB + AB) + B(AB + AB) = B(B) + B(A) = B(0) + B(A) B B z

Note B(0) + B(A) = BA AND function

0 A

OR Pass-Transistor
A B B A 0 1
A B A B' A B

A 0 0 1 1

B 0 1 0 1

Z 0 1 1 1

Pass Function A+ B A' + B A + B' A+ B

0
A'

1
B

Modified Karnaugh Map

OR Pass Transistor gate

B A 0 1
A B A B' A B

0
A'

1
B

Assume B as a control signal for the Mux circuit and A as the input variable Z = B(AB + AB) + B(AB + AB) = B(A) + B(B) = B(A) + B(1) B B z

Note B(A) + B = A + B OR function

A 1

NOR Pass-Transistor
A B B A 0
A' A' B' A' B B'

A 0 0 1 1

B 0 1 0 1

Z 1 0 0 0

Pass Function A' + B' A + B' A' + B A' + B'

1
A B'

Modified Karnaugh Map

NOR Pass Transistor gate

B A 0
A' A' B' A' B B'

1
A B'

Assume B as a control signal for the Mux circuit and A as the input variable Z = B(AB + AB) + B(AB + AB) = B(A) + B(B) = B(A) + B(0) B B z

Note B(A) + B(0) = AB =(A+B) NOR function

A 0

Pass-Transistor -- Comments
A

B Y

For Y=AB Taking A&B as control signals Never allow a function result to be unknown like in this implementation

When A=B=1 Y=1 Correct When A or B = 0 Y=?

Pass Transistors -- continued

Consider the function when true and also when false When true Y=AB

A 1

B Y

When False Y=(AB) =A + B

Pass Transistor - (Y=AB)

AND Function All inputs as controls A 1 0 A B B B Y 0 A 2 Transistors 4 Transistors B Y AND as Mux circuit n-1 control and one as data

Pass Transistor Design Procedure C

Generate truth table from the given Boolean equation Generate the pass-transistor functions

when expression result =1 pass transistor function is represented by the input variables when expression result =0 pass transistor function is represented by the invert of the input variables

Pass Transistor Design Procedure -Continued

Use Karnaugh Map or other means to generate the Pass Transistor Function

For n input variable function use n-1 as control and one only as input data write the expression to include the product terms of the control signals ANDed with the resultant of the minimised sum-of-product expression {This will leave either 0, 1, data, or (data)}.

Investigation

Compare the advantages and disadvantages of

NMOS implementation SCMOS implementation CCMOS DCMOS (Domino) implementation Pass Transistor implementation

Include design requirements, number and type of transistors and total areas (ignore pads and wiring)

EXNOR Gate

F = ab
a

Vdd F 4 Trs

= ( a.b).( a + b)
a b 10 Trs F

XOR Gate

F = ab

a b F 0V

4 Trs

A=B and A=B

Circuit
ab

Use of Transmission gates a Discuss the circuit operation. a=b b

Comparator a=b Circuit

a0 b0 a1 b1 a2 b2 a3 b3
r0 r1 r2 r3

r0 = a0 r1 = a1 r2 = a2 r3 = a3

b0 b1 b2 b3

F= (a=b)

F = AND(r0,r1,r2,r3)

Using Shannon Theorem for pass transistor solution

r0 = (a0 b0) + (a0 b0) = a0b0(1) + a0b0(0) + a0b0(0) + a0b0(1)
Vdd a0 a0 b0 b0

r0
Vss