FORMAT PCF/TH/01 MADHA ENGINEERING COLLEGE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING Branch Year & Semester Academic

Year Subject Code Name of the Subject Nature of the subject Batch Aim of the Course: To make the students to understand the applications of DSP processors in signal processing.,etc : Electronics and Communication Engg. :I/I : 2012-2013 : VL9211 : DSP Integrated circuits : Main : 2012-2014

Objective of the Course To study about the DSP processors and its architectures Understand the application of processors in signal processing Transforms and its applications Image coding,filters and compression

Staff who had handled the subject in the earlier years / Semesters (Including Current Semester) Sl. No. 1 2 3 2011-2012 2012-2013 A.Muthulakshmi Academic Year Name of the Staff Result Obtained %

Name of the Staff

Signature of the Staff

FORMAT / PCF / TH / 02 MADHA ENGINEERING COLLEGE, Kundrathur, Chennai 600 069 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING Class Time Table for I Yr. / I Sem. W. E. F. 12-09-2012
Batch: 2012 2014 HOUR 1 2 9.30 DAY 8.30 -9.30 10.20 MON TUE WED THU FRI AMM AMEE VDT SSDM DSPIC T-TUTORIAL MA 9217 VL 9211 AP 9212 VL 9212 VL 9213 AP 9213 VL 9217 : Applied Mathematics for Electronics Engineers : DSP Integrated Circuits : Advanced Digital System Design : VLSI Design Techniques : Solid State Device Modeling and Simulation : Advanced Microprocessors and Microcontrollers : VLSI Design Lab I : J. Jini (JJ) : A. Muthulakshmi(AM) : S. Bhavani (SB) : A.S. Narmadaa (AS) : 6 Hrs. / Week : 6 Hrs. / Week : 6 Hrs. / Week : 6 Hrs. / Week DSPIC DSPIC ADSD ADSD SSDM 3 10.20 11.10 SSDM DSPIC AMEE VDT With effect from 12.09.2012 Break 11.10 11.25 4 11.25 12.15 ADSD 5 12.15 1.05 AMM Lunch 1.05 1.35 L U N C H Year/Semester: I/I 6 1.35 2.25 VDT DSPIC ADSD 7 2.25 3.15 SSDM AMM VDT 8 3.15 4.05 AMEE VDT AMM

B R E A K

VD LAB-I AMEE ADSD DSPIC SSDM VDT AMEE

VD LAB -I ADSD AMEE AMM

: Dibyalekha Chaini (DC) : 5 Hrs. / Week : S. Immanuel (SI) : A.S. Narmadaa (AS) : 5 Hrs. / Week : 6 Hrs. / Week

Class Advisor : A.S. Narmadaa (AS)

Signature of HOD

FORMAT / PCF / TH / 02 MADHA ENGINEERING COLLEGE, Kundrathur, Chennai 600 069 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING Individual Time Table for me. W. E. F. 02-07-2012
Ms. A. MUTHULAKSHMI 1 HOUR 8.30 9.30 9.30 10.20 10.20 11.10 10.35 11.25 11.25 12.15 12.15 01.05 12.45 1.35 TLW DSPIC DSPIC TLW WED TLW DSPIC (T) THU TLW I YR LAB (A) LIB I YR LAB (G) 1.35 2.25 2.25 3.15 3.15 4.05 DSPIC 2 3 4 5 6 7 8 9 10

DAY

MON TUE

FRI

DSPIC

TLW

DSPIC

T Tutorial Sub. Code Subject THEORY EC2305 VL 9211 LIB TLW DSPIC LIB Staff Name Hours / Week

Transmission Lines and Wave guides DSP Integrated Circuits LIBRARY III A
PRACTICAL

A. Muthulakshmi A. Muthulakshmi A. Muthulakshmi

5 6 1

GE2114

EP LAB

Engineering Practices Laboratory

A. Muthulakshmi

Signature of HOD

FORMAT PCF/TH/05 MADHA ENGINEERING COLLEGE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING DETAILED SYLLABUS Batch: 2012 - 2013 Subject:DSP Integrated circuits Year & Semester : I / I Subject Code : VL9211

Unit No.

Topics
UNIT I DSP INTEGARTED CIRCUITS AND VLSI CIRCUIT TECHNOLOGIES :Standard digital signal processors, Application specific ICs for DSP, DSP systems, DSP system design, integrated circuit design. MOS transistors, MOS logic, VLSI process technologies, Trends in CMOS technologies. DIGITAL SIGNAL PROCESSING :Digital signal processing, Sampling of analog signals, Selection of sample frequency, Signal- processing systems, Frequency response, Transfer functions, Signal flow graphs, Filter structures, Adaptive DSP algorithms, DFT-The Discrete Fourier Transform, FFT-The Fast Fourier Transform Algorithm, Image coding, Discrete cosine transforms. DIGITAL FILTERS AND FINITE WORD LENGTH EFFECTS :FIR filters, FIR filter structures, FIR chips, IIR filters, Specifications of IIR filters, Mapping of analog transfer functions, Mapping of analog filter structures, Multirate systems, Interpolation with an integer factor L, Sampling rate change with a ratio L/M, Multirate filters. Finite word length effects -Parasitic oscillations, Scaling of signal levels, Round-off noise, Measuring round-off noise, Coefficient sensitivity, Sensitivity and noise.

No. of Hours

Books referred

1. Lars Wanhammer, DSP Integrated Circuits, 1999 Academic press, New York

II

2. A.V.Oppenheim et.al, Discrete-time Signal Processing, Pearson Education, 2000.

III

3. Emmanuel C. Ifeachor, Barrie W. Jervis, Digital signal processing A practical approach, Second Edition, Pearson Education, Asia.

IV

DSP ARCHITECTURES AND SYNTHESIS OF DSP ARCHITECTURES:DSP system architectures, Standard DSP architecture, Ideal DSP architectures, Multiprocessors and multicomputers, Systolic and Wave front arrays, Shared memory architectures. Mapping of DSP algorithms onto hardware, Implementation based on complex PEs, Shared memory architecture with Bit serial PEs. ARITHMETIC UNITS AND INTEGRATED CIRCUIT DESIGN :Conventional number system, Redundant Number system, Residue Number System, Bit-parallel and Bit-Serial arithmetic, Basic shift accumulator, Reducing the memory size, Complex multipliers, Improved shiftaccumulator. Layout of VLSI circuits, FFT processor, DCT processor and Interpolator as case studies. Cordic algorithm.

4. Keshab K.Parhi, VLSI Digital Signal Processing Systems design and Implementation, John Wiley & Sons, 1999.

Signature of the Staff

Signature of the HOD

FORMAT PCF/TH/06 MADHA ENGINEERING COLLEGE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING DETAILED LESSON PLAN Batch : 2012 2013 Year & Semester :I/I Subject :DSP Integrated circuits Subject Code : VL9211 Class No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Date Period Topics to be covered Books to be Referred

UNIT- I DSP INTEGARTED CIRCUITS AND VLSI CIRCUIT TECHNOLOGIES Introduction 10/9/12 8 Standard digital signal processors 11/9/12 2 Application specific ICs for DSP 11/9/12 6 DSP system design 12/9/12 3 DSP system design 14/9/12 1 integrated circuit design 14/9/12 3 MOS transistors, 21/9/12 1 MOS logic 22/9/12 2 VLSI process technologies 24/9/12 2 VLSI process technologies 25/9/12 2 25/9/12 26/9/12 27/9/12 28/9/12 28/9/12 29/9/12 1/10/12 3/10/12 4/10/12 5/10/12 6/10/12 8/10/12 2 3 3 1 5 3 2 3 8 1 5 2
Trends in CMOS technologies.

UNIT II DIGITAL SIGNAL PROCESSING

Digital signal processing functions Sampling of analog signals Selection of sample frequency Signal- processing systems Frequency response, Transfer functions Signal flow graphs, Adaptive DSP algorithms, Filter structures DFT-The Discrete Fourier Transform FFT-The Fast Fourier Transform Algorithm Image coding ,Discrete cosine transforms problems

1.Lars wanhammer, DSP Integrated Circuits, 1999 Academic press, New York

23 24 25 26 27 28 29 30 31

UNIT III 9/10/12 10/10/12 12/10/12 12/10/12 13/10/12 16/10/12 17/10/12 19/10/12 20/10/12

2 3 1 5 1 2 3 1 3

DIGITAL FILTERS AND FINITE WORD LENGTH EFFECTS FIR filters, FIR filter structures, FIR chips IIR filters ,Specifications of IIR filters Mapping of analog transfer functions, Mapping of analog filter structures Multirate systems, Multirate filters Interpolation with an integer factor L, Sampling rate change with a ratio L/M, Finite word length effects -Parasitic oscillations, Round-off noise, Measuring round-off noise Scaling of signal levels ,Coefficient sensitivity Sensitivity and noise,problems

UNIT IV DSP ARCHITECTURES AND SYNTHESIS OF DSP ARCHITECTURES DSP system architectures 32 22/10/12 8 Standard DSP architecture 33 24/10/12 3 Ideal DSP architectures 34 29/10/12 8 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 30/10/12 31/10/12 2/11/12 2/11/12 3/11/12 2 3 1 6 8
Multiprocessors and multicomputers, Systolic and Wave front arrays Shared memory architectures Mapping of DSP algorithms onto hardware Implementation based on complex PEs Shared memory architecture with Bit serial PEs.

2 .A.V.Oppenheim et.al, Discrete-time Signal Processing, Pearson Education, 2000.

UNIT V ARITHMETIC UNITS AND INTEGRATED CIRCUIT DESIGN Conventional number system 5/11/12 8 Redundant Number system, Residue Number System 6/11/12 2 Bit-parallel and Bit-Serial arithmetic 7/11/12 3 Basic shift accumulator 9/11/12 1 9/11/12 10/11/12 14/11/12 16/11/12 16/11/12 17/11/12 6 2 3 1 6 3
Reducing the memory size, Complex multipliers, Improved shift-accumulator Layout of VLSI circuits FFT processor, DCT processor and Interpolator as case studies Cordic algorithm

Problems problems

Signature of the Staff

Signature of the HOD

MADHA ENGINEERING COLLEGE DEPARTMENT OF ELECTRONICS AND COMMUNCIATION ENGINEERING NAMELIST Batch: 2012 2014 Year: I Year.
S. No. 1 2 3 4 5 6 7 8 Reg. No. Students Name G. MAHENDRA REDDY LOURDS SHEEBA G. NIVEDITHA C.R. NARENDRAN S. RAJESH A. RANJUDHA R. SRI VIDHYA V. SUBANANTHAN N.

Signature of the Staff

Signature of the HOD

FORMAT PCF/TH/07 MADHA ENGINEERING COLLEGE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING Batch Year & Semester Subject : 2012 - 2014 : I /I : DSP Integrated circuits ASSIGNMENT TOPICS Unit No. Topics Books suggested for reference Date of announcement Date of submission Subject Code : VL 9211

SELF STUDY TOPICS

UNIT No.

Topics Nil SEMINAR TOPICS

Books Suggested

S.No

Date

Topics

Books Suggested

Name of the student Taken

Signature of the Staff

Signature of the HOD

FORMAT PCF/TH/08 MADHA ENGINEERING COLLEGE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING Batch Year & Semester Subject Subject Code : 2012 - 2014 : I /I : DSP Integrated circuits : VL 9211

Current and Relevant Content beyond the syllabus

Sl.No

Date

Topic Covered

Source of the topic

Nil

Syllabus Requirements (AV / ET / System / Demo lab/ Seminar Hall /Etc)

Unit No

Topic

Facility Required

Source of requirement

Nil

Signature of the Staff

Signature of the HOD

FORMAT PCF/TH/09 MADHA ENGINEERING COLLEGE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING MARK LIST Batch : 2012 2014 Year & Semester : I / I Subject : DSP Integrated Circuits Subject Code : VL 9211

Sl.No. 1 2 3 4 5 6 7 8

Reg.No.

Name of the student

G. MAHENDRA REDDY LOURDS SHEEBA G. NIVEDITHA C.R. NARENDRAN S. RAJESH A. RANJUDHA R. SRI VIDHYA V. SUBANANTHAN N.

Cycle test I (Max80 100) 80 83 78 66 80 80 80

Cycle test II (Max 100)

Model Exam (Max100)

University Exam (Max-100)

Signature of the Staff

Signature of the HOD

FORMAT PCF / TH / 10 A MADHA ENGINEERING COLLEGE DEPARTMENT OF ECE 1. 2. 3. 4. 5. 6. 7. 8. 9. Name of the Department Branch Year & Semester Subject Code Name of the Subject Name of the Examination Total No. of Students No. of Students Absent No. of Students Appeared : : : : : : : : : : : : Electronics & Communication Engineering Electronics & Communication Engineering I/I VL 9211 DSP Integrated Circuits Cycle test 1 08 0 08 08 0 100

10. No. of Students Passed 11. No. of Students Failed 12. Percentage of Pass
RESULT ANALYSIS

Below 25% Description

25% to 44%

45% to 59%

60% to 74%

75% to 89%

90% to 100%

Number of Students

Passing Minimum

: 50 %

Difference between First mark and last mark: 17 Reason: NA Action to be taken: NA

Signature of the Staff Name : A.MUTHULAKSHMI Date : 16.11.2012

Signature of the HOD

FORMAT PCF / TH / 11 MADHA ENGINEERING COLLEGE DEPARTMENT OF ECE

CYCLE TEST 1 - BAR CHAT

Batch Subject : 2012 2014 : DSP Integrated Circuits Year & Semester Subject Code :I/I : VL 9211

N O 8 7 O 6 F 5 S T U D E N S 4 3 2 1 0 0 0

Cycle Test 1
7

1 0 0

Students passed

Percentage range

Signature of the Staff

Signature of the HOD