Power Integrity analysis techniques to get the best system performance at the cheapest cost.

Tanit Virutchapunt tanitv@sigrity.com

Sigrity, Inc.
EDAPS2009 Shenzhen, China Dec 2nd, 2009

Power Integrity Specialist

What is the best power plane performance?

What is best DC power plane performance? Devices see voltage closet to nominal voltage Low IR drop Well balanced DC voltages among devices on the same rail Low Temperature Rise on Metal Low Current Density Power Efficiency Low Power Loss What is best AC power plane performance? Low noise Low loop inductance Low and Flat impedance

Best Performance VS Cost

Best power plane performance comes with a price. How to get the best power plane without adding extra cost to the design is challenging to designer.

EST B

$
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What to look for in DC analysis?

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IR drop target
How to budget IR drop and AC noise margin?
Poor design Good design

IR drop

Total margin

IR drop
AC noise margin

Total margin

AC noise margin

IR drop margin should be less than AC noise margin since the AC noise usually a lot harder to be controlled in the margin.
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Excessive IR drop due to narrow and long traces

Functional problem can be caused by too much IRdrop even in the low power .

IR drop target is 66mV

Voltage +3.3VCS refdes
U3_CP1 U2_CP0 J23_GX1 J24_GX2 J54_DASD J49_RAID U18_FSP1 J25_ENET0 U31_HMC0 U30_HMC0

criteria Breif description P6 P6 GX CARD GX CARD DASD backplane RAID card FSP1 chip ENET card HMC chip HMC chip

Max current (A) 0.250 0.250 0.218 0.218 0.006 0.006 0.51 0.006 0.012 0.012

66mV (2%) IR drop (mV) -160 -115 -113 -111 -29 -13 -2.0 -1.4 -1.2 -1.0

159% over the target

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Excessive IR drop due to DC resistance on passive components

There is no such thing as zero ohm resistor.

Excessive IR drop on vias

5mV drop on each via
VRM

10mV drop IC

2.4A flows into each via

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Understand Temperature Rise on copper caused by current flow on the copper

Thickness = 0.5oz

Current Density VS Width Current VS Area

IPC-2152 spec gives relationship between Temperature Rise VS Cross-session of copper. Trace has an uniform cross-session thus IPC spec is straight forward. Shape has different cross-sessions at different locations, IPC spec is no longer straight forward.

Same Current

100 sq.mil 30 c

500 sq.mil 5 c

5A

5A

With the same current flow on the plane, narrower plane will cause more heat.
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Same Temperature

100 sq.mil 30 c

500 sq.mil 30 c

5A 12A To keep the same temperature rise on copper, wider plane can have more current.
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Same Current Density

100 mil 9 c
heat heat

500 mil 32 c

30mA/mil^ 2

30mA/mil^ 2

With the same current density flowing on the plane at different width, the wider plane will cause more heat on the copper since there is less area heat can dissipate.
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Same Temperature

100 mil 30 c

500 mil 30 c

56mA/mil^2

28mA/mil^2

To keep the same temperature rise on copper, narrower plane can have higher current density.
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Smoke or Fire is number#1 concern, what would happen if this design were built?

Temperature Rise = 300c

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Localize Heat in low power net

This low power rail can cause excessive current density on the copper plane because of the narrow shape.

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Power Loss
Power Loss is important in all designs especially products that use battery.

High power loss area

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Devices should see voltage closet to a nominal voltage

2A 1A 1A 1A 1A 4A

0.5A

0.5A

0.5A

0.5A

10A 4A 2A
0.5A 0.5A 0.5A 0.5A

5A

VRM With DC resistance on the plane that causes IR drop from power source to devices, actual voltages at the devices will be less than the nominal voltage.
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Power Source location and voltage output setting are important

1.3V

1)

200mV drop 1A

1.5V

Power Source
200mV drop

1.5V

2)

1.7V

1A

1.5V

1.65V
150mV drop 100mV 1A 3L/4 L/4

Device Current Flow

3)

1.75V

1A

1.5V

1.575V
75mV drop 75mV drop

1.5V
1A

4)

1A L/2 L/2 R1

5)

R2 I2 L2

I1 L1

VRM is at a location where R2*I2 = R1*I1

1.5V 1.5V
1A

6)

1.5V
1A

1.5V
1A

7)

1A

1.552V

1.5V
1A

1.56V
2A

1.5V

52mV on each direction From regulator

60mV on each direction From regulator

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Impossible to place power source in the best location for all devices
Mechanical requirement forces connectors to this place

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How to improve the power plane performance without adding extra cost?

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How to identify copper areas that need to be improved when DC voltage is failing?
Improving high current density area can help three things: 1. Reduce Resistance in this area 2. Reduce current density which will make copper cooler 3. Cooler copper will make copper resistivity lower which will make even less resistance in this area
Plane Voltage Distribution Plot

Sink 5

Sink 4

5.25 V

Plane Current Density Plot

Sink 0

Sink 3 Sink 2

VRM

2nd 3rd 1st

4.75V

Sink 1

Underflow color, Voltage below 4.75V

Current density plot is used to identify areas that should be used to add copper to improve IRdrop.
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How to improve Power Efficiency?

Identify high power loss areas in the design. Power Loss plot can be used to pinpoint high power loss area. High Power Loss area 3A 5A

Regulator

1A each
Trace Via Plane Top 15.75 8.48 73.94 L1 0 0.3 45.78 L2 0 0 666.06 Bottom 0 0 47.67 857.98 mW
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Total 15.75 8.78 833.45

% 2 1 97

Total power loss

How to find the via that will trigger field failure?

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Highest current vias from Thousand of vias

Identify vias that have high current flow. Via Current plot can be used to pinpoint vias with high current flow.

5A

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Optimize VRM sense line to get the best DC voltage balance

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Remote Sense Line is needed when the power source cant be placed in the desired location
VR M
10A

Voltage Sense location

VR M
10A

Without feedback voltage sense to VRM

With feedback voltage sense to VRM

Load sees 100mV below nominal voltage (1V)

Load now sees nominal voltage (1V)

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Where to place the Sense Line when there are more than one device on the power rail?
Voltage Sense location
VR M
1A 10A

Voltage Sense location

VR M

1A

10A

This device sees too high voltage

This device sees too low voltage

1.08V

1V

1V 0.93V

This device sees perfect voltage

This device sees perfect voltage

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A typical way to find the optimal sense location

Chip1 (10A)

Chip2

Chip2 (1A)

Chip1

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A better way to find the optimal sense locations

[Patent Pending - U.S. Patent Application No. 12/468,807]

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[Patent Pending - U.S. Patent Application No. 12/468,807]

Device1 Voltage Level

Optimal VRM Output Voltage

Vout_VRM

Vnominal

Vdevice2
VRM

Device2

Objective = minimizing voltage differences between actual voltage at devices and nominal voltage With this example, Objective = min{ (Vdevice1 - Vnominal1)2+(Vdevice2 - Vnominal2)2+(VdeviceN - VnominalN)2} 1) 2) 3) 4) 5) Start without any sense line Determine the optimal output voltage level of VRM that meets the objective With using the VRM output voltage level from (2) search meshes that have the nominal voltage. The meshes that have the nominal voltage is the optimal sense locations. Optimal Sense Location Tolerance maybe used to display sub-optimal sense locations.

Vdevice1

Note that the rectangular meshes are used in the picture above to simplify the drawing and explanation.

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Optimal Sense Locations (Green)

1A

10A

1.035V

Voltage Sense location

0.965V

35mV

35m V

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Example
Where are the Optimal Sense Locations ?

VRM connector

11 devices, 1A each
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No sense line

Sense here

Sense at U1

Sense here

Optimal Sense Location

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What to look for in AC analysis?

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Flat and Low Power Plane Impedance

Where the breaking frequencies of capacitors on a system?

Power plane Impedance

< 100MHz

< 500KHz

~1KHz

~200MHz Pkg decaps

Note: frequency numbers here are very rough estimated. They are depending on each design.

Target Impedance

Frequency (Log scale) Bulk Capacitors Board Decaps Regulator On-chip capacitance

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Low Loop Inductance from capacitors to a device

Loop Inductance = 1.2nH Loop Inductance = 0.043nH

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0402PKG Decap Mounting Inductance of different fanout type

0.512nH

0.551nH

0.592nH

0.249nH

0.299nH
Via right next to pad (may not allow by Mfg)

1.012mm

0.4mm

0.35mm 0.5mm

Er = 4

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Review Decap Mounting

TOP

BOTTOM

Total of 394 decap locations to be reviewed

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Review Decap Mounting in a flash

TOP

BOTTOM
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Total of 394 decap locations in review

Typical Decap Analysis VS Auto decap optimization

start start Setup Design 30 min Setup Design 30 min Perform Analysis 2 hr Perform Analysis 2 hr View Results 15 min Perform Optimization 4-6 hr done ??? stop View Results 30 min Modify Design 30 min stop

Auto decap optimization Typical Decap Analysis

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Auto Decap Optimization explores the entire decap design space while considering all critical design factors in much less engineering time.
Next decap combination?
Combination#1 Combination#2 Combination#3 Combination#... Combination#... Combination#... Combination#... Combination#... Combination#... Combination#.... Combination#... Combination#.... Combination#.... Combination#.... Combination#.... Combination#.... Combination#.... Combination#.... Combination#.... Combination#.... Combination#.... Combination#.... Combination#.... Combination#250,000

u1

u2

u3

u4

u17

u1

u2

u3

u4

u17

u1

u2

u3

u4

u17

Performance (Self Z, Transfer Z) Cost, Space BOM control Target Impedance Device Weighting Location Preference
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Optimization Result
There are many decap schemes for users selection Each scheme has a tradeoff between cost and performance

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The decap solution from auto decap optimization

Total Decap Cost = 5x0.004 + 2x0.005 + 4x0.0045 = $0.048

Total Setup Time: = 8mins Simulation Time: 1 min Optimization Time: 0.5min Total Time Spent = 10mins

50mohm

10nF 100nF 22nF

Remove
45MHz Conclusion Cost = $0.048 Time = 10 mins Performance = upto 45MHz
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# of decaps=11

BOM=3

Compare results from two approaches

Typical Analysis Decap Optimization Up to 45MHz $0.048 11 3 10mins
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Plane Performance Cost # of decaps BOM Total Time

Up to 40MHz $0.053 13 4 42mins

A new decap solution to fix anti-resonance power plane issue.

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Power plane impedance seen by each device

U2

VRM

U1
U150

TOP

BOT

U1

U2

U150

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A new decap solution yields better power plane impedance and 14% cheaper.
U2 U2

U1 U1

U1
U150 U150

TOP TOP

U2

U150
BOT BOT

Before

After
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Decap summary reports

*
ID 10 17 18 20 21 Total

Original Decap Summary Report

Part No. C_10nF_0402_GRM155R71C104KA88 C_100nF_0603_GRM188R71C104KA01 C_10uF_1206_GRM31MR60J106KE19 C_1uF_0805_LLA219R70J105MA01L C_1nF_0402_GRM155R71H102KA01 Capacitance (nF) 9.5 90.1 7099 1027 0.95 --Size 0402 0603 1206 0805 0402 --Quantity 43 10 10 2 3 68 Total Cost

1.32109

* NEW Decap Summary Report

ID Part No. 2 C_100nF_0402_GRM155R71C104KA88 4 C_220nF_0402_GRM155R60J224KE01 5 C_2p2uF_0402_GRM155R60J225ME15 6 C_470nF_0402_GRM155R60J474KE18 7 C_4p7uF_0603_GRM188R60J475KE19 8 C_1uF_0402_GRM155R60J105KE19 11 C_10uF_0603_GRM188R60J106ME47 17 C_100nF_0603_GRM188R71C104KA01 18 C_10uF_1206_GRM31MR60J106KE19 Total Capacitance (nF) 100 195 1204 340 2740 620 4991 90.1 7099 --Size 0402 0402 0402 0402 0603 0402 0603 0603 1206 --Quantity 4 6 2 15 1 5 1 1 7 42 Total Cost

1.16586

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Decap BOM simplification (Reducing decap part numbers)

Limited numbers of reels to be loaded into the machine.

Pick and Place machine

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Decap BOM simplification (Reducing decap part numbers)

U17
10 nF 47 nF 100 nF 220 nF 470 nF

U1

U2

U3

U4

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Decap BOM simplification (Reducing decap part numbers)

10 nF 47 nF 100 nF 220 nF 470 nF

Original Design
U17 U1 U2

U3

U4
Original Decaps Optimized Decaps

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Power Plane Noise improvement on Memory DIMM with measurement verification

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Observation and decap locations

Observe impedance at DRAM locations

This design is a high volume production. Cost should also be taken into account during optimization.
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The resonant peak is reduce by 50% while saving 6cents per board

U11 Original Design Scheme45(6cents saving) 50%

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New Decap placement

Original Decaps Scheme45

DecapLib_13 = 220pF 0402 DecapLib_14 = 2.2uF 0603 DecapLib_6 = 100nF 0402 DecapLib_@OPEN@ = no-pop

remove
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Time domain noise with real current excitation from Scheme45

Original Design

78mV

18% noise improved

Scheme45 (6cents saving)

9% cost saving

64mV

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Noise from new decaps(Green) is less than noise from original decaps(Red) across the frequency band.

Noise amplitude

Frequency
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SI / PI expertise + automation = optimized design BETTER and FASTER!

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