Switched-Capacitor Fundamentals

Fundamentals on Switched-Capacitor Circuits Jose Silva-Martinez
Switched Switched Capacitor Capacitor Switched Switched--Capacitor Capacitor

Circ its Circ its Circuits Circuits
Jose Silva Jose Silva- -Martinez Martinez
Texas A&M University 1 Spring, 2011
CHARGE CONSERVATION: Analytical methodology CHARGE CONSERVATION: Analytical methodology
T
t
1
|
2
|
1 n
2
1
n n
2
1
n+
T
| | |
1
V
+
-
2
V
+
1
|
2
|
- - -
1
C
2
C
-
|
-
EXAMPLE
-
- - -
for
2
|
0 )]
1
( V ) ( V [ C )]
1
( V ) ( V [ C
o e o e
0 )]
2
1
n ( V ) n ( V [ C )]
2
1
n ( V ) n ( V [ C
o
1
e
2 1
o
2
e
2 2
= +
for
1
|
) 1 ( V )
1
( V 0 )] 1 ( V )
1
( V [ C
e o e o
) 1 n ( V )
2
1
n ( V 0 )] 1 n ( V )
2
1
n ( V [ C
e
2
o
2
e
2
o
2 2
= =
THEN THEN
) 1 n ( v C ) 1 n ( v C ) n ( v C ) n ( v C
o
1 1
o
2 2
o
2 2
o
2 1
+ = +
1 o
1 1
o
2
1
2
o
2 2 1
Z ) Z ( V C ) Z ( V Z C ) Z ( V ) C C (

= +
1 1 2 2 2 2 1
) ( ) ( ) ( ) (
1
1
Z
C

1
1
1
2 2 1
1
1
1
oo
Z 1
Z
Z
C
C
C
C C
Z
C
) Z ( H
o o +
=
+
=
1 1
C C
Switched-Capacitor techniques advantages p q g
Reduced silicon area
Good accuracy. Time constants are implemented with
capacitor ratios (~0.1%)
Dont require a low-impedance output stage (OTAs could
be used)
Could be implemented using digital circuit process
technology
Very useful in ADCs (Algorithmic, Pipeline, Time Interleaved,
Sigma-delta) and baseband high-performance filters
Switched-Capacitor Filters Components
Basic Elements
Capacitors
CF
1 2
vi -
p
polysilicon
metal1-metal2
parasitics, clock-feedthrough
CR
CF
1
2
vo
Switches
N-MOS
Transmission gates
+
Noise and on-resistance
OTAS
DC-gain
Typical switched-capacitor integrator
DC-gain
settling time (GBW, phase
margin)
noise
Non-overlapping clock phases
Operational Transconductance Amplifier
PRACTICAL CONSIDERATIONS:
DC i Th i ti i t i t DC-gain. The inverting input is not a
real virtual ground. v
invert
=v
o
/A
dc
Settling time. C1 must be discharged
1 2
C1
Cf
Sett g t e C us be d sc a ged
during phase 1. The main limitation is
due to limited output current and phase
margin.
1
1
2
2
vi
vo
-
Clock feedthrough. Can be alleviated
by using especial clocking schemes.
Noise. In most of the practical cases
the dominant noise components are due
to the Switches!!!
Switched Switched- -Capacitor Integrator: Analysis Capacitor Integrator: Analysis p g y p g y
Phase 1
CF
2 / T t t t
0 0
+ s <
1 2
vi
v
-
CF
Phase 2
T t t 2 / T t
0 0
+ s < +
Vi(t
0
+T/2)
C1
vo
Basic Stray-Sensistive Integrator
1
1
1
1
t
t
2
+
Charge conservation Principle: Charge conservation Principle:
Charge injected by C1 is equal to the charge
absorved by CF (AQ =AQ )
t
0
2
2
2
AV
0
absorved by CF (AQ
CI
=AQ
CF
)
AV
0
CF = -AQ
C1
) 2 / NT t ( v
CF
1 C
v
0 i 0
+ = A
Switched Switched- -Capacitor Stray Capacitor Stray- -Sensitive Integrator Analysis Sensitive Integrator Analysis
1 2
vi -
( ) ( )
) t ( v ) 2 / NT t ( v
t v ) t ( v
) 2 / NT t ( v ) 2 / NT t ( v
t v ) t ( v
0 CF 0 CF
0 CF CF
0 i 0 1 C
i 1 C
= +
=
+ = +
=
Phase 1
CF
2 / T t t t
0 0
+ s <
C1
vi
vo
B i I t t
Charge conservation Principle:
Ch i j t d b C1 i l t th h
Phase 2 T t t 2 / T t
0 0
+ s < +
Basic Integrator
( ) ( ) | | ( ) ( ) | | 0 C ) 2 / T t ( v 0 C ) t ( v 0 C 0 ) 2 / T t ( v C 0 0
f 0 0 f 0 1 0 i 1
= + + +
Charge injected by C1 is equal to the charge
absorved by CF (AQ
CI
=AQ
CF
)
Solving for phase 2 (t=t0+T)
2 / 1
1
z C
) z ( H
=
1
f
z 1
C
) z ( H
=
Switched-Capacitor Integrators : Stray-Insensitive Integrators
1 1
vi -
1 2
Cin
Cf
Cin
Cf
2 2
vi
vo
1
2
vi
vo
-
Backward Integrator
Forward Integrator
( ) ( ) ( ) | |
Charge conservation ==>Phase 1
( ) ( ) ( ) | |
Charge conservation ==>Phase 1
( ) ( ) ( ) | | 0 C 0 ) 2 / T nT ( v C 0 ) nT ( v C 0 ) nT ( v
f 0 f 0 in i
= +
( ) ( )
f 0 f 0
C 0 ) T nT ( v C 0 ) 2 / T nT ( v 0 =
Phase 2
( ) ( ) ( ) | | 0 C ) 2 / T nT ( v C ) nT ( v C ) 2 / T NT ( v 0
f 0 f 0 in i
= +
) 2 / T NT ( v ) 2 / T NT ( v
) T nT ( v C ) 2 / T nT ( v C 0
i cin
0 f 0 f
=
=
Phase 2
Solving for phase 1
| | 0 C ) T nT ( v ) nT ( v C ) nT ( v
f 0 0 in i
=
1
in
1 C
) z ( H =
) ( ) (
i cin
| | 0 C ) T nT ( v ) nT ( v C ) 2 / T nT ( v
f 0 0 in i
=
2 / 1
in
z C
) z ( H
=
1
f
z 1
C
) (
1
f
z 1
C
) z ( H

Switched Switched- -Capacitor Backward Integrator Capacitor Backward Integrator
1 1
C2
C1
1
2 2
vi
vo
-
i
f
in
v
C
C
Backward Integrator
h 2 h 1
C i h d ( )
phase 2
C
in
is discharged (v
ci
=0)
and v
out
is constant
phase1
C
in
is charged (v
ci
=v
i
)
i in Cin
V C Q = A ( ) ) 2 / T nT ( V ) nT ( V C Q
o o f Cf
= A
( ) ( ) ( ) | |
) nT ( v
C
) T nT ( v ) nT ( v
0 C 0 ) 2 / T nT ( v C 0 ) nT ( v C 0 ) nT ( v
i
in
0 0
f 0 f 0 in i
=
= +
or
) (
C
) ( ) (
i
f
0 0
Switched-Capacitor Backward Integrator
1 1
C
in
C
f
2 2
vi
vo
-
i
f
in
v
C
C
+
Backward Integrator
h 1 h 2
i
f
in
0 0
) nT ( v
C
C
) T nT ( v ) nT ( v =
phase 1 phase2
0 0
) nT ( v ) 2 / T nT ( v = +
1
f
in
o
i
o
0
oo
Z 1
1
C
C
) z ( v
) z ( v
) Z ( H
= =
1
2 / 1
f
in
o
i
o
0
2 / 1
o
i
e
0
eo
Z 1
Z
C
C
) z ( v
) z ( v Z
) z ( v
) z ( v
) Z ( H
= = =
Switched-Capacitor Integrators: Fundamental limitations
1 1
H( 1) d i
2 2
vi
vo
-
H(z=1)=
H(z=-1)=-Cin/Cf
dc gain
Minimum gain
1
f
in
oo
Z 1
1
C
C
) Z ( H
=
H(Z)
T j
e Z
e
=
H(s)
H(Z) behaves as a good
Fs/2
Fs/4 Fs/8 Fs
f
H(s)
( ) g
emulated integrator if f<fs/4
Backward (series) integrator: Why is stray insensitive???
1 1
phase2
Cin
Cf
2 2
vi
vo
-
phase2
C
P1
C
P2
C
in
, C
P1
and C
P2
are discharged
(initial conditons=0)
phase 1
C
in
and C
P1
are connected to Vi
C is connected to the virtual
NOTE THAT NOTE THAT
C
P2
is connected to the virtual
ground (initial conditons=0)
NOTE THAT NOTE THAT
CP1 IS CHARGED BY vi
CP2 IS CONNECTED TO GROUND OR
VIRTUAL GROUND (provided that the gain of the
1
f
in
o
i
o
0
oo
Z 1
1
C
C
) z ( v
) z ( v
) Z ( H
= =
OPAM is large enough)
BOTH CP1 AND CP2 DO NOT
INJECT ANY CHARGE TO CF.
Texas A&M University Analog Filter Design JSM
INJECT ANY CHARGE TO CF.
Why SC-Circuits are important?? y SC C cu ts a e po ta t
Little sensitive to parasitics (due to
1 1
Little sensitive to parasitics (due to
the use of local feedback)
High precision (0.2-1 %) (function of
capacitor ratios and clock frequency)
Cin
C
f
2 2
vi
vo
-
1
f
in
oo
Z 1
1
C
C
) Z ( H
=
C
P1
C
P2
capacitor ratios and clock frequency)
+
f
Z 1

Reduced Silicon-Area (double poly
or metal-metal capacitors can be
easily implemented in CMOS) easily implemented in CMOS).
OPAMPS (VCVS) ARE NOT
REQUIRED; OTAS ARE FASTER
(Resistors are simulated by switches
(Resistors are simulated by switches
and capacitors).
Gain and Gain Bandwidth Product Gain and Gain Bandwidth Product
3
C
C
+
o o
i
V
3
C
o
V
1
C
2
C 4
C
o
i
V
3
C
1
C
C
C
x
V
2
C
4
C
Vx g
m
g
o
g
Basic Equations
( ) | | 0 V sC V sC C C C s V
o 3 i 1 3 2 1 x
= + +
| | ( ) | | 0 V C C s g sC g V
3 4 3
= + + +
| | ( ) | | 0 V C C s g sC g V
o 3 4 o 3 m x
= + + +
Solving the System => g y
=
m
3
1 o
g
C
s 1
C V
( ) ( )
|
|
.
|
\
| + +
+
+ + + +
+
+ +
+
=
v 3
3 2 1
m 3
2 1 3 3 2 1 4
v
3 2 1
3
i
A C
C C C
1 g C
C C C C C C C
s 1
A
C C C
C
V
Id l i
C
. \ v 3
A C
Ideal gain
Error due to
3
1
C
C
=
2 1
C C
1
+
+
Error due to GBW (speed)
- Consider the pole
v
3
o
m
v
A
C
g
g
A =
3
1
s
1
1
C
C
) s ( H
+
=
p
e
Pulse Response => Pulse Response => pp
i
3
1
t
o o o
V
C
C
e 1 ) t ( V ) t ( v
p
|
.
|
\
|
=
e
Error =
t
p
e
e
1
Error
@ t = T/2 =>
Error =
e
t
p
e
1
Error < 1%
2
e
0
t
e
p
> fs x 10
1 2 3
4
2 / T
p
t
e
ff
pp
> 2* > 2*fs fs Quite Quite
Important!! Important!!
fs 10
) C C (
C
C C C
g
4
m
p
> = e
Clock Phase
) C C (
C
C
C C C
2 1
3
4
4 2 1
+ + + +
Settling Time of Slew Settling Time of Slew -- Rate Rate gg
I i
2 o
V
B
I
'
V
B
I
o
i
B max 2 o
I i =
2 o
2 o
i
' o
V
1
i
V
2
i
V
0
B
I 2
B
I
o
V
DSAT
V 4 . 1
DSAT
V 4 . 1
3
C
fb
i
i
V ~
I V > 1 4 V Diff i >
i
V
3
1
C
o
i
fb
i
x
V
I
f
V
x
> 1.4 V
DSAT
Diff pair =>
i
o
= I
omax
+
o o
2
C
4
C
1 o
i
i
o
= i
fb
- i
o1
v
x
(C
1
+ C
2
+ C
3
) = C
1
V
i
+ C
3
V
o
Solving
) t t ( I V C
) C C (
C
C
C C C
) t t ( I
C C
C C
C C
V C
) t ( V
2 1
3
4
4 2 1
o max o
4 3
4 3
2 1
i 1
x
+ + + +

+
+ +
=
) C C (
C
C C C
) t t ( I
C C
C C
V C
) t ( V
4
o max o
4 3
i 1
x
=
) C C (
C
C C C
C C
C C
2 1
3
4
4 2 1
4 3
4 3
2 1
+ + + +
+
+ +
max o 3 2 1
I ) C C C (
l
+ +
V
4 2 1 3 4 2 1
max o 3 2 1
C ) C C ( C ) C C C (
) (
slope
+ + + +
~
+
o
V A
x
V
+
o
V A
When V < 1 4 V the system is linear and When V
x
< 1.4 V
DSAT
the system is linear, and
( )
i
1
t
o o o
V
C
C
e 1 ) t ( V ) t ( v
p
e
=
3
C

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Fundamentals on Switched-Capacitor Circuits Jose Silva-Martinez

Switched Switched Capacitor Capacitor Switched Switched--Capacitor Capacitor

Fundamentals on Switched-Capacitor Circuits Jose Silva-Martinez

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