Steps to make the inverters layers on the wafer in the foundry: 1. Make p-substrate.

We start with a si wafer; add boron impurity into si substrate to make it p-type, so we call it p-substrate or just p-sub. 2. Add a SiO2 layer to the top of the p-sub wafer by injecting the Oxide to psub surface, and baked in a very high temperature around 900 to 1200 degree C, to make the SiO2 layer on the surface of the p-sub. Building SiO2 layer is called Oxidation the silicon layer, in general is heating the silicon in an oxidation atmosphere. There are three ways to Silicon Oxidation: Wet Oxidation: The oxidation atmosphere contains water vapor, usually is heated with 900 to 1000 degree C on 2:1 hydrogen vs oxygen ratio oxidation. Faster oxidation process for building thicker oxides. Dry Oxidation: The oxidation atmosphere is pure oxygen, temperature is around 1200 degree C; slower process used to build thin oxide. ALD (Atomic Layer Deposition): Use a thin chemical layer to attach to a surface first, then place another layer to the top of the thin layer to build another layer. 3. Use a process called photolithography process to build the NWELL layer and also other layout drawn layer to the silicon wafer. First, add a photoresist layer to the top of the SiO2 to have the light effect; and add photomask layer to mark the area to let the light go through the photomask layer and go to the particular photoresist layer. For positive photoresist, the marked photoresist area will let the light go through and will be cut for making the nwell area; for negative photoresist, the marked area will be kept, and the unmarked photoresist area will be resolved or etched away. We will use positive photoresist in this class. 4. Expose to the light, the marked photoresist area will be resolved and disappeared; as we are using positive photoresist. The light wavelength lumda can influence the cut width (2b) : 2b=(k1*lumda)/NA ( where NA=n*sin(a); n is the media refactive index; k1 is the factor about 0.5 to 0.8); When applying the light to go through the photoresist, there are several techniques to improve light pass through: RET (Resolution Enhancement Techniques): modify the incoming light amplitude, phase, direction, so the layout end of line receives less light than the center layout, to have nonuniform light exposure. OPC (Optical Proximity Correction): makes small changes on the layout mask corner to reduce undesired rounding. OPC enhancement becomes necessary on the 0.18u or below designs. PSM (Phase Shift Masks): takes advantage of the masks parallel line diffraction grating effect, to change the mask thickness so the adjacent lines light are out of phase, and cancel PSM when light is not needed. 5. Cut the marked SiO2 area using the hydrofluoric acid (HF), so we can inject the n-type impurity to make the n-well region inside thep-sub next.

6. Inject the n-type impurity to make the n-well region inside the p-sub bulk. In CMOS technology, well area can be p-well, n-well, twin well, deep nwell. Twin well means make nmos sit inside p-substrate body, and make pmos sit inside nwell body; deep nwell means make nmos sits inside pwell, and make pwell sit inside deep nwell body, and deep nwell sit inside p-sub body. When building nwell area, three ways can be used: Epitaxy: growing a single-crrystal film on top of th esilicon body surface, and place the silicon surface to high tempeartue with dopant material. Deposition: placing the dopant material on top of the silicon surface, and then driving the dopant into the silicon bulk using the thermal diffusion step. CVD (Chemical Vapor Deposition) is used to deposit the dopant with the high temperature gas into the silicon bulk. Ion Implantation: bombarding the high energy donor (electron) atom or acceptor (hole) atom into the si bulk surface, then diffuse into the si bulk with high temperature. Ion Implantation is the most popular way to build the well. 7. Remove the SiO2 layer on top of the unmarked area on top of the p-sub wafer. So now you have the n-well area. 8. Add a Thin-Oxide layer on top of the p-sub.

9. Add a Poly layer on top of the Thin-Oxide layer by the process called Chemical Vapor Deposition CVD. 10. Add a photoresist layer on top of the Poly layer. Add two Poly markers on photoresist layer, expose to light, cut the unmarked photoresist, Poly SiO2 layers. So now you have the two Poly for nmos gate and pmos gate. 11. Add a SiO2 layer on top of the p-sub, cover the two Polys too. 12. Add a photoresist layer on top of the SiO2; mark the area to be cut for two nmos source drain, and one for pmoss ntap pin inside the n-well area. Expose to the light, cut the marked photoresist SiO2 area; 13. Injected the n-diff impurity to the two n-type source drain areas, and one n-tap area inside the n-well region. After the n-diff injection, cut the unmarked SiO2; now you have the nmos two source drain, and pmoss ntap pin inside n-well. 14. Add a SiO2 layer on top of the p-sub; add a photoresist layer on top of SiO2 layer; mark the photoresist area to be cut for pmos source drain, and for nmoss ptap pin inside p-sub substrate.

15. Injected the p-diff impurity to the two pmos source drain areas inside the n-well, and one for nmoss ptap pin inside the p-sub substrate. iAfter the p-diff injection, cut the unmarked SiO2; now you have the pmos two source drain inside the n-well, and nmoss ptap pin inside p-sub substrate. 16. Add a Thick Oxide layer on top of the p-sub; add a photoresist layer on top of the Thick Oxide layer; mark the area and injected the metal1 layer to the metal contacts to the pmoss two p-diff source drain pins, ntap pin; and for nmoss two n-diff source drain pins, and one ptap pin. Now you have the complete inverter layers in the wafer.