Low-Power Design of CML Drivers for On-Chip Transmission-Lines

Akira Tsuchiya Takeshi Kuboki Hidetoshi Onodera

Dept. Communications and Computer Engineering, Kyoto University Yoshida-honmachi, Sakyo-ku, Kyoto 606-8501, Japan {tsuchiya, kuboki, onodera}@vlsi.kuee.kyoto-u.ac.jp

Abstract In this paper, we discuss a design technique to reduce the power dissipation of CML buers for on-chip transmissionlines. CML buers can operate in higher frequency than conventional static CMOS buers. On the other hand, the power dissipation is larger than that of the static CMOS buers. We reduce the power dissipation by using an impedance-unmatched driver. From the pole frequency analysis, our method can decrease the tail current without degrading the throughput of the CML buer. Experimental results show that our method can reduce the power dissipation by 25%.

VDD RD Vout1 Vin1 CL Itail M1 M2 Vin2 CL RD Vout2

I. Introduction According to the continuous improvement of the LSI fabrication technologies, the performance of LSIs is rapidly accelerating. One of the big challenges in high-performance LSIs is the interconnect bottleneck problem. The on-chip interconnection is becoming a limitation of the whole chip performance because the performance of on-chip wires does not improve by technology scaling. At the same time, the multi-core architecture is a trend of microprocessor design [1]. In such LSIs, on-chip buses have strong impact on the chip performance and on-chip interconnection is required to achieve higher bandwidth [2]. Thus on-chip high-speed communication is one of the hot topics and several methods are developed [37]. In high-speed communication, the primal elements of the signaling system are the driver, the receiver and the interconnect. The on-chip interconnects can transmit 10Gbps or higher bit rate [8] and the bottleneck is the driver circuit. To realize highspeed circuits, current-mode-logic (CML) is one of the solutions [912]. However CML buers have more design parameters comparing static CMOS inverter [13]. CML buers can operate in higher frequency and have tolerance to the common mode noise, but CML buers require the static current ow and the power dissipation is larger than that of the static CMOS buers. Thus low-power design of CML buers is discussed [14]. This paper proposes a low-power design of CML buers for on-chip transmission-lines. Conventionally, impedancematched driver is a common practice for transmission-line drivers [13]. The proposed method use an impedanceunmatched driver to reduce the power dissipation. Impedanceunmatched driver cause reection of the propagating wave, however the reected wave rapidly attenuates on on-chip transmission-lines. Therefore the impedance-mismatch is not a serious problem. We use a resistance larger than the characteristic impedance as the pull-up resistance. By using the larger resistance, we can reduce the tail current. From the pole frequency analysis, we can reduce the tail current without degrading the

Fig. 1. CML dierential buer.

bandwidth of the buer. We experimentally verify the proposed method. The contribution of this paper is a low-power design method that does not degrade the bandwidth. Section II explains fundamentals of CML buers for on-chip transmission-lines. In Section III, we show a relationship between the pole frequency and the bandwidth of CML buer. Section IV describes the proposed method and Section V shows experimental results. Section VI concludes this paper.

II. Fundamentals of CML Buffer In this section, fundamentals of CML buer are explained. First, the basic operation of CML buers is explained. Next, the design guideline of Ref. [13] is introduced.

A. Basic operation of CML buer Figure 1 shows a basic CML buer. The CML buer is based on the dierential architecture. The main components of the CML buer are two pull-up resistors RD , two nMOS transistors for switching and a current source Itail . NMOS transistors control the current ow of each side of the dierential pair according to the dierential input. CML buers can operate in high frequency because no pMOS transistor is used and the nMOS transistors are always in saturation region. Figure 2 shows a transfer characteristic of the CML buer. As the dierential input (Vin1 Vin2 ) varies, each output voltage varies from (VDD RD Itail ) to the supply voltage VDD . Thus the range of the dierential output voltage (Vout1 Vout2 ) is from RD Itail to RD Itail . By assigning each condition to 0 and 1, the CML buer can transmit dierential signal.

VDD

Vout1

Vout2 RD Itail = Vout

N stages

1st

2 nd

N th

differential transmission-line

VDD - RD Itail Vin1 - Vin2

u N-1=X

Vin, min

Fig. 3. Tapered driver.

Fig. 2. Transfer characteristics of CML dierential buer.

B. Conventional design guideline of CML buer The CML buer shown in Fig. 1 is the basic of dierential amplier [15] and a design guideline to use as a driver is already discussed [13]. From Fig. 1, design parameters of a CML buer are the pull-up resistance, the size of the nMOS transistor and the tail current. Generally, the pull-up resistance RD is tuned to the characteristic impedance of the transmission-line to achieve impedance matching. The size of the nMOS transistor is determined by the constraint of CML buer operation. As shown in Fig. 2, a certain input voltage is needed to swing the output voltage from (VDD RD Itail ) to VDD . When all of the tail current ows through either nMOS transistor, the output voltage swing reaches RD Itail . From the square law of nMOS drain current, the relationship between the tail current and the minimum input voltage Vin, min is expressed by 1 W 2 Itail = Cox Vin, min , (1) 2 L where is the mobility, Cox is the gate capacitance par unit area, W and L are the gate width and the gate length respectively. The mobility and the gate capacitance Cox are determined by the fabrication process and the gate length L is set to the minimum value in the fabrication process. Therefore the freedom in the nMOS transistor is only the gate width W. To drive the next stage, the output voltage has to be larger than the minimum input voltage. Vout Vin, min . (2) From Eq. (1) and Eq. (2), The gate width W is determined by W 2LItail . 2 Cox Vout (3)

uation in the transmission-line, the output voltage Vout is expressed by Vinreceiver , min Vout , (5) exp(l) where and l are the attenuation constant and the length of the transmission-line respectively. According to this design guideline, the design parameters are xed when the characteristic impedance of the interconnect and the required voltage swing is given. C. Tapered CML buer On-chip CML driver has to drive a dierential transmissionline. The characteristic impedance of on-chip dierential lines is typically in the range from 50 to 200. To drive such low impedance load, the tail current becomes large and the size of the switching transistor becomes large. Therefore tapered buers are used and the number of stages and the taper factor are also design parameters. Figure 3 shows a tapered driver. In Fig. 3, the number of stages is N and the taper factor is u. In this discussion, the input stage of the tapered driver is written as the 1st stage. The last stage is the N-th stage. The transistor size and the tail current gradually scale up with the taper factor u. In opposite, the pull up resistance scales down with the taper factor u. The relationship between the k-th stage and the k + 1-st stage is expressed as RD = RD /u k+1 k , (6) Wk+1 = uWk I tailk+1 = uItailk the subscript k + 1 and k denote the (k + 1)-st stage and the k-th stage respectively. The parameter X is the ratio between the rst stage and the last stage and is equal to uN1 . The latency of tapered CML buer is discussed in Ref. [13] and Ref. [13] concludes that the delay of CML buer has similarity with static CMOS buer and the number of stages becomes optimal when the number of stages N satises ( ) N ln uN1 . (7) In other word, the optimal taper factor is Napiers constant e. On the other hand, the bandwidth is also an important metric of CML driver. From the viewpoint of the bandwidth, the taper factor and the number of stages change the gain curve of the CML buer. As the taper factor u becomes small, the pole frequency shifts toward high frequency because the load capacitance becomes small. However as the number of stages increases, the gain drops rapidly in high frequency region. An

Equation (2) is the lower limit of the output voltage. The upper limit of the output voltage depends on the threshold voltage Vth . For high-speed operation, nMOS transistors should operate in the saturation. From this constraint, the maximum output voltage is derived as [13] Vout = RD Itail Vth . (4)

The last design parameter Itail is determined from the output voltage swing. The nal stage of CML driver has to drive the transmission-line and the receiver. In on-chip transmission-line, loss of the transmission-line is not negligible. Therefore the lower bound of the output voltage Vout is larger than the minimum input voltage of the receiver. By considering the atten-

20 15 10 Voltage gain [dB] 5 0 -5 3 stages 2 stages 5 stages 4 stages

VDD

Vout1

Vout2

-10 -15 -20 -25 0.1 1.0 Frequency [GHz] 10

CL

Vin1 Itail

Vin2

CL

Fig. 4. Gain curve of tapered CML buers. (X = 5) Fig. 5. Parasitic capacitances in CML buer.

u N-1=X

Fig. 6. Experimental circuit for eye-diagram evaluation.

III. Pole Frequency Analysis of Tapered CML Buffer In this section, we propose the pole frequency as an indicator of the bandwidth of CML buers. As mentioned in the previous section, the design parameters RD , W and Itail are determined by the characteristic impedance of wire and the required voltage swing. Therefore in this section, the design freedoms are the taper factor u and the number of cascade stages. A. Pole frequency of CML buers The voltage swing of CML buers is limited because it should be smaller than the threshold voltage. Thus we can expect that we can estimate the performance of CML buers by the small signal analysis. The pole frequency of CML buer shown in Fig. 1 is determined from the resistor and the capacitor connected to the drain of the switching transistor [15]. The pole frequency p is expressed as p = 1 , RD C L (8)

In reality, there are several parasitic capacitances as shown in Fig. 5. The overlapping or adjacent wires and the polysilicon resistor are the main causes of the parasitic capacitances. Therefore we have to take these parasitic capacitances into consideration.

B. Relationship between pole frequency and eye-diagram To evaluate the performance of CML buers, we evaluate the eye-diagram by circuit simulation. The experimental circuit is shown in Fig. 6. The CML buer is designed in accordance with the design guideline explained in Section II. We use a 180nm . CMOS process whose supply voltage is 1.8V. The required voltage swing is set to 0.48V in dierential. The ratio between the rst stage and the nal stage X is xed to 5 and the number of stages is changed. The input is a random Non-Return-to-Zero sequence. The input pulse shape of trapezoidal and the rise/fall time is one tenth of the minimum pulse width. The output of the buer is terminated by the resistor that represents the characteristic impedance of the transmission-line. We evaluate the eye-diagram at the output of the buer. Figure 7 shows the eye opening voltage and the input frequency. As the input frequency becomes higher, the eye opening voltage degrades. In Fig. 7, the lowest pole frequency of each conguration is also shown. We calculate the pole frequency from the pull-up resistor RD , the drain-backgate capacitance, the gate capacitance and the parasitic capacitances shown in Fig. 5. From Fig. 5, the pole frequency indicates the frequency where the eye opening voltage starts to degrade. Therefore we propose the pole frequency as an indicator of the performance of CML buers.

if there is no parasitics. Without considering the parasitic capacitances, the load capacitance CL is the sum of the drain-backgate capacitance and the gate capacitance of the next stage. Then the pole frequency of tapered CML buers is expressed as p = 1 ( ), RDN CDBN + uCGN (9)

where RDN , CDBN and CGN is the pull-up resistance, the drainbackgate capacitance and the gate capacitance of the nal stage of tapered buer respectively.

example of gain curves is shown in Fig. 4. Figure 4 is the result of circuit simulation. The nal stage of the buer is designed to drive a dierential transmission-line whose dierential characteristic impedance is 100. The ratio of the rst stages and the nal stage is xed to 5 and we change the number of stages. As shown in Fig. 4, the gain of the 2-staged buer starts to drop from the relatively low frequency. The gain curve of the 5-staged buer remains to be at, however, the gain drops rapidly in the higher frequency. Therefore on the bandwidth, it is not clear how many stages or taper factor maximize the bandwidth of CML buer.

random NRZ
1st 2 nd

N stages

Eye-diagram evaluation
N th

bridge termination (100 )

5.6

14.5 18.9 21.6

0.5 Eye opening voltage [V] 0.4 0.3 0.2 0.1 2 stages (pole: 5.6GHz) 0 0 10 20 30 40 Frequency [GHz] 50 60 70 4 stages (pole: 18.9GHz) 3 stages (pole: 14.5GHz)
Pole frequency [GHz]

100

5 stages (pole: 21.6GHz)

10

Parasitics of Tr Parasitics of wire are dominant are dominant 0.1 10 100 1000 Pull-up resistance [Ohm]

Fig. 7. Eye opening voltage and pole frequency. (X = 5)

Fig. 8. Pull-up resistance and the pole frequency.

IV. Low-Power Design of CML Buffer This section proposes a design technique to reduce the power dissipation of CML buers without degrading the bandwidth. A. Power reduction by impedance-unmatched driver According to Section II, the tail current is determined by the pull-up resistance and the required voltage swing. Conventionally, the pull-up resistance is tuned to achieve impedance matching because impedance-matched drivers suppress the reection of the electromagnetic wave and improve the signal integrity. However on on-chip transmission-lines, the attenuation is signicant and the reected wave attenuates rapidly. Therefore impedance mismatch does not cause serious problem in signal transmission and we can use impedance-unmatched drivers [16]. From Eq. (4), the product of the pull-up resistance RD and the tail current Itail have to be constant value because the output voltage swing Vout is a given parameter. If we can increase the pull-up resistance RD , we can decrease the tail current Itail . On the other hand, tuning the pull-up resistance does not degrade the bandwidth of the CML driver. From Eq. (8), the pole frequency is expressed as the inversion of the product of the resistance RD and the capacitance CL . The load capacitance CL is composed by the gate capacitance, drain-backgate capacitance and parasitics as shown in Fig. 5. We can classify the components of the load capacitance as below; CTr : Parasitic capacitance of the nMOS transistor. This capacitance is proportional to the transistor size. CRD : Parasitic capacitance of the pull-up resistor. This capacitance is proportional to the resistance RD . Cwire : Parasitic capacitance of metal wires. This capacitance is independent to the design parameters. In this paper, we assume that the pull-up resistance is realized by polysilicon. Thus the capacitance CRD is proportional to the resistance RD . To drive on-chip transmission-lines, the output impedance of the driver has to be comparable small to the characteristic impedance and the transistor size has to be large. Therefore in the CML driver for on-chip transmission-lines, the component CTr is dominant and the load capacitance CL is approximately proportional to the size of the transistor.

From Eq. (3), the transistor size is proportional to the tail current. As explained in Section II, the product of RD and Itail is determined by the output voltage swing. Thus the pole frequency can be rewritten as p = 1 1 1 = const. RDCL RD W RD Itail (10)

Therefore if the load capacitance CL is proportional to the transistor size, the pole frequency does not change by tuning the pull-up resistance RD . As a result, the impedance-unmatched driver can reduce the tail current without degrading the bandwidth. We experimentally verify the impedance-unmatched driver in the next section. B. Relationship between the pole frequency and the pull-up resistance If the load capacitance CL is proportional to the gate width, we can decrease the tail current by increasing the pull-up resistance. However the load capacitance includes the parasitic capacitance of wire and the pull-up resistance. The wire parasitics is not depends on the gate width. If we realize the pull-up resistor by polysilicon, the parasitic capacitance of the resistance is proportional to the resistance value. When the gate width is large and the gate capacitance and the drain-backgate capacitance is dominant, we can reduce the tail current without degrading the bandwidth of the CML buer. As the size of switching transistor decreases, the parasitic capacitance of wires and the resistance becomes signicant. In this case, the pole frequency shifts to the lower frequency as increasing the pull-up resistance. Figure 8 shows the relationship between the pull-up resistance and the pole frequency. The parasitic capacitances are extracted from a CML buer designed in a 90nm CMOS process. When the resistance is small, the switching transistor is large and the gate capacitance and the drain-backgate capacitance is dominant. In this region, the pole frequency is almost the constant even the pull-up resistance is changes. As the resistance becomes larger, the parasitic capacitance of wire and that of the resistance becomes dominant. Thus the pole frequency becomes lower when the pull-up resistance is large. Therefore the proposed method is limited by the parasitic capacitance of wires and that of the resistance.

driver X=uN-1 Random input (differential)

Eye-diagram evaluation
eye opening voltage [V]

0.5 N=4 0.4

1 u

u N-2

terminator

cascade

0.3

Fig. 9. Experimental circuit.

0.2 16 18

RD=50 Ohm RD=100 Ohm 20 22 24 26 frequency [GHz] 28 30 32

V. Experimental Results In this section, we show some experimental results of the impedance-unmatched driver. First, we explain the simulation setup. Next, the bandwidth and the power dissipation of impedance-unmatched drivers are evaluated by circuit simulation. A. Simulation setup The experimental circuit is shown in Fig. 9. We evaluate the bandwidth of the cascaded driver. The CML buer is scaled by a constant taper factor u and the number of stages is N. The ratio X is the ratio between the rst stage and the last stage and is expressed by X = uN1 . The input of the driver is a random NonReturn-to-Zero pulse sequence. To evaluate the performance of the driver, we assume that the transmission-line is lossless and the length is zero. Thus the output of the driver is directly connected to the bridge termination. A 90nm CMOS process is assumed as the fabrication process and the supply voltage is 1.0V. We evaluate the eye-diagram at the output of the driver. B. Comparison between impedance-matched and impedanceunmatched driver We x the ratio X to 9 and vary the number of stages N. We assume that the dierential characteristic impedance of the transmission-line is 100. Therefore the resistance of the terminator is 100. If we tune the driver to achieve impedance matching, the pull-up resistance of the nal stage is 50. We set the pull-up resistance 100. Figure 10 shows the simulation result. The x-axis is the frequency of the input pulse and the y-axis is the eye-opening voltage. The number of stages is 4 and 5. The taper factor u is 2.08 and 1.73 respectively. From Fig. 10, the eye-opening voltage is almost the same even if the pull-up resistance RD is changed. The comparison of the total tail current is shown in Table I. From Fig. 10 and Table I, impedance-unmatched driver reduces the total tail current by 25% without degrading the bandwidth. VI. Conclusion A design technique to reduce the power dissipation of CML driver is proposed. Conventionally, impedance-matched driver is a common practice of the driver design. We use a impedanceunmatched driver whose pull-up resistance is larger than that of impedance-matched driver. By using larger pull-up resistance, we can reduce the tail current of CML buers. From the pole
eye opening voltage [V]

0.5 N=5 0.4

0.3

0.2 16 18

RD=50 Ohm RD=100 Ohm 20 22 24 26 frequency [GHz] 28 30 32

Fig. 10. Input frequency and the eye-opening (X = 9, N = 4, 5).

TABLE I Total tail current of the driver.

#stages matched-driver proposed (N) (RD = 50) (RD = 100) ratio 4 13.9mA 10.4mA 0.748 5 16.5mA 12.4mA 0.752 6 19.2mA 14.4mA 0.750 8 24.6mA 18.5mA 0.752 : (ratio)=(proposed)/(matched-driver)

frequency analysis, our method can reduce the power dissipation without degrading the bandwidth. Experimental results show that the impedance-unmatched driver reduce the tail current by 25% and its bandwidth is almost the same as that of the conventional impedance-matched driver.

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