BASICS OF VLSI-MINI PROJECT

ANALYSIS OF SRAM DELAYS AND STATIC NOISE MARGIN

DAVIS OOMMEN ABRAHAM (M101233EC) RICHU JOSE CYRIAC (M120128EC) INTRODUCTION This project looks upon delays associated with SRAM write and read operations at preand post layout stages. It also looks upon how the cell ratio (CR) and widths of access transistors affect the speed of operation with respect to 0.18m technology. Finally a comparative value for different types of Static Noise Margin (SNM) is also computed. THEORY The conventional 6T SRAM bit cell consists of two cross-coupled inverters and two access transistors a four transistors comprise(M1, M2, M3, M4 ) cross coupled CMOS inverters which form a latch and store either a 1 or a 0. Two NMOS transistors (M5 and M6 ) function as the access transistors that isolate the cell from the bit lines during the hold state and provide access to the cell during the read and write operations.

Fig 1: 6T SRAM

READ OPERATION Prior to the start of the read operation, both the bit lines BL and BLBAR are precharged to VDD. After the bit lines are precharged, the read operation is initiated by asserting the word line to VDD; thereby connecting the two bit lines to the internal nodes of the cell. Based on the voltage stored at the two nodes of the bit cell, the bit line adjacent to the node containing 0 is discharged and the other bit line is held at 1.

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The conditions for a successful write operation can be derived using the current equations at the node QBAR
2 kn, M 5((VDD V VTn)VDSATn VDSATn) kn, M1((VDD VTn)V V ) 2 2 2

eqn (1.1) eqn(1.2)

VDSATn CR(VDD VTn ) VDSATn (1 CR) CR 2 (VDD VTn) 2 CR

CR

W 1 / L1 W 5 / L5

eqn(1.3)

Fig 2: reading 1 when CR=1 and PR=3

VARIATION OF READ DELAY WITH RESPECT TO CELL RATIO DELAY BL rise time BLBAR fall time CELL RATIO=1 0.09 ns 0.05 ns CELL RATIO=2 0.067 ns 0.043 ns CELL RATIO=2.5 0.064 ns 0.041 ns

Table 1: time delays associated with reading 1 with respect to variations of cell ratios

OBSERVATIONS Changing the Cell Ratio, speed of SRAM cell increases. If cell ratio increases, then size of the driver transistor also increases, for hence current also increases. As current is an increase, the speed of the SRAM cell also increases.

WRITE OPERATION Prior to the start of the write operation, one of the bit lines is precharged to VDD and the other bit line is driven to ground. The bit line adjacent to the node containing 0 is precharged to 1 and the bit line adjacent to the node containing 1 is precharged to 0. After the bit lines are precharged, the write operation is initiated by activating the word line, thereby connecting the two bit lines to the internal nodes of the cell. When the voltage at node Q falls below the

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switching-threshold of the inverter pair (M3-M4), the state of the inverter( M3-M4) toggles; in this case from 0 to 1 and the new values are written to the cell. The ease with which the node voltage at Q decreases to a value lesser than the switching threshold of the adjacent inverter (M3-M4), translates to the write ability of the cell. The conditions for a successful write operation can be derived using the current equations at the node Q

kn, M 6((VDD VTn)VQ V Q ) kp, M 4((VDD VTp )VDSATp V DSATp ) 2 2

2 2

eqn(1.4) eqn(1.5) eqn(1.6)

VQ VDD VTn (VDD VTn) 2 2

p V 2 DSATp PR ((VDD VTp )VDSATp n 2

PR

W 4 / L4 W 6 / L6

The write ability depends on the pull-up ratio (PR) of the SRAM cell .For 0.18m technology the range cell ratio and pull-up ratio should be in 1-2.5 and 3-4 respectively otherwise data will be destroy.[1]

Fig 3: Writing 0 when CR=1 and PR=3

SRAM WRITE DELAY The rise time of Q is defined as SRAM write delay. WRITING 1 Case 1: ALL TRANSISTORS ARE OF W=240 nm and L=180 nm Q rise time=0.09 ns QBAR fall time=0.04 ns Case 2: ACESSS TRANSISTORS(M5 and M6) ARE OF W=480 nm and L=180 nm Q rise time= 0.08 ns QBAR fall time= 0.03 ns

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OBSERVATIONS Fall time of the QBAR is 0.04 ns. This time is much smaller than the write delay because an NMOS switch has less channel resistance for passing a 0 than for passing a 1. With the width of both access transistors doubled, write delay of Q and fall time QBAR of the internal node reduce to 0.08ns and 0.03ns, respectively. It can be accounted due to reduction in the resistance of the access transistor which allows the input voltage to drop more across the SRAM transistor than the access transistor. COMPARISON OF PRE-LAYOUT AND POST-LAYOUT SIMULATIONS OF READ AND WRITE DELAYS. Parameter Q rise time(writing) QBAR fall time(writing) BLBARfalltime(reading) Pre Layout 0.09 ns 0.04 ns 0.043 ns Post Layout 0.134 ns 0.029ns 0.051 ns

Table 2: Delay comparison in reading 1 when CR=1 and writing 1 when PR=3

STATIC NOISE MARGIN Static Noise Margin (SNM) SNM is the measure of stability of the SRAM cell to hold its data against noise. SNM of SRAM is defined as minimum amount of noise voltage present on the storing nodes of SRAM required to flip the state of cell SNM can be computed as the length of the side of a maximum square nested between the two voltage transfer characteristic (VTC) curves (i.e., for each back to back inverters) of SRAM cell .SNM can be categorized into two types: Hold SNM and Read SNM. Hold SNM is the SNM of the cell when WL (word line) is LOW or disabled, meaning that the cell is in standby mode. SNM was calculated by the method mentioned in the reference[3],[4],[5].To plot the butterfly graphs the characteristics of two cross coupled inverters were plotted using Microsoft Excel then flipped and merged using transparent tool in Microsoft Paint

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OUTPUT GRAPHS

Fig 4 : hold SNM with QBAR on Y-axis and Q on X-axis

Fig 5: Read SNM with QBAR on Y-axis and Q on X-axis

Fig 6: Write SNM with QBAR on Y-axis and Q on X-axis

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BASICS OF VLSI-MINI PROJECT

OBSERVATIONS Hold SNM= 0.8 V Read SNM= 0.6V Write SNM= 0.7V REFERENCES [1] Debasis Mukherjee1, Hemanta Kr. Mondal and B.V.R. Reddy, Static Noise Margin Analysis of SRAM Cell for High SpeedApplication, IJCSI International Journal of Computer Science Issues, Vol. 7, Issue 5, September 2010. [2] Jan M. Rabaey, Anantha Chandrakasan, Borivoje Nikolic, "Digital integrated circuit A design perspective" second addition, Prentice Hall electronics and VLSI series. [3] E. Seevinck, F. J. List, and J. Lohstroh, "Static-noise margin analysis ofMOS SRAM cells," IEEE J. Solid-State Circuits, vol. SC-22, no. 5,pp. 748-754, Oct. 1987. [4] http://.michaelwieckowski.com/?p=27 [5] vnividiwiki.ee.viginia.edu/mediawiki/index.php/ToolsSimulationMemoryStaticNoiseMargin

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