Professional Documents
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by
______________________________________________ Alex C. DiDonato ______________________________________________ Ryan T. Dupuis ______________________________________________ Tyler W. Folsom
__________________________________________ __________________________________________ Professor John McNeill Professor Demetrios Papageorgiou Project Advisor Project Advisor
ABSTRACT
This MQP involved the design, construction, and testing of an Ultra-Efficient, High-Powered, Class-D audio amplifier. The main goal was to achieve 95% efficiency using the 42 Volt PowerNet Standard. The signal processing stage was completed using a three-level Sigma-Delta Modulation scheme which powered a MOSFET H-Bridge configuration. Testing confirmed that the goal of 95% efficiency was met, and an RMS power of 400 Watts was produced using a 42 Volt supply.
Acknowledgements
We would first like to thank Analog Devices, Texas Instruments, and Allegro Microsystems for sponsoring the Analog MQP lab. Without their continued support, the resources needed to fund this project would not have been available. We would also like to thank all the companies that were willing to donate free samples for us to perform testing in lab. These companies included Fairchild Semiconductor, Texas Instruments, Intersil, and Analog Devices. A huge thank you goes out to Tom Angelotti for all his patience and willingness to help us when we needed anything from the shop. The most thanks goes out to our MQP advisors Professor McNeill and Professor Papageorgiou for all their guidance and support throughout the year. Without their willingness to always bestow their knowledge and help when in dire need, our MQP would not have been a success.
TABLE OF CONTENTS
ABSTRACT ............................................................................................................................................................................... 2 ACKNOWLEDGEMENTS ...................................................................................................................................................... 3 TABLE OF FIGURES .............................................................................................................................................................. 5 EXECUTIVE SUMMARY ....................................................................................................................................................... 7 1 2 INTRODUCTION............................................................................................................................................................ 9 BACKGROUND ............................................................................................................................................................ 10 2.1 WHAT IS CLASS-D...................................................................................................................................................10 2.2 METHODS OF ACHIEVING CLASS-D.........................................................................................................................12 2.2.1 Pulse Width Modulation ....................................................................................................................................12 2.2.2 Sigma-Delta Modulation....................................................................................................................................15 2.2.3 Digital Signal Processing ..................................................................................................................................18
2.2.3.1 S/PDIF ....................................................................................................................................................................... 19
2.3 2.4 2.5 2.5.1 2.5.2 2.6 2.7 2.8 3 3.1 3.2 3.3 3.4 3.5 3.6 4 4.1 4.2 4.3 4.4 5 5.1 5.2 5.3 5.4 5.5 5.6 6 7 8
POWERNET 42V STANDARD ....................................................................................................................................22 POWER MOSFETS ..................................................................................................................................................25 POTENTIAL CONCERNS ............................................................................................................................................28 Filtering .............................................................................................................................................................28 Electromagnetic Interference (EMI) ..................................................................................................................32 EFFICIENCY .............................................................................................................................................................35 CONTROLS THEORY.................................................................................................................................................39 TEST MEASUREMENT METHODOLOGY ....................................................................................................................41 SIGMA DELTA MODULATION...................................................................................................................................43 POWER STAGE .........................................................................................................................................................48 SYSTEM STABILITY .................................................................................................................................................50 FILTER .....................................................................................................................................................................53 HEAT SINK ...............................................................................................................................................................57 PRINTED CIRCUIT BOARD ........................................................................................................................................59 FIRST PCB...............................................................................................................................................................62 SECOND PCB...........................................................................................................................................................63 THIRD PCB..............................................................................................................................................................65 FOURTH PCB...........................................................................................................................................................67 EFFICIENCY TESTING ...............................................................................................................................................68 DEAD-ZONE.........................................................................................................................................................71 ACOUSTIC CLARITY.................................................................................................................................................75 OUTPUT POWER.......................................................................................................................................................76 SIGNAL TO NOISE RATIO .........................................................................................................................................78 EFFICIENCY LOSS ....................................................................................................................................................80
DESIGN .......................................................................................................................................................................... 43
PROJECT EVOLUTION.............................................................................................................................................. 62
APPENDIX .............................................................................................................................................................................. 92
Table of Figures
Figure 1: Class-D explanation without modulation or brightness reduction ............................................ 10 Figure 2: Class-D explanation with resistor added to reduce brightness.................................................. 11 Figure 3: Switch Open .............................................................................................................................. 11 Figure 4: Switch Closed............................................................................................................................ 11 Figure 5: Input Sine Wave vs. PWM Output............................................................................................ 13 Figure 6: Two-Level vs. Three-Level PWM ............................................................................................ 14 Figure 7: PWM Comparator ..................................................................................................................... 15 Figure 8: Delta Modulation and Demodulation ........................................................................................ 16 Figure 9: Block Diagram of Sigma-Delta (-) Modulation ................................................................... 17 Figure 10: DSP Block Diagram ................................................................................................................ 19 Figure 11: Biphase-Mark-Code Example ................................................................................................. 21 Figure 12: Maximum Over-voltage .......................................................................................................... 23 Figure 13: Maximum Dynamic Voltage ................................................................................................... 24 Figure 14: Starting Voltage....................................................................................................................... 25 Figure 15: H-Bridge.................................................................................................................................. 27 Figure 16: Typical Low-Pass Filter .......................................................................................................... 29 Figure 17: H-Bridge Output Low-Pass Filter ........................................................................................... 30 Figure 18: Bode Plot for 1 Ohm Load ...................................................................................................... 30 Figure 19: Bode Plot for 2 Ohm Load ...................................................................................................... 31 Figure 20: Bode Plot for 4 Ohm Load ...................................................................................................... 31 Figure 21: Bode Plot for 8 Ohm Load ...................................................................................................... 31 Figure 22: Braided Speaker Wire Example .............................................................................................. 33 Figure 23: EMI Interference ..................................................................................................................... 33 Figure 24: Basic level circuit model ......................................................................................................... 36 Figure 25: Current paths through the H-bridge......................................................................................... 37 Figure 26: MOSFET Switching Losses .................................................................................................... 38 Figure 27: Block Diagram ........................................................................................................................ 40 Figure 28: Duty Cycle............................................................................................................................... 41 Figure 29: Testing Diagram ...................................................................................................................... 41 Figure 30: Basic Sigma-Delta Modulation ............................................................................................... 43 Figure 31: Noise Spectrum ....................................................................................................................... 44 Figure 32: Three-Level Sigma-Delta Modulation .................................................................................... 44 Figure 33: Integrator ................................................................................................................................. 45 Figure 34: Quantizers................................................................................................................................ 47 Figure 35: Three-Level Switching ............................................................................................................ 47 Figure 36: Feedback Attenuation.............................................................................................................. 48 Figure 37: Three possible MOSFET configurations................................................................................. 49 Figure 38: Graphical Bode Plot Method................................................................................................... 52 Figure 39: Bode Plot ................................................................................................................................. 52 Figure 40: H-Bridge Filter Configuration................................................................................................. 54 Figure 41: H-Bridge Filter Half Representation ....................................................................................... 55 Figure 42: H-Bridge Filter Design Configuration .................................................................................... 56 Figure 43: H-Bridge Filter Configuration................................................................................................. 57 Figure 44: Heat sink used for testing ........................................................................................................ 58
Figure 45: Heat sink shown with supports................................................................................................ 58 Figure 46: Placement of MOSFETs for Heat Sink ................................................................................... 60 Figure 47: Two Separate Sections of Board Layout................................................................................. 61 Figure 48: Original PCB ........................................................................................................................... 63 Figure 49: Second PCB Ground Plane (Top) ........................................................................................... 65 Figure 50: Second PCB 42V Power Plane (Bottom) ................................................................................ 65 Figure 51: Third PCB Ground Plane (Top) .............................................................................................. 66 Figure 52: Third PCB 42V Power Plane (Bottom)................................................................................... 66 Figure 53: Third PCB Fully Populated ..................................................................................................... 67 Figure 54: Oscilloscope Snapshot............................................................................................................. 69 Figure 55: Efficiency vs. Clock Speed ..................................................................................................... 70 Figure 56: Ideal Integrator Output ............................................................................................................ 72 Figure 57: Vdz = 7.5mV (Too Small), f = 1kHz .................................................................................. 73 Figure 58: Vdz = 150mV (Too Large), 1kHz ....................................................................................... 74 Figure 59: Vdz = 150mV (Too Large), 10kHz ...................................................................................... 74 Figure 60: Vdz = 50mV (Near-Ideal Value), f = 1kHz ........................................................................... 75 Figure 61: Vdz = 50mV (Near-Ideal Value), f = 10kHz ......................................................................... 75 Figure 62: Speaker Test ............................................................................................................................ 76 Figure 63: Input vs. Output....................................................................................................................... 77 Figure 64: FFT used to obtain SNR.......................................................................................................... 79 Figure 65: Power Loss .............................................................................................................................. 81 Figure 66: Actual vs. Ideal 0.01uF Capacitor Impedance ........................................................................ 83 Figure 67: Power Loss vs. Dissipation Factor .......................................................................................... 84 Figure 68: Power Loss vs. Switching Frequency...................................................................................... 84 Figure 69: Efficiency vs. Switching Speed............................................................................................... 85 Figure 70: Efficiency vs. Clock Speed ..................................................................................................... 86
Executive Summary
Completing a project in the Analog Lab at WPI involves an enormous amount of growth, maturity and perseverance. The time invested and the struggles that we overcame left us with a sense of self-satisfaction and a broader knowledge that can be used in future endeavors. It is because of projects like this, that WPI is such a highly touted academic institution. The MQP was a wonderful hands-on experience that one can only achieve by participating in a project of this nature. This project, sponsored by Analog Device, Texas Instruments, and Allegro was to design a Class-D Audio Amplifier with an efficiency of at least 90%. For us, this project meant more than just exceeding the goals of previous MQP groups that have tackled similar projects. It meant exploring a larger scope of what could and will be done with Class-D design in the near future. Many topics were researched, such as how to implement the signal processing of the amplifier, which covered Pulse-Width Modulation, Sigma-Delta Modulation, and Digital Signal Processing. After an immense amount of research, Sigma-Delta Modulation was decided upon to carry out the signal processing due to various advantages it brought to the design. Also researched were electrical systems that would be incorporated into future automobiles that would ultimately revolutionize the design of Class-D amplifiers. Future luxury cars are predicted to consume 5,000 Watts of power requiring the evolution of the 42 Volt PowerNet Standard. This project would therefore be designed around the new standard allowing for greater power potential. These new concepts ultimately changed the goal of the project to design a Class-D amplifier capable of 95% efficiency. With such a small window for power loss, more research was spent investigating the leading causes of power loss in Class-D amplifiers. After an extensive study, we decided to implement a three-level modulation scheme that would allow for better efficiency than a twolevel design. We also discovered that the MOSFET selection and the filter components would be a critical choice in our amplifier design. The current that passes through the load passes through the MOSFETs and the inductors of the filter as well. This makes it extremely important to find components with a minimal DC on resistance to minimize voltage drops across these elements. In order to achieve a three-level modulation scheme, it was necessary to alter the typical scheme of Sigma-Delta Modulation. Instead of having one signal to control the output, there would be four signals controlling the output. These signals are the cornerstone for the three-level modulation. The reason that three-level was chosen over two-level was to maximize efficiency. The reason that it is able to do so is because with a three-level signal, you have the ability to control the load with either a 7
positive state, a negative state, or a neutral state. During the positive state, current is drawn through the load in one direction, during the negative state, current is drawn through the load in the opposite direction, and during the neutral state, current is not required to flow from the supply. Instead, both terminals across the load are grounded, causing any residual current to exit through the ground plane. The configuration that we used for the MOSFETs was a standard H-Bridge. This is the configuration used in most Class-D amplifiers on the market. To add more safety into the design, we used a driver chip to drive the MOSFETs. We did this because it had built in logic protection preventing a short from the power plane to ground. The driver chip could also drive the MOSFET gates with up to 1 Amp of current. This would allow the MOSFETs to turn on and off faster than without the use of a driver chip. These faster switching speeds would result in greater efficiency. After the MOSFET stage of our amplifier, the signal had to pass through one more block before it could reach the load. This last block was the filter. In our filter design, we used an inductor and a capacitor to create a low-pass filter. The low-pass filter was necessary to reduce the amount of electromagnetic interference that would radiate out of the amplifier without it. It was also necessary to transform the digital logic stream back into an analog signal that more closely represents the input signal. The filter was created with two separate cut-off frequencies at both 14 kHz and 37 kHz. The reasoning behind separating the poles was to maintain stability throughout the amplifier. When the design of the amplifier had taken shape and was ready to be tested, we ordered a printed circuit board to limit the inductive and capacitive effects found in typical breadboards. The design of the printed circuit board was done in a program called Ultiboard 2001. This program gave us the freedom to design the board in any matter that we saw fit. The end result was a professional looking populated printed circuit board that avoided the side effects of a breadboard. In the end, we were happy to report that the amplifier we designed and built was a success. The output power of the final product met its goal of being high powered with a measured output of 400 Watts RMS. The efficiency goal of the amplifier was also met reaching 95% efficiency with a fully clipped input signal. The total footprint size of the amplifier measured to be only 29 square inches. This produced a power to size ratio greater than many other amplifiers found on the market today. With the completion of our project, we like to think that we are paving the way for future designs of Class-D amplifiers utilizing the 42 Volt PowerNet Standard.
1 Introduction
Currently there are many Class-D amplifiers on the market for car audio applications. The conventional Class-D amplifier has several drawbacks: most have only 85% efficiency, they typically are used as subwoofer amplifiers, and are generally lower quality than conventional Class-A or ClassAB amplifiers. Imagine now, an amplifier with both the advantages of the Class-AB and Class-D amplifiers combined. This combination would provide an amplifier that is smaller in size with higher efficiency, very low distortion, and lower cost. The goal of this project is to create a Class-D, car-audio amplifier with an efficiency of at least 95%. The overall scheme of the project will be to foresee the future of car audio amplifiers assuming the adoption of the new 42 Volt PowerNet standard. The footprint size of the amplifier will be reduced dramatically due to the fact that the power supply of the amplifier will be eliminated from the design. This allows the amplifier to produce the same amount of power as other Class-D amplifiers with twice the footprint size. Similar to all Class-AB amplifiers, this amplifier will have a goal of running full audible bandwidth (20 to 20 kHz). Unlike present amplifiers on the market, this Class-D amplifier will not use Pulse-Width Modulation (PWM). Instead, Sigma-Delta Modulation will be used to drive the MOSFET switching stage by means of discrete components. The method of creating a Sigma-Delta modulated signal ensures a high level of efficiency which utilizes feedback to create a clean output signal.
2 Background
This section is included to provide the necessary background information and design concepts to build a Class-D amplifier. The topics include a brief overview of what Class-D really is and methods of creating a Class-D amplifier. The subsequent topics include relevant information on the PowerNet 42 Volt Standard, Power MOSFETs, Filtering, Efficiency, and Controls Theory.
it can be found that the power dissipated by the light bulb is 144 Watts.
Now if it was determined that this particular light bulb was running much brighter than intended, we would need to decrease the power that the light bulb dissipates. The simplest solution to fix this problem would be to implement a resistor in series with the light bulb. This would decrease the voltage across the light bulb, resulting in less current flow through it. For simplicity of explanation, well add a resistor to the circuit of the same resistance, 1. This can bee seen in Figure 2.
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Notice that now when we calculate the current, we see that the voltage across the light bulb has dropped from the full 12 Volts down to 6 Volts. What this means is that there is now only 6 Amps running through the bulb, which reduces the power the light bulb dissipates, and in effect, the brightness. Now this light bulb is emitting 36 Watts of power instead of the original 144 Watts which is what we wanted. The problem however is that the resistor is also consuming 36 Watts of power, which is being released in the form of heat, which is detrimental to achieving high efficiency. If only there was a way to decrease the power consumption of the light bulb to reduce the brightness while conserving energy at the same time. It turns out that adding a switch to the circuit instead of a resistor achieves this goal. Please take a look at Figure 3 & Figure 4 below.
Notice that when the switch is in the open position, there is no current flowing through the light bulb, resulting in the light bulb being off. However, when the switch is in the closed position the current is back to the original 12 Amps resulting in the light bulb being on again. In order for the light bulb to be dimmer than it was originally, but still remain on for the entire duration, the controlling switch would have to be switched very rapidly between off and on. If this happens, the bulb appears to remain on for the entire duration, illuminated at approximately half of its full capable brightness. Energy is
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conserved in this situation in the respect that a resistor is not absorbing half the power. Assuming the switch is lossless, an efficiency of 100% would be reached. If we calculate the power of these three circuits, we can see that in the first circuit we have 144 watts of power being dissipated by the light bulb. This is running at 100% efficiency, but we want the light bulb to be much dimmer. In the circuit we have the resistor and the light bulb which both dissipate 36 Watts of power. The 36 Watts of power dissipated by the resistor, in the form of heat, is actually wasted since it does not become dissipated by the light bulb. In this circuit we have 50% efficiency since the light bulb gets only 50% of the total power in the circuit. In the last circuit the light bulb averaged 72 watts of power due to the fact that it received 6 Volts across it on average, but at the full 12 Amps of current. In this circuit there is no wasted energy as there was in the resistor circuit, therefore there is no power loss due to non-bulb elements. Again we see the potential for 100% efficiency in this circuit while the bulb is running at 50% brightness, which was our goal. This example briefly explains and shows the relevance behind a Class-D amplifier. Even though the example has nothing to do with music or sound, it is intuitive that by implementing switching into a circuit, there are endless possibilities to what one may control. This leads into a few possible techniques to control the switching of various devices, comparing both advantages and disadvantages of each scheme.
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cycles vary according to the input signal. As an input signal approaches its upper limits, the duration of the pulses increase. The average of all the varying width pulses is equivalent to the original input. The Class-D amplifier utilizes an H-bridge to convert the PWM square-wave to an acoustic wave that ultimately drives the speakers at the output stage. Figure 5 depicts a PWM signal.
The red line in Figure 5 is the input sine wave that was needed to generate the PWM signal. Notice when the sinusoidal waveform reaches its peaks, the pulse width remains wider versus when the sinusoidal waveform approaches zero volts, the pulse widths get smaller. Class-D amplifiers typically use two-level rather than three-level PWM to control the switching of the H-bridge circuit. Two-level PWM contains two possible output levels, high and low. Three-level PWM contains three possible output levels, positive, negative, and zero. difference between the two PWM methods. Figure 6 illustrates the
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Three-level PWM is more beneficial because it increases the efficiency of the H-bridge circuit. To prove this, we must look at the input when it is zero volts. The two-levels duty cycle will be 50% because the MOSFETs will be switching on and off equally. The three-levels duty cycle will be zero because there is no need to draw current through the load. This conserves energy by minimizing MOSFET switching, increasing the efficiency. In todays standard Class-D amplifier, the PWM signal is created by a comparator. The
comparators job is simply to compare the audio signal to a reference signal, typically a triangle wave. When the audio signals amplitude is larger than the reference signals amplitude the resulting PWM signal is high. The longer the audio signals amplitude remains larger than the reference signals amplitude, the longer the PWM will remain high. In the case when the audio signal changes polarity, the terminals on the comparator circuit become switched. The analog input goes to the inverting terminal and the reference signal goes to the non-inverting terminal.
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To achieve a proper PWM signal that will represent an analog input, the reference signal amplitude must be larger than the maximum input amplitude. Another important factor of the reference signal is the operating frequency or clock speed of that waveform. The operating frequency must be faster than the audio signal to assure an accurate sampling rate.1 The faster the clock speed of the reference signal, the closer the output will represent the input. A drawback is more Electromagnetic Interference (EMI) will be radiated from the circuit which will be talked about later. The advantage of an extremely high clock speed, 1MHz and up, is full audible bandwidth capabilities of the amplifier, 20 to 20 kHz. As of 2003, the Xtant 1.1i was the only Class D amplifier on the market with this capability.2 For the purposes of this project, a comparator will not be used to create a square wave signal in the manner just discussed. A Sigma-Delta modulated signal (SDM) will be used as opposed to a PWM signal. The SDM will be created using discrete components that accept an analog input. The analog input will be a standard 1.4 Volt peak.
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Notice how the output of the integrator in the feedback loop of Figure 8(a) tries to predict the input x(t ) . This signifies that the integrator works as a predictor and the equation x(t ) x(t ) is the prediction error term. The prediction error term in each current prediction is quantized and is used in the subsequent prediction. The quantized prediction error (delta modulation output) is integrated in the receiver just as it is in the feedback loop. Finally, the predicted signal is smoothed out with a low-pass filter and produces the channel output.3 It is important to mention that delta modulators exhibit slope-overload for rapidly rising input signals. Slope-overload happens because the output takes a long time to catch up and follow the input. Thus, delta modulators performance is dependent on the frequency of the input signal. On the reverse end, granular noise can also be a problem when implanting SDM. Granular noise occurs when the step size is too large and causes excessive quantization noise when the input changes slowly. The step size is explained in much greater detail later in the report. 16
Integration, a linear operation, allows the two integrators in delta modulation to be combined into one without altering the input/output characteristics. Figure 9 shows the Sigma-Delta (-) Modulator.
Sigma-Delta Modulation is a smoothed out version of delta modulation, which is why it was chosen for this project. Both delta modulation and Sigma-Delta Modulation use a simple quantizer (comparator) but only in Sigma-Delta Modulation does this comparator encode the integral of the signal itself. The performance of this system is insensitive to the rate of change of the signal. Later in this report, these noise-shaping properties will be discussed in more detail and will show why Sigma-Delta Modulation is well suited to signal processing applications such as digital audio and communications.3 Sigma-Delta Modulation and Pulse-Width Modulation are similar and are applicable in the same topologies. Both SDM and PWM quantize the signal of interest directly. The product of the encoded waveforms when filtered can be represented in both cases by the ratio of the time the signal spends in the high position to the time it spends in the low position over a given time. The only difference is the time the two use to modulate the signal. The PWM signals are averaged over one switching cycle where 17
frequency is hidden and less harmonic energy is contained at lower frequencies.3 The frequency is hidden due to the MOSFETs not switching every cycle of the clock. With PWM, switching occurs at every instance of the reference signal. This results in a more spread out spectral density for SDM. When comparing these two methods, the fact that SDM has a more spread out spectral density really separates it apart from PWM. PWM uses only one switching cycle, which will have a tendency for its power spectrum to be concentrated about the switching frequency and its harmonics, which give rise to harmonic spikes. These spikes can produce many drawbacks for PWM with unwanted effects such as acoustic noise, torque ripple, and electromagnetic interference. One case where the drawbacks of SDM exceed those of PWM is at low modulation indices. With first order SDM, spectral spikes will degrade the performance unless a dither is added. Dither will help reduce the spikes and open the door for SDM.
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The main function of the DSP chip would be to process the audio input and create an equivalent square wave output to drive the H-bridge. The DSP chip would utilize the new S/PDIF input for signal processing and regulate both the output voltage level from fluctuating, due to the automobiles power consumption and excessive charging voltage, and minimize the level of total harmonic distortion in the final audio signal with analog feedback. More information about the benefits of feedback can be found in the Controls Theory section of this report. In the subsequent paragraphs, a deeper understanding of the S/PDIF input will be explored.
2.2.3.1 S/PDIF
Sony Philips Digital Interface (S\PSIF) format, also known as TOSlink, is a standard that is specified in the compact disc red book. The red book describes in detail the workings of digital audio transmission, storage and replay within a compact disc digital audio environment.4 S/PDIF is sent over coaxial cable, and TOSLink (Toshiba) is sent over fiber optic cable, but they are otherwise identical. Many audiophiles and industry professionals feel that the S/PDIF protocol allows for better sound quality than TOSlink.4 S/PDIF is used on DAT, Minidisc, and CD hardware.
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The S/PDIF (IEC-958) is a 'consumer' version of the AES/EBU-professional interface. Below is table that shows the differences between S/PDIF and AES/EBU.
There are two distinct parts that make up an S/PDIF signal: data protocol and hardware interface. The data protocol is universal across all S/PDIF devices. Sampling rates and resolutions between 16 and 24 bits can be supported as well as up to 4 channels. The hardware interface is what has already been mentioned and that is how to send S/PDIF data. The next table illustrates other important details about the Standard IEC958 "Digital audio interface" from EBU (European Broadcasting Union).
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Some key points in this table are the sampling frequencies and control information about the inputs. These are necessary points that allow signal processing to be carried out. The signal on the digital output of any device looks like an almost perfect sine-wave, with amplitude of 500 mVolts and a frequency of almost 3 MHz. Each sample contains two 32-bit words that are transmitted which result in a bit-rate of 2.8224 Mbit/s at a 44.1 kHz sampling rate for CD and DAT.5 The S/PDIF signal is coded using the 'biphase-mark-code' (BMC), which is a kind of phasemodulation. What this means is that if two zero-crossings exist, the signal records a logical 1 and if there is one zero-crossing, a logical 0 will be recorded. Figure 11 shows an example of BMC.
In the figure above, the clock frequency is twice the bit rate. It can be easily seen that each bit of the data signal is represented by two logical states for a cell. The length of a cell is knows as a time slot which is also equal to the length of a data bit. BMC uses two-level modulation where the logical level at the start of a bit is always inverted to the level at the end of the previous bit. This is as far as we got with S/PDIF as we chose to use an analog input to our Sigma-Delta Modulation .
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The transition to a 42 Volt standard from 12 Volt is something that will occur over time. Companies such as DaimlerChrysler and BMW are pioneering 14/42 Volt dual voltage systems. These
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cars will have the ability to power both 14 Volt and 42 Volt components using two separate circuits. Currently, components such as aftermarket car stereos and other mobile electronics are not ready for this jump. As the 42 Volt system becomes more prevalent, it can be assumed that companies producing devices such as car audio amplifiers will take advantage of this new system. One of the obvious reasons is the greater potential that the 42 Volt system allows over the 12 Volt system. A primary concern of the 42 Volt standard is limiting the maximum allowed voltage produced by the automobile. In the PowerNet, the generator must supply a voltage, UPN, of 42 Volt to the vehicles electrical system whereas the maximum static over-voltage is to be no more than 52 Volt including ripple due to load dump protection (LDP) 5%. This is shown in Figure 12.
The 48 Volt effective level was determined to be the power recharging voltage of the battery. Therefore, the peak static voltage is not to exceed 52 Volts given an 8 Volt (peak-to-peak) ripple riding on the effective voltage level. Perhaps the most important factors with regards to this project are the maximum and minimum dynamic voltages. The maximum dynamic voltage for the PowerNet is determined to be 58 Volts due to LDP. This is an important parameter when selecting semiconductors that see this unregulated power source. Each of the MOSFETs used in this project are able to withstand this voltage since their 23
breakdown limitation is at least 60 Volts. Figure 13 shows a test waveform of the maximum overshoot voltage.
Another issue that must be considered is the minimum start voltage of the system. The minimum voltage in the PowerNet standard measured at the battery terminals is never to drop below 18 Volts at any point and 21 Volts at startup. This is to provide full functionality of all loads which are relevant for startup and safety, including brakes and engine power management. For an audio amplifier application, it is not necessary for all circuits to be immediately operable. Often turn-on delay circuits are
implemented in order to minimize current draw to the amplifier at start-up. Figure 14 depicts what the voltage level may look like at the startup of the system; first dropping to its minimum value, then slowly increasing to a nominal 42/48 Volts.
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Many other factors such as slow decrease and increase of the power supply voltage have also been determined. This limitation is defined, No undesired functions shall appear when decreasing the operating voltage from max 42 Volts to 0 Volts and increasing it from 0 Volts to max 42 Volts.6
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spikes are common with automotive alternators, a MOSFET was chosen with no less than 60 Volts for a breakdown voltage. This helped narrow the search significantly. The next step was to enter all other important specifications from each chips datasheet onto a spreadsheet for comparison. Specifications that were decided upon were peak drain current (Id), onresistance (Rds), gate charge (Qg), power dissipation (W), rise time (tr), and fall time (tf). From these values it was possible to calculate many important factors such as max switching speed, conduction loss, energy loss due to switching, and power loss. Table 3 below shows the equations that were used to calculate these factors. Derivations for each equation can be found in Appendix A. Appendix A also shows comparison tables and charts that were used in determining which MOSFET to choose for the Hbridge of this amplifier.
1 = [ Hz ] + t fall
Conduction ( DC ) Loss = VRds * I d / 2 = [Watts ] 2 Rds C.L. = R Load + 2 Rds C.L. = Vds * 2 Rds
2
MaxSwitchingSpeed =
t rise
2(RLoad + 2 Rds )
Several values remain constant throughout the calculations. Switching will be at an absolute maximum frequency of 2 MHz however this is very unlikely. Understanding how Sigma-Delta
Modulation works, the MOSFETs are not going to switch at every clock pulse. It would be difficult to compute the actual speed at which the MOSFETs are switching using SDM. This sampling rate is used in high-end processors and can produce THD at or below 0.001% and a signal-to-noise ratio >110dB.7 Switching speeds are not a limiting factor since all MOSFET values considered were into the 5-10 MHz range. Also, it has been decided that a Vgs of 12 Volts will be a sufficient value based on manufacturers
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data in order to minimize DC on-resistance, Rds. All efficiency calculations have been considered at the predetermined load of 4. Conduction loss is the largest factor in determining efficiency for the operating frequency of 2 MHz. Based on calculated results, the Fairchild FDP038AN06A0 seems to be the best MOSFET due to its low Rds and conduction loss. As seen in Appendix A, this MOSFET dissipated a loss of 16.3 Watts/chip with an Rload of 1. Since the H-bridge configuration allows flow of current through two chips at a time we can find the total power loss in the MOSFETs by doubling this value.
Therefore, the ideal efficiency limited by the output MOSFETs will be 98.14% given by the following equation. Efficiency = Efficiency = PLoad PTotal 1718.1W = 98.14% 1750.6W
Further details about efficiency calculations are given in the Efficiency section of this report.
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2.5.1 Filtering
In the audio industry, the audible bandwidth range is considered to be 20 20 kHz. Because of this fact, all frequencies above 20 kHz will be filtered out. Filtering benefits this project in that it reduces the signal range that the speaker would have to play. Energy is wasted in trying to play frequencies higher than the human ear can hear and will result in a loss of energy in the form of heat. Additionally, EMI caused from high frequencies will be kept to a minimum. Without filtering, the Sigma-Delta Modulated signal would remain digital instead of converting back to analog. To ensure the goal of 95% efficiency, it was decided to use a passive filter. A passive filter is able to achieve higher efficiency because it theoretically gives back all the energy that it absorbs. For this project an inductor and capacitor will be used to construct the filter. To determine the values for the two components, the following formulas were used:8
= 2 *
2 2 1 1 = 0 2 RC 2RC
28
1 LC
From these equations, the capacitor value was calculated to be 1.4 F and the inductor value was calculated to be 45 H. These were based on a 4 load in a typical low-pass filter configuration as seen below in Figure 16. A 4 load was chosen because it matches the typical speaker impedance. This means that if 2 speakers are connected in series yielding an 8 load, the amplifier will be capable of playing up to 40 kHz rather than the cut-off frequency of 20 kHz. Conversely, a 2 load will only be able to play up to 10 kHz, and a 1 load will only be able to play up to 5 kHz. We chose this configuration because when trying to achieve high quality sound, the lower impedances generally lose their quality. This means that a 2 or 1 load should be reserved for subwoofer applications where the cut-off frequency is not as much of an issue. A typical subwoofer is reserved for very low frequencies less than 500 Hz.
L3 V3 1V 0.71V_rms 1000kHz 0Deg 45uH C3 1.4uF R2 4ohm
Because a MOSFET H-bridge configuration will be used to drive the speaker in this project, our typical low-pass filter setup had to be altered slightly. A basic schematic of the layout and the values for the components can be seen below in Figure 17. This may look like the typical low-pass filter, but notice that based on the filter described above, the load output is half, the input voltage is half, the inductor value is half, and the capacitor value is doubled. This is due to the fact that there will be two of
29
these filters in place at the H-bridge, for simplicity and ease of explanation, the model was done in this manner.
L1 V1 0.5V 0.35V_rms 1000kHz 0Deg 22.5uH C1 2.8uF R1 2ohm
To ensure that the design will perform in the manner that it was designed, simulations were in order.
30
31
The simulations show where the cut-off frequency will be for each speaker load configuration. The calculations were very close to the simulated results with the margin of error increasing as the impedance decreased. Notice that the last figure of the 8 load shows a frequency of approximately 20 kHz. This is due to the fact that there is a slight rise in the filter response before the cut-off. The rise is approximately 3db, and that is what is shown. The actual -3dB point is in fact 40 kHz.
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Another major concern is due to the high-frequency noise caused by the fast switching speeds of the MOSFETs. In a mobile environment, the Class-D amplifier can be detrimental to the operation of the vehicles central computer. A typical Class-D amplifier should be at least 3 feet away preventing the occurrence of interference. However, in this project, one of the goals is to create an amplifier that remains high powered, small in size, and also EMI shielded.
The high-frequency noise could also present a problem on the speaker lines. Even though it can not be heard in the speaker, there is always going to be residual high-frequency noise.10 Long speaker lines will act as an antenna to receive that high-frequency noise. This residual noise can also interfere with your radio reception. This interference is minor but it can also cause problems with the operation of the vehicles sensors. An example of this is in Toyota pickup trucks when the amplifier is mounted under the seat. The reason this is a problem is because the
33
vehicles central computer is also located there. This poses a problem because if the EMI affects the computer of the vehicle, it will affect the vehicles performance, and could create a safety concern. Also, the high-frequency noise carried through the line will be absorbed by the voice coil of the speaker. This noise is extra energy that the voice coil absorbs, causing it to not only heat up, but also waste energy in the process. To face these problems, EMI shielding must be implemented into the design of the amplifier. Currently, there is no shielding in Class-D amplifiers. The manufacturers warn consumers that the amplifier must be at least 3 feet from the cars central computer.10 In this project, the amplifier will be designed so that the user may place it wherever it is convenient without worrying about where the central computer is located. To do this, three methods have been considered. The first is a braided material that can be purchased that shields EMI very effectively. The tradeoff is that if the braided material is wrapped around several of the components such as the MOSFETs, the heat transfer from the component to the heat-sink would be compromised due to the nylon casing that surrounds the sheilding. This could solve the EMI problem without adding excessive cost to the amplifier, but lacks the thermal capabilities of heat dissipation to the heat sink. The second possibility is to design both a base and heat sink for the amplifier that is naturally EMI shielded. One example would be lead, which is great at shielding, but not as great at dissipating the heat like aluminum.11 Also, implementing lead as a heat sink and an effective EMI shield would greatly increase the weight of the entire amp which would not be good in a mobile environment. Another material to look at is steel. Steel is a compromise between both shielding and heat transfer but adds weight and does not fully shield against all frequencies and still does not dissipate heat as well as aluminum.12
34
A third method is to use perforated metals. Aluminum can still be used as the heat sink, but if we used perforated aluminum we can serve the purpose of both shielding and heat-sink. Tests have proven that a shielding effectiveness of 40dB provides 99.000% attenuation of EMI, and that a shielding effectiveness of 92dB provides 99.997% effectiveness.13 Our amplifier will meet or exceed the FCC regulation of 100 Volts/m at a distance of 3 meters; however the attenuation required for the amplifier in uncertain at this time. The perforated aluminum appears to be the most effective way to go, but the cost of implementing perforated aluminum has yet to be determined.
Shielding Possibilities
Material
Shielded Material Braiding
Advantage
1. In-expensive
Dis-Advantage
1. Difficult to work with. 2. Lacks heat transfer properties 1. Very heavy 2. Most metals either good at shielding or heat sink, not both. 1. Thicker heat-sink 2. Slightly more expensive
Active research continues on reducing interference by inspecting new arrangements for components to either reduce or completely eliminate the electromagnetic waves. This is certainly an area that must be fully explored but will be much easier once the design of the amplifier is complete.
2.6 Efficiency
The most limiting factor in achieving high-efficiency is in the final stage of any amplifier. The theoretical efficiency of a Class-D amplifier is 100%, but unfortunately it is also limited by non-ideal components. In addition, the increasing switching speed necessary to produce a clean audio output also
35
reduces this factor by a great deal. This section will attempt to describe the effects of discrete MOSFET shortcomings. In our amplifier, we chose to use a standard MOSFET H-bridge power stage. This allows us to apply both a positive and negative voltage to the load somewhat easily. Another alternative commonly used in an amplifier output stage is the push-pull BJT pair found in Class-AB amplifiers where the output stage consists of an NPN and a PNP transistor. As the input sweeps from VEE to VCC, the output passes through a dead zone of 1.4 Volts in which both transistors are off. This dead zone causes crossover distortion which can be avoided when using MOSFETS and either a Sigma-Delta or PulseWidth modulated signal. Figure 24 below shows a basic model of our circuit.
In Figure 24 there are four N-MOS devices. In an H-bridge configuration as the one depicted below, current may take one of two paths.
36
Sigma-Delta technology implies that the signal be switched from 0 Volts to either rail voltage rapidly enough to represent an analog signal. This means that for any given pulse, the output must change 42 Volts. The fact that MOSFETS are not ideal and contain capacitive and inductive properties limits the speed at which this switching occurs. In order to simulate the effects of such characteristics one would need to simulate the complex model of each MOSFET in a circuit. We have circumvented such testing due to time limitations and have found equations to give linear approximations of the output. These can be found further along in this section. There are in fact two sources of loss from switching a MOSFET. The first is due to changing the drain to source voltage limited by Cds and the second from changing the gate to source voltage by Cgs. For our purposes, a linear approximation of the power loss due to switching from both the drain to source and gate to source will suffice. Figure 26 gives an accurate representation of what we are trying to calculate.14
37
The new simplified equation uses common specifications given by manufacturers and therefore may be estimated before purchasing any of the MOSFETs. The equations used to find the power loss are listed in Table 5 and are explained in the Appendix.
SwitchingP owerLoss (Gate Source ) = Q g * V gs * f clk = [Watts ]
Conduction ( DC ) Loss = VRds * I d / 2 = [Watts ] 2 Rds C.L. = R Load + 2 Rds C.L. = Vds * 2 Rds
2
2(RLoad + 2 Rds )
From the calculations in the Power MOSFET section of this report, one can see that the efficiency of the Fairchild FDP038AN06A0 is adequate enough for us to achieve our goal of 95% efficiency. While other MOSFETs met or exceeded 95% efficiency at our test frequency of 192 kHz, this model was the most efficient. This has been made possible by a small Rds value and reasonably small Qg value. These two specifications are the most significant in gaining efficiency. As Rds or Qg increase, efficiency decreases proportionally. These specifications are also
inversely related which means that a When manufacturing a MOSFET a design consideration has to be made because it is not possible to decrease both Rds and Qg at the same time. Currently it is not
38
possible to decrease both factors at the same time. Perhaps a different fabrication process will some day minimize these limiting factors. However, since Rds is a much larger factor to consider, we chose the MOSFET with the least DC-on resistance. Semiconductor technology continues to advance every year. New ways of making faster, higherpower, and smaller devices are being discovered all the time.15 These minimize both the size and cost of the electronic devices. Next year there will be an even better selection of MOSFETs to implement and raise efficiency once again. The most important factors to look for when deciding on any switching device would be its DC-on resistance, unless switching speeds are in excess of 10 MHz. The advent of these new components shall push the limits of efficiency and give engineers the tools they need to make amplifiers switch faster and ultimately produce higher fidelity sound.
instability. If employed correctly, it may safeguard the overall output of the amplifier from variations in the rail voltages and unwanted energy produced by the signal processing. A simple block diagram of the system gives a better understanding of how the output can be used to correct these simple problems.
39
Analog Input
H-Bridge
Feedback
A main concern of this MQP is to maintain a certain level of total harmonic distortion (THD). Since the rail voltage of the H-bridge is entirely dependent on the automobiles PowerNet voltage, a wide range of values must be tolerated without alteration to the speaker output. This means that if a lower voltage is present, then the output may need to remain high for a longer period of time to reach an equivalent analog value. Conversely, if a higher rail voltage is present, the output will remain high for a shorter period of time. If done properly, the output should not deviate from the input apart from the gain. Figure 28 shows that as the rail voltage changes, the duty cycle must be changed to achieve a steady output. By using the average output voltage as a midpoint, relative voltage swings can be calculated and used to modify the duty cycle of the Sigma-Delta modulated signal. For instance, if the average voltage of a PowerNet system is 48 Volts and voltage drops to 44 Volts, the duty cycle must increase by 8.33%. DutyCycle = V f Vi Vi = 48 44 = 8.33% 48 Conversely, the duty cycle must be
40
This same technique serves a dual purpose. In addition to opposing the effects of rail voltage swings, some of the excess energy generated by the switching output can be negated. The control circuit must be fast enough, i.e. clock speed remains much higher than 20 kHz, in order for this theory to work. All other noise generated will be attenuated by the output low-pass filter. Theoretically, the output should be a clean representation of the input.
41
By measuring both the voltage and current at the power supply, the input power of the amplifier can be determined using the following formula: PIN = I V By finding the RMS voltage out of the amplifier, the output power of the amplifier can be determined using the following formula:
POUT =
V2 R
The theoretical
From the actual power of the amplifier, the efficiency can be calculated.
efficiency has already been determined in the MOSFET section of this paper. If the measured output is divided by the input power, this will yield the efficiency of the amplifier.
42
3 Design
The design of a Class-D car audio amplifier is a complex and faceted undertaking. The design stage of any project requires the most time and effort, and is also the most crucial to success. The design considerations we took into account for this project were signal processing, power output and amplification, filtering, thermal relief, and printed circuit board layout.
The open loop response of this system would look something like a pole at the integration constant and a -20dB/dec slope thereafter. This is due to its transfer function
H (s) =
1 s int
where int
is the integrator time constant. Ideally, noise would be introduced mostly at the switching frequency of the system but would be minimal at audible listening levels due to the inherent noise-shaping characteristic of Sigma-Delta.16 Figure 31 shows the normal (average) distribution of energy in the
43
harmonics of this noise. One can see the decline in magnitude within the audible band. All higher frequency noise is filtered out using a low-pass filter as described in the Filter section of this report.
In the design of our amplifier, we chose to modify the basic modulation scheme depicted in Figure 30. By adding a second 1-bit quantizer, or comparator, we were able to generate four separate gate signals to drive the four n-channel enhancement mode MOSFET devices in our H-bridge configuration separately. This control over all the MOSFETs simultaneously was crucial in creating a three-level output signal. The functionality of how the MOSFETs create these three states can be found in further detail in the Power Stage section of this report. This additional control would minimize power loss from drain to source switching, given the following equation:
17 1 PDS = Vin I o (t ON + t OFF ) f s = [Watts ] . 2
Discussion of this topic can be found in the Efficiency section of the report. This more advanced SigmaDelta Modulation scheme is shown in Figure 32.
44
The signal path can be described using Figure 32 above as a visual aide. First, (1), the signal arrives at the amplifier from the audio source as an analog waveform of either music or a test tone. Since Sigma-Delta Modulation requires a feedback loop in order to take the difference from input versus output, signal 7 is best described as a scaled down version of the output. Signal 2 is therefore the difference between the input and output waveforms. This may also be called the error. In order to keep track of this error, continuous integration takes place resulting in a sum of errors waveform at signal 3. Using two 1-bit quantizers, four quasi-digital streams, signal 4, are generated to control the gates of the H-bridge. The power stage of the amplifier receives these streams and is able to interpret them in such a manner to switch the four MOSFET devices. At location 5, the signal is very much still digital but greatly amplified to the level of +/- the rail voltage. After the amplified signal is filtered using a 2-pole Butterworth filter, the result is signal 6, an amplified version of the original analog signal. This loop is continued indefinitely. Now that the system has been described, each module involved can be delineated separately. Starting with the integrator, the schematic in Figure 33 shows the basic configuration.
The integrator portion of the signal processing loop shown above has three important tasks. The first is to take the difference between input and feedback. This is shown in the blue square marked Delta including a pair of resistors whose center is the output. Since the input and output are roughly the same but opposite in sign, one can expect this waveform to fluctuate closely around zero volts. While testing, we did not capture this waveform since the magnitude was essentially zero. The second task is to 45
compute the integral of the signal at its negative input terminal. The final duty required for the integrator to accomplish is the addition of a zero as illustrated in the next paragraph. As described in the Stability section of this report, it is necessary to implement both a pole and zero into the integration of the signal to achieve stability. The zero of the integrator was determined to be 20 kHz using a Miller integrator equation of f z = 1 . The pole of the integrator was determined 2Rz C
by using the same equation, however this time the resistor value used to determine the pole was taken from the negative feedback of the integrator. This yielded a pole at 7 kHz using the equation
fp =
1 .18 2R p C
The next stage of Sigma-Delta Modulation was to implement comparators as high and low 1-bit
quantizers. This was actually performed by using two comparators whose negative inputs saw either a voltage slightly higher or lower than zero. This voltage margin was called the dead-zone voltage due to the fact that any output of the integrator between zero and this level resulted in zero switching of the output. We found that the calculation of such a value is a trivial matter since, in testing, it was best to finely tune this margin using a plug-and-check method. The resistor value that yielded the least crossover distortion and optimal switching efficiency was 620. Using this ratio of resistors, the corresponding voltage for the dead-zone was computed to be VDZ = 15V *
need and application of a resistor divider network to accomplish this voltage margin can be read about in the Dead-Zone section of this report. As the sum of errors was compared to these near zero voltages, TTL logic level voltages are sent to a D-latch flip-flop which converts the two outputs to four quasidigital streams: Q1 , Q1 , Q 2 , and Q 2 . Figure 34 shows the resistive voltage divider, comparators, and
flip-flop.
46
If the Q1 and Q 2 waveforms are plotted on the same axis, this gives the illusion of three-level Sigma-Delta switching. While this waveform does not directly exist, the output of the H-bridge does follow the switching pattern seen in Figure 35. To further clarify, what appears to be switching either positive or negative is really a change in polarity at the load. However this three-level state is what the load thinks it is seeing, which is why we say that it does not directly exist.
47
Since the H-Bridge is described in a different section of this report, we can jump to the final division of designing the signal processing segment of the amplifier. The feedback attenuation block is simply an instrumentation amplifier, or In-amp, that has been calibrated to the specific gain of our amplifier.
We were able to determine the values of these resistors by using the low frequency gain of the system, A =
R1 19 . In our case, the amplification factor of the amplifier is about 30, so R2 must be 30 R2
times greater than R1. This completes the Sigma-Delta Modulation signal processing piece of our report and is now important to discuss the power output and final stage of the amplifier.
48
In order to achieve the three states shown above, we had to use all the resources available to us. This meant that we had to use all four outputs of the flip-flop to control the MOSFETs individually. To accomplish this goal, we used the output of the Q1 pin from the flip-flop to control the A-side High MOSFET, otherwise known as AH. This means that if the logic output sees a high, it triggers this MOSFET on. On the flip side, if the logic output sees a negative high, then we want the B-Side High MOSFET (BH) to be turned on. The way the flip-flop is configured, this corresponds to the Q 2 pin. These two states are what control the majority of the switching; however there are still two more connections to be made. When the AH MOSFET is on, the AL MOSFET must be off. In order to achieve this, the AL MOSFET was connected to the Q1 output pin of the flip-flop. This ensures that the AH MOSFET and the AL MOSFET will never be both on or off at the same time. The same type of configuration occurs on the B-Side. When the BH MOSFET is on, the BL MOSFET must be off to prevent a short to ground as well. This means the BL MOSFET must be connected to the Q 2 output pin of the flip-flop to ensure it is always opposite from the BH MOSFET. This leads us into a discussion of the final configuration of the MOSFETs, which we will call the zero state. For the time duration when neither the AH or the BH MOSFETs are on, we need a third state, zero. During this time, we turn both the AL and the BL MOSFETs on, grounding both sides of the speaker. Having this third state is what allows us to maximize efficiency because we are not wasting energy when not needed.
49
The output from our Sigma-Delta Modulation is what tells the MOSFETs when to turn off and on, but there is one other device that was not yet mentioned. Between the flip-flop and the MOSFETs is a driver chip. A driver chip was chosen for two reasons. The first reason is because it has built in logic protection to ensure that 42 Volts is never shorted to ground. The second reason is because the driver chip we chose can source up to 1 Amp of current per gate drive. What this means is that it will turn each of the MOSFETs off and on with more power, resulting in quicker turn-on and turn-off times. The actual schematic of the Power Stage can be found in the Appendix.
poles of the system to be found. Zeros are values for s that make Z(s) = 0 and the overall gain of the system zero. Poles are values that make P(s) = 0 and the overall gain infinite20. In addition, a zero produces a phase-shift of +90 while a pole produces a phase-shift of -90. 21 The low pass filter used in the power output stage of the amplifier plays a large role in maintaining stability. This filter is 2nd order, which means it has two cutoff frequencies. These frequencies are calculated in the Filter section of this report to be at 14 kHz and 40 kHz. Together these two poles (low-pass cutoffs) add an additional -90 of phase shift to frequencies above each of their cutoffs. If the open-loop gain at these frequencies approaching -180 phase shift is not less than 1, or 0dB, resonance may become a problem. This could be detrimental to any system taking negative feedback from the output because the resonance could oscillate indefinitely, causing the system to crash. Now, instead of the negative feedback being able to correct for any imperfection in the output as described in the Sigma-Delta section of the report, the noise is reinforced. It is preferable to have a phase at which gain is 0dB of 145or less.22 This is also called the phase margin, or difference between
50
0dB phase and -180. Later in this section it is shown that a phase margin of 35 is required for stability. The other source of poles and zeros comes from the Miller integrator used in Sigma-Delta processing. It was determined that our system could not tolerate any more poles without zeros, therefore an additional resistor was added in series with the capacitor of the integrator. Please reference the Sigma-Delta section of this report for this schematic and cutoff frequency calculation. The pole of the integrator was located at 7 kHz while the zero was introduced at 20 kHz. The location of the zero was chosen purposely close to the 14 kHz pole of the output low-pass filter. This zero would offset the phase shift and decrease the attenuation [in dB per decade] caused by the pole. The result of this action is such that neither pole nor zero have an overall effect on the system. The cancellation of pole and zero then allowed us to determine the frequency at which to make our integration pole while maintaining a phase margin greater than 35. This calculation was not a simple one to make. Therefore a graphical method was used to determine this value. First, we had to determine the DC gain of our system. Using the equation below, it was computed to be the following:
V A = 20 log OUT V IN
42V A = 20 log 6V
A = 16dB
We then decided to draw a Bode Plot of our system. The DC gain of our amplifier is 16dB and therefore can be regarded at the starting point of our Bode Plot. Figure 38 helps illustrate the graphical method we used in obtaining the integrator pole. By reducing the frequency of this pole location, the magnitude curve is shifted down and phase margin decreased. Conversely, increasing the frequency of the integrator pole shifts the magnitude curve up and phase margin increased. The value at which the resulting phase margin is 35 is 7 kHz and can be seen in Figure 38.
51
The final bode plot of the system can then be plotted. This can be seen in Figure 39.
From Figure 39 one can see that the system is stable. This is justified by the phase margin of about 35. In this amplifier, the output filter relies on a 4 load for stability. If the gain of the amplifier was increased or load changed to different impedance, the system may become unstable.
52
3.4 Filter
One of the most critical stages of our amplifier was our filter. Without it, a sinusoidal input would remain in the form of a three-level Sigma-Delta Modulated output. This signal would contain a great deal of unwanted high frequency content. This energy at frequencies up to the fastest response frequency of the driver chip may be potentially damaging to a speaker and would use any speaker wire as an antenna for radiating EMI. In order to solve this problem, a low-pass filter was introduced to the circuit to cutoff any frequencies higher than approximately 20 kHz. This is because the human ear can only hear from 20-20 kHz, so any frequencies higher than this would result in wasted energy that the speaker would try to play. Originally, we thought we could create a second order Butterworth filter with a double pole at 20 kHz. However, the filter got slightly more complicated when we introduced our Sigma-Delta circuit. The problem that arose was that we then had to be concerned with the stability of our system. The details on the stability of our system can be found in the Stability section of this report. From a design standpoint the only thing we needed to know was that the poles had to be separated, meaning that there could not be a double pole at 20 kHz. Again, the reasoning for this can be found in the Stability section of this report. Separating the poles of the filter turned out to be a much more difficult task than anticipated. Early in the project, we knew that inductors would have to be ordered. Originally, we thought that we would be able to run a 1 load, resulting in nearly 50 Amps of current to be drawn through the inductors. Because of the high current rating of the inductors required for our specifications, the inductors had to be custom made. This resulted in a fairly costly investment for our amplifier, so once we had the inductors in our possession, we could not afford to send away for new ones. This posed a bit of a problem for our design. In order to determine the cut-off frequencies for our filter, the two equations below were used. 1
f1 =
2 L C R f2 = 2 L
53
Notice that the inductor value is used to obtain both cut-off frequencies. This means that because we were stuck with our original inductor value of 22.5 H, we were limited in the range of cutoff frequencies we could obtain. Also, thinking ahead to the testing of our amplifier, we decided to stick with a fixed load resistance of 4. This meant that the cut-off frequency for f2 was predetermined.
f2 =
R 2 = = 14kHz 2 L 2 22.5H
Notice that the cut-off frequency is only 14 kHz. This is a design trade-off that we had to make in keeping our original inductor values. Although the first cut-off frequency is lower than 20 kHz, most people can only hear up to 16 kHz.23 By taking that into consideration, we decided as a group that it was one design decision we were willing to live with. The benefit of purchasing new inductors was not worth the small increase in cut-off frequency of the low-pass filter. Also notice that a resistance of 2 was used in the equation instead of 4. This is because in an H-bridge configuration, there are two separate filters, one for each half of the bridge. This can be seen in Figure 40 below.
When trying to design a filter for an H-Bridge configuration, the easiest way to approach the situation is to look at only half the bridge at a time. What this means is that it is necessary to divide the bridge in half. If that is done, you will notice that the inductor value and capacitor values remain the same. The only variable that changes is the resistive load, because half would belong to each side of the filter. Please refer to Figure 41. 54
The circuitry remains exactly the same, and you will notice that there is still a 4 load in place. However, when looking at the filter half representation, only 2 belongs to each filter, which is the reasoning behind the 2 being used in the f2 equation rather than the 4. After we accepted the first cut-off frequency to be 14 kHz, it was then time to set the second cutoff frequency. Notice that the inductor value is also included in this equation, but we do have the flexibility to change the capacitor value. Once again we already had purchased several 0.1 F capacitors, so we decided to use those as well. This was not as big of a concern because we had the ability to add as many 0.1 F as we wanted, giving us a range of overall capacitance. Knowing that our first cut-off frequency was 14 kHz, we decided to make the second cut-off frequency approximately 40 kHz. This would be well past the audible range, but still low enough in frequency to reduce EMI. Using the formula for f1, we were able to compute what capacitor value was desirable to yield a cut-off frequency of 40 kHz.
f1 =
1 2 L C
40kHz =
1 2 22.5H C
C = 0.7 F
Based on this formula, the capacitance value that should be used is 0.7 F. This would be easy to obtain from the 0.1 F capacitors that we already had by configuring 7 of them in parallel. Figure 42 shows how the filter may look from a schematic perspective.
55
One of the reasons that we decided to use multiple capacitors in parallel rather than one big capacitor was to reduce the equivalent series resistance, or ESR of the capacitors. The ESR is a calculated resistance at a particular frequency. As the frequency increases, the ESR decreases linearly. This was an important factor to take into consideration because at low frequencies, the ESR is relatively high, measuring at 1.6 for the capacitors we chose. However, AC current through this series resistance would be lower at low frequency since I = C
and will be talked about in further detail in the Efficiency Losses section of this report. Although the configuration shown in Figure 42 would have worked, this was not the layout that we chose for our filter. If you count the total number of capacitors in the circuit, you will find that 14 capacitors would be necessary in order to produce our filter. There is a way to reduce the total number of capacitors used that create the same filtering effects. The way to achieve that is to use some of the capacitors across the load instead. Please refer to Figure 43 for further clarification.
56
By placing some of the capacitors across the load, they essentially become twice as effective. This is because they contribute to both sides of the H-Bridge filter, rather than one side at a time. Notice that if the 4 capacitors across the load count for each side, then that yields an overall capacitance of 0.8F, not 0.7F. Well this is true. We decided that we wanted a symmetrical looking board, and in order to achieve that, three rows of 4 capacitors would have to be used. We decided that this was also a design tradeoff we were willing to accept because the difference between 0.7 F and 0.8 F resulted in a cut-off frequency of 40 kHz and 37 kHz respectively. Also notice that the total capacitor count was reduced from 14 to 12, while still increasing the effective capacitance. Had we not added the capacitors across the load, and still wanted 0.8 F of effective capacitance, then a capacitor count of 16 would have been necessary instead of the 12 we used in our filter design.
the testing of our amplifier in lab, we decided that 15 minutes of playing time would be more than sufficient to test the amplifier and obtain our results. It was decided to construct an adequate heat sink for our purposes of testing in lab, and to design another that would be used as both a housing and a heat sink if the amplifier was put into production. For testing purposes, two heat sinks were fabricated out of a solid piece of aluminum. The aluminum was donated to us by A & R Plastics Inc. as well as their machine shop for fabrication of our heat sinks. The design of the heat sinks presented some constraints. One constraint was how wide the heat sinks could be by the amount of space we had on our board between components. Our second constraint was the depth of the heat sink, which was limited by the depth of our board. We chose aluminum for the design of our heat sink because of its light weight and thermal properties. Secondly, in order to maximize the surface area of the heat sink to the ambient air, cooling fins were added to the design. Generally the more cooling fins that a heat sink has, the better job it will do at keeping the components cool. The heat sink was made larger than necessary, but in our situation it was best to over estimate the need for thermal protection. This yielded two identical heat sinks with overall dimensions of 2.25x 2x 1.375. An actual picture of the heat sink used for testing can be seen in Figure 44 below.
One of the problems that we encountered with such a large heat sink was the weight of the finished product. The heat sink could have been made smaller, but since the product was already finished, we thought it would be best to leave it alone. Because we had a machine shop at our disposal, we decided to drill and tap some supports into the fins of the heat sink. This would allow us to use 58
Teflon screws to support the weight of the excessively large heat sink. After it was mounted to the board, the idea worked out quite well. Figure 45 shows a heat sink mounted to the MOSFETs with supports in place to help reduce the load the MOSFETs would have to carry. Although it may not look as professional as it should, the idea worked, and so did the heat sinks. We were able to play music, which causes the most amount of switching, for approximately 15 minutes before the heat sinks started to get too hot. We were able to conduct all of our testing with the heat sinks shown. In the event that our amplifier is to be sold in todays market, the amplifier would have to be contained in a solid casing of some sort. This means that the heat sinks can not be two large objects attached to the MOSFETs. Instead, the MOSFETs would be placed at the very edge of the board, and the casing surrounding the amplifier would double as a heat sink. Fins would be incorporated into the design for what would hopefully be fan cooled. In addition to this casing being used as both a heat sink and an outer housing unit, it would also serve as an EMI shield which was discussed in the Background section of this report. The actual fabrication of this type of device was not made, however it is important to point out the need for a housing in the event of a continuing MQP or for marketing purposes.
Determining the fundamental shape of our board was one of the more elementary steps in laying out our design. While many forms and sizes may have worked, the most basic and industry standard shape is still the rectangle. Since our design followed a strict flow of information in one direction, an elongated rectangle certainly seemed the most reasonable model. This would allow for as much surface area as required by heat sinks as well as minimizing wasted space. The layout of the final board design was the next step to take place. As mentioned previously, the flow of our signal path was strictly unidirectional if feedback were ignored. Therefore we found it best to divide the PCB into sections, much like our circuit for both simplicity and practicality. One side of the board was clearly designated as the signal processing portion whereas the other was reserved for the power output section. These two divisions are distinct from one another in their requirements so were best left separate. On one hand, the signal-processing side is filled with mixed signals and hightransient voltage transmission lines. Adversely, the power output stage of the amplifier requires large ground planes, many wide current paths, and spacing between thermally dangerous components.
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Good engineering practices should always be used when designing a printed circuit board. There are several rules of thumb that we used. The first and foremost was to allow high transient voltages their own paths and ground planes while keeping them short. What this means is to avoid running other traces either over or under these paths in a multilevel board. Failing to do so will certainly affect signal integrity as each trace acts as a transmitter and receiver. This is due to the fact that the traces are capacitively and inductively coupled. The second rule that we used was relative to any high current paths. These traces should be kept as wide as possible to minimize the trace resistance, and wherever possible, power planes should be used. Any high current path that is too narrow will not have negligible resistance. In our design using a 4 load, we measured currents in excess of 10 Amps. From a power loss perspective even a 0.1 trace would burn up to 10W of power, or 2.5% of the total. This loss could greatly set back our efficiency goal. Another method of keeping these traces short was to place power, ground, and speaker connections on the power output side of the board. By following these layout rules, we believe that efficiency and signal integrity can be maximized.
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4 Project Evolution
In order for us to complete the project with a working amplifier, several board designs were used to achieve our goal. At first we started small, and eventually worked our way to a professional looking printed circuit board for the testing our amplifier. This section of the report will explain how the project evolved and how we ended at out final result.
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As you can see, we tried our best to keep the board layout as neat as possible to simplify troubleshooting. The huge coils that you can see at the top of the picture are our inductors used for the low-pass filter. When we started the board layout, the custom wound inductors were just being ordered, so we had no idea they would be so large. Because of this, they are hanging off the edge of the board, but through the use of banana connectors, we were able to make it work regardless. Another thing to point out is the large black block attached to the MOSFETs. This was a chunk of aluminum we cut to use as a heat sink. The aluminum served the purposes we needed it for, and also gave us some practice for the heat sinks that were created later in the project.
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even told us where we had flaws in our design. Every flaw that the program found in our design was minor enough that the board could be produced immediately. Most flaws were clearance issue such as a hole being too close to the edge of the board, but since the board size was not etched in stone, they just expanded the board for us where it needed it. To our surprise, the turnaround time was only a few days. We were expecting a turnaround time of a week or two. Also, another observation that we made was that whether you bought 1 board or 4 boards, the price remained the same. This is because setting up the equipment to create your board takes the most time, and after that, the material cost for the board itself and the solder used to coat it is insignificant. When our board arrived, we were very happy with our product. It was very impressive looking, but more importantly it was a very neat design with a lot of thought put into the board layout, and the product was paying off. However, the first draft if you will of our project did have a few flaws. Fortunately however, nothing was catastrophic to the forward progress of our project. The flaws that we found in our first board were as follows:
The ground pins of the BNC connectors were not connected to our ground plane The signal pin of the BNC connector was slightly too large for the hole that was drilled for it A keep out area on the power plane for the banana jacks used for speaker connections was forgotten Mounting holes to elevate the board of the ground were forgotten Many soldering pads were too small, making it very difficult to solder to A keep out area on the power plane was forgotten around the driver chip to make soldering easier The drill holes for the RJ45 jack were much too large, making the solder contact only on one side of each pin. A few of the diode and capacitor holes were slightly larger than necessary The power and ground pins for the voltage regulator were reversed, requiring surgery on our PCB Although most of the issues had to do with hole sizes, luckily in almost all cases, the holes were
larger than needed. Had the situation been reversed, we would have run into a much larger problem. Even where the BNC hole was too small, we were still able to make it fit after some TLC. Our first professional looking PCB can be seen in Figure 49 and Figure 50 below.
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For this board, the MOSFETs were separated by pairs on each half of the board. Because of this, a new heat sink had to be created. Unfortunately we do not have a picture of this board fully populated, but this did give us a chance to improve our fabrication skills. It was much easier to create this heat sink that it was for the first one because we now had some experience under our belt.
under the board, so that as you looked at the top of the board, you only saw 1 resistor at a 45 degree angle rather than 2 crossing resistors. This was the board that we used for all of our testing on the amplifier. The board itself can bee seen in Figure 51 and Figure 52.
The populated board that was used for testing can be seen in Figure 53 below. As you can see, a massive heat sink was created. We put a lot more time into this design because we knew that audio applications play at a wide range of frequencies, causing the MOSFETs to switch much more often that if they were playing a sine wave. The more switching that takes place, the hotter the MOSFETs will get. This is why the heat sinks are so much larger than the previous ones, and also have fins on them to provide more surface area to the ambient air, which increases the thermal properties of the heat sink.
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V2 Power = R
Since the BK Precision regulated power supply we were using gave a current reading as well as a voltage reading, we chose to use the P = IV equation for input power. We were somewhat limited by the accuracy of this device since it was accurate only to one-tenth of an ampere. On the other hand, we would be able to easily monitor the input voltage directly on the board using an HP 34401A multimeter accurate to six significant figures. The output power was measured using only one device at a time. For this task, we chose to use a Tektronix TDS 210 digital real-time oscilloscope. With this device we were able to capture snap-shots of the output waveform as shown in Figure 54.
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When connected to a computer, data could be uploaded into a spreadsheet to find the RMS, or root-mean squared, voltage. This was solved using the following equation.
Avg (VOUT ) =
V
n
OUTi
n
2
2 VRMS . R
temperature was apparently negligible because the load resistance measured to be the same at both ambient room temperature and at 140F. Finally, the ratio of input and output powers was solved for and recorded as the percentage efficiency of the amplifier.
Efficiency =
The efficiency in comparison to clock speed of the Sigma-Delta Modulation was our most critical measurement. This relation is essential in determining the sampling frequency at which yields
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the highest efficiency. By using a HP33120A to generate an array of clock waveforms we were able to graph the results at several frequencies ranging from 250 kHz to 4 MHz. Figure 55 below shows the results of these tests.
Efficiency is shown here under three different input conditions in addition to clock speed. The first condition uses an un-clipped sinusoidal input. This produces the least efficient case since the output never reaches the rails of the supply. Therefore switching occurs at each clock pulse in order to represent a median value. The second case was taken with a 40% clipped input signal. At this condition, little or no switching takes place nearly 40% of the time. While no switching is taking place, no error can be apparent with the output at the rail, thus the Sigma-Delta Modulation does not send a correcting signal. The final case utilized for these results uses a fully clipped input signal. For this case, the output is either high or low during each half cycle of input, switching is at a minimum. Nearly all switching loss is therefore avoided and maximum efficiency is obtained. This proves that we do in fact meet our expected 95% efficiency.
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There are other factors that affect efficiency. Since the 42 Volt PowerNet standard states that all vehicles should run at a charging voltage of 48 Volt, we decided to test our amplifier in that state. Using a fully clipped input signal we were able to achieve a maximum of 97.4% efficiency. The larger efficiency is due to the increase in voltage and was noted to be due to the standard specifications. Lastly, using the correct value for the dead-zone resistor is important when optimizing efficiency and will be explained in the following section of this report.
5.2 Dead-Zone
In order to achieve a clean output, the signal processing circuit must be properly calibrated. For a closer look at the components involved see the section on Sigma-Delta. One of the first items that must be taken into account is the dead-zone resistor, Rdz. It determines the voltage that each comparator sees on its negative input. Finding the ideal resistor value is a multilevel process beginning with the calculation of the integrator time constant, int. The following equations are given knowing the transfer function of a Miller integrator discussed in the Sigma-Delta section of this report.
Vripple = 0.05V
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Figure 56 shows the ideal integrator output and how given the correct VDZ there should be no overlap of MOSFET switching and minimal crossover distortion. Therefore the dead-zone voltage is half this total swing.
RDZ = 167.5
It is also important to mention how to calculate VDZ given a Vrail of 15V, RDZ, and R100k.
VDZ = Vrail
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However when implemented in the circuit, this did not give us the results that we were looking to achieve. The output of the tri-level sigma-delta modulation scheme should be two waveforms that should nearly overlap at low voltages to avoid crossover distortion and not result in clipping at the output. With a dead-zone that is too small, outputs of the flip-flop will be too active. This decreases the efficiency of the scheme greatly since it leads to the greatest amount of switching. On the other hand, a value too great would result in cross-over distortion.
Cross-over distortion is caused by too great a dead-zone voltage seen by the comparator negative input. This leads to a period when the outputs are both zero. The problem with crossover distortion is that this greatly affects performance at lower volume since the dead-zone is a large portion of a small input <100mV. This distortion can be seen in Figure 58 and Figure 59. When the input voltage is near zero, the filtered output looses its sinusoidal shape and flat-lines causing cross-over distortion for a small time duration.
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The theory behind the dead-zone voltage states that the noise in the output is regulated by the amount of crossover distortion. Since crossover distortion is clearly a result of an inaccurately tuned dead-zone, one can state that output noise is proportional to dead-zone voltage. Although we lacked the time to perform accurate signal-to-noise tests with several dead-zone voltages, listening tests were a second option. We can say that there was a distinct difference in noise level between each of the deadzones depicted above. Additionally, a signal processing scheme equipped with a larger dead-zone was susceptible to a greater percentage of noise at low input voltage levels. This is due to the fact that
V signal-to-noise ratio is calculated as 10 log SIGNAL .25 This noise would emphasize the need for a V NOISE
smaller dead-zone. The perfect dead-zone voltage was found by plugging and checking several resistor values in order to find where the crossover gap shrinks to zero and minimal overlap switching occurs. This voltage value was 50mV. Figure 60 and Figure 61 depict the ideal results given when using this value.
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The result of choosing the correct dead-zone voltage maximizes efficiency while providing satisfactory acoustic clarity. While minimizing crossover distortion is important, overlapping high and low switching signals could be detrimental to efficiency. of acoustic clarity. This would lead to overheating of the MOSFETs and ultimately cause the amplifier to run too hot. The following section continues discussion
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Although listening tests were satisfactory, there was a slight hiss in the output. To view the noise, we displayed an FFT of the output. This noise had a constant magnitude regardless of input signal, so it was determined to be internally generated. In order to maximize the signal-to-noise ratio, it was best to leave any CD player or other device at full volume. At low volume speech intelligibility was greatly degraded. According to our system design, noise should have been stopped from reaching the load. In one respect, any high-frequency (EMI) would be filtered by a two-pole Butterworth filter. On the other hand, anything below our sampling rate should also be compensated by the time it reached the output with negative feedback. There are a few culprits that have been identifies as candidates for the hissing noise at our speaker. The first are improperly calibrated resistor networks used as voltage dividers using 5% resistors. In practice it is best to use special resistor network packages calibrated to less than a percent. Secondly, Texas Instruments LF356 operational amplifiers were used in place of more expensive types. In a final board design these components would be swapped with more precise and faster slewing chips.
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different areas of the amplifier, we were able to capture an oscilloscope output of one of our tests. This output can be seen in Figure 63 below.
What you can see from the picture is an input sine wave at 5 Volts per division on the scope and an output sine wave at 25 Volts per division. What you cant see is that the test input signal was an 800 Hz sine wave with amplitude of 1.4 Volts. The output waveform was measured to have amplitude of 40 Volts. To determine the gain of our amplifier, you can simply divide the output power by the input power as shown. Gain = Output 40 = = 28.57 Input 1.4
As you can see, the gain of our amplifier is approximately 30. This gain factor can be decreased at our discretion by adjusting the feedback discussed in the Sigma-Delta section of this report. This gain of 30 that we obtained was determined using the specifications of a CD player maximum output value of 1.4 Volts. Because this was a maximum value, we wanted a signal of equal magnitude to have the ability of playing through our amplifier without clipping. As you may recall, the voltage rails that we are using are 42 Volt. Based on Figure 63, the output is only 2 Volts from reaching the rails of our amplifier, which would result in a clipped output. Other adjustments could have been made to achieve a
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greater gain if the input signal was attenuated, however we felt that the maximum value out of a portable CD player was adequate for our testing purposes. We also wanted to know how much power our amplifier was able to produce. To do this, we imported the data from the oscilloscope to our computer as mentioned in Efficiency section of this report. Using the same Microsoft Excel spreadsheet, we were able to compute the RMS power of our amplifier. To recap, the formula we used was: Power = V2 R
Using the same input of an 800 Hz sine wave of amplitude 1.4 Volts, we were able to measure a power output of 400 Watts RMS when 42 Volt supply rails were used. We were very pleased with the results, and met our goal of creating a high powered amplifier. Perhaps 400 Watts was slightly more power than necessary, but it granted us great satisfaction in knowing that the amplifier we produced is capable of competing with other amplifiers on the market.26 Referring to Figure 63 once again, notice that the output remains in phase with the input. This is important because in car audio applications, often times an amplifier is used to only power the front speakers in the automobile. If the output was out of phase with the input, then the result would be rear speakers that were playing out of phase with the front speakers, resulting in poor sound quality and noise cancellation.
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In order to compute the SNR, an FFT of the output must first be examined. For our amplifier, we used an 800 Hz sinusoidal input with amplitude of 1.4 Volts. We then examined the output, as seen in Figure 64 below.
Figure 64: FFT used to obtain SNR The oscilloscope that we used for testing was a Tektronix TDS-210. One of the features that made this scope easy to work with that it has an output that allowed us to import data into the computer. The data was imported into Microsoft Excel, where we were able to use the data to compute the power of both the signal and noise. To do this, we had to first separate the signal power from the noise power. That was done by observing the large magnitudes that occurred around 800 Hz where the spike was apparent. Everything else was considered to be noise in our system. With the signal and noise magnitudes separated, the total power in each was found. This was done by converting all of the data from decibels into watts of power. The equations below show the correlation between decibels and watts of power.
PWatts 10 12
PdB 10
10
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All of the signal and noise powers were then summed separately. Because the SNR is simply a ratio of the two powers, the SNR was easy to calculate at this point. With the information obtained from the FFT, we determined that our amplifier had a SNR of 43dB using the next equation.
SNRdB = 10 log
WSignal W Noise
Typically in the market, you will find amplifiers that range from 80dB 120dB for a SNR. Our amplifier is much less, and as a result there is an apparent hissing noise at the output. If more time were permitted, there are several things that could be done to try and increase the SNR, or possibly locate the noise in our system. Some of these suggestions are listed in the Recommendation section of this report.
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Conduction( DC ) Loss = VRds * I d / 2 = [Watts] 2 Rds C.L. = R Load + 2 Rds C.L. = Vds * 2 Rds
2
2(RLoad + 2 Rds )
These important specifications are therefore RDS and QG. This is discussed in the Background section on efficiency but is important to note that both RDS and QG should be minimized. These two factors greatly affect efficiency and follow the following power loss curve as shown in Figure 65.
Our decision to select the Fairchild FDP038AN06A0 PowerTrench MOSFET was based on finding the perfect match for our application. We needed a device with at least a 60 Volt break down voltage and a 50 Amp continuous current limit based on a 1 load. Since we found that with higher break down voltage, RDS increased, we chose a MOSFET with a break down voltage at our bare minimum of 60 Volts. Other decreases in efficiency are due to the filter components. Losses from either the capacitors or inductors can be calculated using several known equations given throughout this section. Methods by which these elements dissipate power are either conductively or in their AC characteristics. A primary concern in our filter design was the inductors. After calculating the appropriate values for these components, we needed to send our specifications to a custom winding company for 81
manufacture. Each inductor had to withstand the same amount of current as each MOSFET. Using a 1 resistive load, this current would peak to 50 Amps at 50 Volts. Therefore, above average gauge wire had to be used. The windings were made with 10 gauge wire and RDC of less than 20m. Now that all the conduction loss resistances are known, the total conduction loss can be calculated from the MOSFET, inductor, and load values.
Conduction( DC ) Loss = Vdrop * I d = [Watts] 2(RMOSFET + Rinductor ) Vrail Vrail * C.L. = R Load + 2(RMOSGET + Rinductor ) RLoad + 2(RMOSGET + Rinductor ) C.L. =
Some additional power loss is due to the capacitors. A perfect capacitor would be lossless and return each bit of energy it had stored. However, the ESR (Equivalent Series Resistance) rating of a capacitor is a particular evaluation of quality given to each series of manufactured devices. Ideally this value would be zero and therefore would have no AC resistance. In order to calculate the ESR for a given capacitor, one must start by finding its dissipation factor. In our case, we used capacitors with a dissipation factor of < 1% @ 20C at 1 kHz. Using a value of 1% and the following equations, we can solve for the ESR at a switching frequency of 192 kHz.
=
Xc =
ESR Xc
1 2Cf
ESR = ESR =
2Cf
.01 = 83m 2 (0.1uF )(192kHz ) Figure 66 shows the ideal and actual
ESR is not constant and changes greatly with frequency. impedance of a 0.01 F capacitor.
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Using the equations for current and ESR, the power dissipated in the capacitors can be found.
I =C dV dt
Figure 67 shows power loss versus dissipation factor. This is very helpful when determining how much loss is acceptable when selecting capacitors.
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Additionally, we have plotted the power loss versus switching frequency since we have a very dynamic range of switching frequencies that may be encountered during audio amplification. See Figure 69.
35
30
25
20
15
10
0 0 200,000 400,000 600,000 800,000 1,000,000 1,200,000 1,400,000 1,600,000 1,800,000 2,000,000 Switching Frequency [Hz]
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Theoretical calculations are extremely difficult for MOSFET switching, conduction, and filter losses in an amplifier that use Sigma-Delta Modulation. This is due to the fact that the actual number of switches per cycle of an input signal is not known. The amount of switching that occurs corresponds to the size of the dead zone. The dead-zone is described in its own section of this report. Also, input signal size has an affect on the efficiency. On one extreme, much too large an input will result in clipping and minimal switching. In this case, the MOSFET devices need only to switch twice per cycle. On the other hand, a small input signal creates the most uncertainty in the output and maximum amount of switching will occur. In this case or any in between, the number of switches per cycle is not known. In order to demonstrate this, we have plotted the ideal efficiency versus switching frequency in Figure 69 using the equations in Table 5.
The results are as predicted. The efficiency of a constantly switched output is very poor and decreases linearly due to the frequency that the MOSFETs switch. Conversely, if the input signal is large and the output is clipped, the efficiency remains at 99.8%. We decided to plot our actual efficiency results using three different input conditions on the same axis as the predicted results. The first case was an unclipped 800 Hz sine wave. The second signal
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was clipped 40% of the time. Finally, the last was a 100% clipped sine wave, or essentially a square wave. This is plotted in Figure 70.
By analyzing the two simultaneously, we can see that the theoretical efficiency is lower than that obtained. Clearly something is happening that prevents the measured efficiency from dropping below the theoretical efficiency. The fact that the output MOSFET switches are not being toggled during each clock tick like in some configurations is not shown here. The only real data that we can abstract is a difference of nearly 5% difference in efficiency between an ideally clipped and actually clipped output. This would suggest that much more loss is due to conduction than expected. In fact, this would explain the warming of the MOSFET switches at high current. If this 5% were to be explained by a direct series resistance, that value would be 221m solved for in the next few equations.
Efficiency =
Requiv = 221m
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Based on the fact that this amplifier was able to reproduce an unclipped sine wave at 92% efficiency, 32 Watts of power loss, would suggest a maximum number of 3.5 million switches per second or 1.75 MHz at theoretical conditions. These values can be found using Figure 68 The factors mentioned in this section have played a major part of determining the efficiency of our amplifier design. In summary, the lack of lossless capacitors, wires without resistance, and perfect MOSFET switches can not be avoided. Because we had a fairly large budget, we found the components that were most detrimental to our efficiency goals and purchased the best components we could find to reduce efficiency loss.
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6 Recommendations
Now that the project is completed, we recognize that there are some things that could have been done differently. There are areas for improvement in all stages of the design. This section will focus on ideas that could be implemented into the amplifier to improve upon the existing design. The first recommendation if this project is continued is that a DSP chip should be used to control the signal processing. There are several reasons for this. DSP technology has been a fiercely growing application in audio. Many home entertainment units and even car audio amplifiers now use this technology. The benefits are numerous as the possibilities of signal processing with DSP are nearly limitless. First, is that the signal to noise ratio would be much higher, resulting in a cleaner sounding output. The cleaner sounding output is made by the much higher switching speed of the amplifier. Therefore if quantization noise can be pushed into the megahertz band, filtering becomes simpler and noise in the audible band is negligible. Second, DSP processors are often equipped with multiple analog and digital inputs that may perform other tasks besides Sigma-Delta Modulation. With the use of a DSP chip, external controls could be implemented into the amplifier. For example a digital keypad could be part of the design where the user could control the volume, crossover, bass boost, or other added features into the amplifier. If DSP is not the method of choice, then there are other options as well. First, a higher ordered Sigma-delta modulator could be used. This means that the feedback taken from the load would go through several integrators instead of just one. This creates a cleaner output, but as you might expect adds a great deal of complexity to the circuit. One thing to note is that every integrator added to the circuit creates another pole. To balance this, an equal number of zeros must be added to keep the system stable. Second, potentiometers could be used instead of resistors from the input signal to control the volume of the amplifier or to add a high or low-pass crossover. Typically, Class-D amplifiers are not used for full-range audio applications, but if the application requires a small frequency bandwidth, there is no reason to make the amplifier do more work than it has to. Our amplifier was designed to reproduce the full audible bandwidth of 20-20 kHz. If this was not such a stringent requirement, a lower switching speed could be used to further push the efficiency limitations. Lastly, all the components in the amplifier were designed for a 50 Amps maximum current draw. By reducing the impedance of the load, the amplifier may be tested at these more extreme levels. 88
While the components in our amplifier were designed to be able to run at a 1 load, the system will become unstable. The reason for this is because the inductors that were purchased for the project were very costly, and in order to push the poles further from each other, a different inductor value would have to have been chosen. By redesigning the filter, it is possible to achieve a phase margin of greater than 45 at a 1 load. It is imperative that these inductors be similarly rated for 50 Amps of current. At the very least, a future MQP group could improve our current signal processing circuit in a few ways. The first and most immediate impact would be to compare several different operational amplifiers. While the LF356 model chip used in our circuit is widely accepted for many applications, there are new technologies that deserve to be explored. Many of these technologies boast low-voltage offset, less jitter, and higher slew rates. These op-amps would be more able to accurately reproduce high frequency noise which would allow for more noise to be filtered out. If information is lost in translation through these devices, the risk of noise slipping through is greatly increased. Lastly, many basic components used in the signal processing portion of the amplifier could be replaced with more finely tuned values. These include both resistor and capacitor values and ratings. Many parts were used because of their accessibility through the WPI ECE Shop with short notice. Capacitors were all special ordered but their values were determined by manufactures data sheets only. Larger bypass capacitors may reduce the noise due to instant current demands and they may also increase stability. Resistor packages are available that deviate less than 1% of the measured value and they could be used as input to the instrumentation amplifier or differential feedback attenuator. Additionally, instrumentation amplifiers are available that would replace the need for these resistor packages and op-amp. While many of these upgrades would cost significantly more money, their nonmonetary value may make them worthwhile.
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7 Conclusions
This project was deemed a success. An amplifier was designed, constructed, and tested that met all of the project goals. The first project goal to mention is the fact that amplifier is capable of reaching 95% efficiency. The goal was surpassed when the amplifier was tested under a 100% clipped input sine wave, at 800 Hz, using a 42 Volt supply. If you are skeptical about using a fully clipped input signal to achieve a maximum efficiency, we are pleased to announce that an efficiency of 92% was achieved using a purely sinusoidal input at 800 Hz once again with a 42 Volt supply. From the measurements taken of our amplifier, it was determined that a clock speed of 1.5 MHz would yield the highest efficiency. Another project goal was to design the amplifier around the 42 PowerNet Standard. With that said, the amplifier must also maintain a constant power throughout the fluctuations in voltage that will occur in a real-life car application. The amplifier was tested from 48 Volts all the way down to 30 Volts to observe the amplifier's response. The amplifier acted just as intended and the output power did not change more than 3 Watts over the swing in voltage. In the audio world, there is no point in making an amplifier unless the output is an amplified version of the input. Our amplifier was capable of driving a 4 speaker with a max power of 500 Watts and an RMS power of 400 Watts. At low volumes, the noise coming from the speaker was apparent but as the volume increased the noise became less and less noticeable. The noise is largely due to the tradeoff that is made with the "dead-zone" voltage. With a dead-zone voltage too high, acoustic clarity gets lost but efficiency goes up. For the opposite case, with a really small dead-zone voltage, acoustic clarity improves but the efficiency suffers. The dead-zone voltage that suited the amplifier's purposes the best was 50 mVolts. Lastly, it is believed that the amplifier that has been constructed could be marketable with a little more time. The amplifier currently has a footprint size of only 29 square inches, making the power to size ratio much higher than that of other amplifiers on the market. If more time was allowed to be spent on the design of an EMI shield that would double as a heat sink for the amplifier, the amplifier could be located anywhere in an automobile regardless of a vehicles central computer location. This would also make the amplifier very marketable.
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8 References
Beranek, Leo L. Acoustics. New York: Acoustical Society of America, 1996. Boylestad, L. Nashelsky. Electronic Devices and Circuit Theory. New Jersey: Prentice Hall, 1992 Haag, Michael. Understanding Pole/Zero Plots on the Z-Plane. July 2003, <http://cnx.rice.edu/content/m10556/latest/> Incropera & DeWitt. Introduction to Heat Transfer 4th ed. New York: John Wiley & Sons, Inc. 2002 Mohan, Ned. Power Electronics and Drives. Minnesota: MNPERE, 2003. Pohlmann, K.C. Principles of Digital Audio, 3rd ed. New York: McGraw-Hill, 1995. Robichaud, Jon. Interview. Heat Transfer & Metal Properties. Leominster, 23 Sept. 2003 Sedra & Smith. Microelectronic Circuits 4th ed. New York: Oxford University Press, 1998.
1 2
http://www.cpemma.co.uk/pwm.html www.xtant.com/html/products/xtant1.1i.cfm 3 http://www.numerix-dsp.com/appsnotes/APR8-sigma-delta.pdf 4 http://skyvision.com/pages/information_center/hdtvfaq.html#t7 5 http://www.epanorama.net/documents/audio/spdif.html 6 http://www.sci-worx.com/internet/bordnetzforum/bnvill.pdf 7 http://focus.ti.com/docs/prod/productfolder.jhtml?genericPartNumber=PCM1738 8 Class D Audio Amplifier, WPI MQP, 2003 9 http://www.web-ee.com/primers/files/DesignSem3.pdf 10 http://www.tripath.com/downloads/an11.pdf 11 Incropera & DeWitt , p53 12 Robichaud 13 http://www.diamondman.com/usesb3.htm 14 Mohan, p2-9 15 http://www.fairchildsemi.com/whats_new/30vauto_nph.html 16 Pohlmann, p154. 17 See Appendix on Efficiency Calculations 18 Sedra & Smith, p76. 19 Sedra & Smith, p89. 20 Haag, p1. 21 Haag, p2. 22 Ogata, Katsuhiko, Modern Control Engineering, Prentice Hall, 2002, p539. 23 Beranek, pg. 395. 24 www.4pcb.com 25 Beranek, pg 253. 26 Appendix Amplifier research 27 Boylestad, ch15. 28 http://newson-consulting.com/emi-capacitors.htm
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Appendix
Manufacturer Part # Vbrdss Rds Id (break (mOhm, at Vin Gate Charge (Qg) Pmax (Watts) (25degC) down) Vgs=10V) tON (nsec) tOFF (nsec) Max Switching Speed
Fairchild
Fairchild Fairchild IRF Fairchild Fairchild Fairchild Fairchild IRF IRF Fairchild IRF
FDP038AN06A0
FDP050AN06A0 HUF76443P3 IRFP064V FDP10AN06A0 HUF76445P3 FDP13AN06A0 FDP14AN06LA0 IRFP064 IRFP054 FQP50N06L IRFZ44E
60
60 60 60 60 60 60 60 60 60 60 60
80
80 75 130 75 75 62 61 70 70 52 48
3.8
5 8 5.5 10.5 6.5 13.5 11 9 14 21 23
10
10 10 10 10 10 10 10 10 10 10 10
95
61 107 173.3 28 124 22 24 126.7 106.7 24.5 40
310
245 260 250 135 310 115 125 300 230 121 110
163
264 195 226 206 205 158 276 211 180 380 72
75
86 100 250 94 295 74 109 300 233 145 140
4.20E+06
2.86E+06 3.39E+06 2.10E+06 3.33E+06 2.00E+06 4.31E+06 2.60E+06 1.96E+06 2.42E+06 1.90E+06 4.72E+06
MOSFET Specifications
G-S Switching Loss (Watts, Vin=10V, fclk=192kHz) 1Ohm 2Ohm 4Ohm 8Ohm D-S Switching D-S Switching D-S Switching D-S Switching Conduction Loss (Watts, Conduction Loss (Watts, Conduction Loss (Watts, Conduction Loss (Watts, Efficiency Efficiency Efficiency Efficiency Loss Vin=10V,fclk=1 Loss Vin=10V,fclk=1 Loss Vin=10V,fclk=1 Loss Vin=10V,fclk=1 92kHz) 92kHz) 92kHz) 92kHz)
Manufacturer
Part #
Fairchild
Fairchild Fairchild IRF Fairchild Fairchild Fairchild Fairchild IRF IRF Fairchild IRF
FDP038AN06A0
FDP050AN06A0 HUF76443P3 IRFP064V FDP10AN06A0 HUF76445P3 FDP13AN06A0 FDP14AN06LA0 IRFP064 IRFP054 FQP50N06L IRFZ44E
0.182
0.117 0.205 0.333 0.054 0.238 0.042 0.046 0.243 0.205 0.047 0.077
6.60
8.65 13.67 9.49 17.77 11.17 22.58 18.58 15.32 23.37 34.12 37.08
9.52
13.97 11.71 18.98 11.85 19.90 9.11 15.19 20.24 16.20 20.31 8.17
98.14%
97.40% 97.05% 96.70% 96.57% 96.40% 96.31% 96.08% 95.87% 95.36% 93.56% 94.62%
1.66
2.18 3.47 2.40 4.53 2.83 5.80 4.75 3.90 6.00 8.88 9.69
4.78
7.02 5.90 9.54 5.99 10.01 4.61 7.68 10.21 8.21 10.37 4.18
98.49%
97.88% 97.81% 97.20% 97.58% 97.01% 97.60% 97.14% 96.72% 96.68% 95.53% 96.76%
0.42
0.55 0.87 0.60 1.15 0.71 1.47 1.20 0.98 1.52 2.27 2.48
2.39
3.52 2.96 4.78 3.01 5.02 2.32 3.86 5.13 4.13 5.24 2.11
98.64%
98.10% 98.16% 97.40% 98.08% 97.28% 98.25% 97.67% 97.11% 97.32% 96.54% 97.86%
0.10
0.14 0.22 0.15 0.29 0.18 0.37 0.30 0.25 0.38 0.57 0.63
1.20
1.76 1.48 2.40 1.51 2.52 1.17 1.94 2.57 2.07 2.63 1.06
98.65%
98.17% 98.27% 97.38% 98.32% 97.34% 98.56% 97.92% 97.22% 97.58% 97.03% 98.39%
92
93
2(RLoad + 2 Rds )
a) Maximum Switching Speed [Hz] the fastest a device can switch on and off based on its rise time and fall time. Since Hertz is simply the reciprocal of time in seconds, we can calculate the maximum switching speed by adding the rise and fall times and dividing 1 by this number. b) Conduction Loss (DC) [Watts] power loss due to current flowing from the drain to source of a MOSFET device. This equation assumes DC current or current that is steady. In order to calculate DC loss, we can begin with the equation P=I*V where V is the rail voltage and current is the drain-source current. Since we are only concerned with one of the MOSFETS, we can divide by 2. The voltage across each MOSFET is given by the ratio of its resistance relative to 2 Rds the resistance of the load, . The drain-source current is then the ratio of the rail RLoad + 2 Rds Vds . The simplified voltage over the total resistance of the MOSFETs and the load, RLoad + 2 Rds conduction loss equation can be found in the table above. c) Switching Power Loss (Gate-Source) power loss due to the charging of the gate-source capacitance of the system in order to reach the gate-source voltage. This can be found by multiplying the gate charge (Qg), gate-source voltage (Vgs), and switching speed (fclk). d) Switching Power Loss (Drain-Source) power loss due to the charging of the drain-source capacitance of the system in order to reach the drain-source voltage. Equation was taken from Power Electronics and Drives, p2-9
94
2500
2000
125
175
200
225
250
Class - D Car Audio Amplifier Dimensions Max Total Power (RMS Watts) Alpine MRD-M100 700 Alpine MRD-M500 400 Alpine MRD-M300 200 ArcAudio 1500D-XXK 1000 ArcAudio 1500D-R 1000 Audiobahn A18001DT 1800 Audiobahn A12001DT 1200 Audiobahn A8001DT 800 Autotek MX2000 1200 Autotek MX5000 2200 Boss R1400D 800 Boss R2200D 1400 Boss R3000D 2200 Crossfire VR-300D 300 Crossfire VR-600D 600 Crossfire VR-1000D 1000 Crossfire VR-2000D 2000 Eclipse DA7122 1000 Eclipse DA7232 2000 Kenwood KAC-X810D 800 Kicker SX1250.1 1250 Kicker SX650.1 650 Kicker KX1200.1 1200 Kicker KX600.1 600 Kicker KX400.1 400 MA Audio HK-2000D 1500 MA Audio HK-4000D 3600 MA Audio SY7011DX 1500 MA Audio SY5011DX 1000 MA Audio H2KTP 2000 Memphis MC250D 250 Memphis MC500D 500 Memphis MC100D 1100 Memphis MC1500D 1500 Memphis MC2000D 2400 MTX Thunder251D 160 MTX Thunder311D 200 MTX Thunder421D 300 MTX Thunder801D 500 MTX Thunder1501D 1000 Orion 2500D 2500 Orion 1200D 1200 Orion 600D 600 Phoenix Gold R15.0:1 1000 Phoenix Gold R8.0:1 600 Phoenix Gold R30.0:1 2000 Rockford Fosgate Power 1001bd 1000 Rockford Fosgate Power 5001bd 500 Rockford Fosgate Power 1501bd 1500 Sony XM-D1000P5 900 Sony XM-D400PS 400 Soundstream EGA900D 900 Soundstream EGA1400D 1400 Soundstream EGA1700D 1700 U.S. Acoustics USX600D 375 U.S. Acoustics USX800D 600 U.S. Acoustics USX1000D 1250 Xtant X1001 1000 Xtant 1.1i 100 Zapco C2K-9.0XD 2200 Our Amp 400 Company Model Height (in) 2.6772 2.6772 2.6772 2.3500 2.3500 2.5000 2.5000 2.5000 2.6575 2.6575 2.2500 2.2500 2.2500 2.1000 2.1000 2.1000 2.1000 2.0500 2.0500 2.3125 2.5000 2.5000 2.5000 2.5000 2.5000 2.7100 2.7100 2.5600 2.5600 2.6800 2.0000 2.0000 2.0000 2.0000 2.2500 2.1000 2.1000 2.1000 2.1000 2.1000 2.3000 2.3000 2.3000 2.2500 2.2500 2.2500 2.3800 2.3800 2.3800 2.2500 2.2500 2.2000 2.2000 2.2000 2.3900 2.3900 2.3900 2.1875 1.6300 2.3750 Width (in) 21.6535 12.4016 8.2677 8.0000 8.0000 11.9375 11.9375 11.9375 8.5039 8.5039 11.7500 11.7500 11.7500 9.3000 9.3000 9.3000 9.3000 11.8500 11.8500 11.3333 10.0000 10.0000 10.0000 10.0000 10.0000 12.4000 12.4000 11.6000 11.6000 8.6000 6.5000 6.5000 6.5000 6.5000 9.1250 9.7500 9.7500 9.7500 9.7500 9.7500 10.5000 10.5000 10.5000 10.8750 10.8750 10.8750 9.8500 9.8500 9.8500 13.7500 11.5000 11.0000 11.0000 11.0000 9.5000 9.5000 9.5000 10.3125 5.8100 8.7500 Length (in) 9.7244 9.7244 9.7244 15.2500 15.2500 16.6875 14.5000 13.1250 13.4252 21.6535 11.4375 14.1875 15.3750 9.5000 11.5000 14.0000 22.0000 15.7500 21.0000 13.7500 17.0000 11.0000 17.5000 11.0000 7.7500 14.2900 25.8600 16.7300 15.9000 16.1000 8.2500 10.4000 13.4000 19.0000 22.5000 8.0000 8.0000 9.4000 11.5000 17.8000 27.2000 18.7000 16.4000 16.5000 14.7500 19.7500 13.0700 13.0700 17.0700 13.3750 11.6250 12.6000 15.0000 17.7000 5.7500 10.2500 15.7500 20.6875 6.5000 19.5000 Area (LxW) 210.5673 120.5981 80.3984 122.0000 122.0000 199.2070 173.0938 156.6797 114.1666 184.1392 134.3906 166.7031 180.6563 88.3500 106.9500 130.2000 204.6000 186.6375 248.8500 155.8329 170.0000 110.0000 175.0000 110.0000 77.5000 177.1960 320.6640 194.0680 184.4400 138.4600 53.6250 67.6000 87.1000 123.5000 205.3125 78.0000 78.0000 91.6500 112.1250 173.5500 285.6000 196.3500 172.2000 179.4375 160.4063 214.7813 128.7395 128.7395 168.1395 183.9063 133.6875 138.6000 165.0000 194.7000 54.6250 97.3750 149.6250 213.3398 37.7650 170.6250 29.0000 THD S/N Ratio (%) (dB) 1.000 90 1.000 90 1.000 90 0.055 98 0.055 98 0.050 100 0.050 100 0.050 100 90 90 100 100 100 0.080 90 0.080 90 0.080 90 0.080 90 0.007 120 0.007 120 0.200 100 1.500 98 1.500 98 1.500 95 1.500 95 1.500 95 1.000 96 0.500 96 1.000 96 1.000 96 0.200 98 0.500 80 0.500 80 0.750 80 0.750 80 0.500 90 1.000 100 1.000 100 1.000 100 1.000 100 2.000 100
1.000 1.000 1.000 0.050 0.050 0.050 0.600 0.600 0.300 0.300 0.300 0.015 0.300 0.500 2.000 1.000 0.050
80 80 80 80 80 80 90 100 85
January 2001
2.0 Features
n n n n n Operates from single 5V supply Input current: 150 nA max. over temperature Offset current: 20 nA max. over temperature Differential input voltage range: 30V Power consumption: 135 mW at 15V
(Note 3) Strobing
DS005704-36
DS005704-37
Note: Do Not Ground Strobe Pin. Output is turned off when current is pulled from Strobe Pin.
DS005704-38
DS005704-39
DS005704
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LM111/LM211/LM311
DS005704-40
DS005704-41
*Absorbs inductive kickback of relay and protects IC from severe voltage transients on V++ line. Note: Do Not Ground Strobe Pin.
DS005704-42
Note: Do Not Ground Strobe Pin. Note 2: Typical input current is 50 pA with inputs strobed off. Note 3: Pin connections shown on schematic diagram and typical applications are for H08 metal can package.
DS005704-24 DS005704-23
*Solid tantalum
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LM111/LM211/LM311
Operating Temperature Range LM111 55C to 125C LM211 25C to 85C Lead Temperature (Soldering, 10 sec) 260C Voltage at Strobe Pin V+5V Soldering Information Dual-In-Line Package Soldering (10 seconds) 260C Small Outline Package Vapor Phase (60 seconds) 215C Infrared (15 seconds) 220C See AN-450 Surface Mounting Methods and Their Effect on Product Reliability for other methods of soldering surface mount devices. ESD Rating (Note 11) 300V
Note 4: This rating applies for 15 supplies. The positive input voltage limit is 30V above the negative supply. The negative input voltage limit is equal to the negative supply voltage or 30V below the positive supply, whichever is less. Note 5: The maximum junction temperature of the LM111 is 150C, while that of the LM211 is 110C. For operating at elevated temperatures, devices in the H08 package must be derated based on a thermal resistance of 165C/W, junction to ambient, or 20C/W, junction to case. The thermal resistance of the dual-in-line package is 110C/W, junction to ambient. Note 6: These specifications apply for VS = 15V and Ground pin at ground, and 55CTA+125C, unless otherwise stated. With the LM211, however, all temperature specifications are limited to 25CTA+85C. The offset voltage, offset current and bias current specifications apply for any supply voltage from a single 5V supply up to 15V supplies. Note 7: The offset voltages and offset currents given are the maximum values required to drive the output within a volt of either supply with a 1 mA load. Thus, these parameters define an error band and take into account the worst-case effects of voltage gain and RS. Note 8: The response time specified (see definitions) is for a 100 mV input step with 5 mV overdrive. Note 9: This specification gives the range of current which must be drawn from the strobe pin to ensure the output is properly disabled. Do not short the strobe pin to ground; it should be current driven at 3 to 5 mA. Note 10: Refer to RETS111X for the LM111H, LM111J and LM111J-8 military specifications. Note 11: Human body model, 1.5 k in series with 100 pF.
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LM111/LM211/LM311
Operating Temperature Range 0 to 70C Storage Temperature Range 65C to 150C Lead Temperature (soldering, 10 sec) 260C Voltage at Strobe Pin V+5V Soldering Information Dual-In-Line Package Soldering (10 seconds) 260C Small Outline Package Vapor Phase (60 seconds) 215C Infrared (15 seconds) 220C See AN-450 Surface Mounting Methods and Their Effect on Product Reliability for other methods of soldering surface mount devices.
Note 12: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. Note 13: This rating applies for 15V supplies. The positive input voltage limit is 30V above the negative supply. The negative input voltage limit is equal to the negative supply voltage or 30V below the positive supply, whichever is less. Note 14: The maximum junction temperature of the LM311 is 110C. For operating at elevated temperature, devices in the H08 package must be derated based on a thermal resistance of 165C/W, junction to ambient, or 20C/W, junction to case. The thermal resistance of the dual-in-line package is 100C/W, junction to ambient. Note 15: These specifications apply for VS = 15V and Pin 1 at ground, and 0C < TA < +70C, unless otherwise specified. The offset voltage, offset current and bias current specifications apply for any supply voltage from a single 5V supply up to 15V supplies. Note 16: The offset voltages and offset currents given are the maximum values required to drive the output within a volt of either supply with 1 mA load. Thus, these parameters define an error band and take into account the worst-case effects of voltage gain and RS. Note 17: The response time specified (see definitions) is for a 100 mV input step with 5 mV overdrive. Note 18: This specification gives the range of current which must be drawn from the strobe pin to ensure the output is properly disabled. Do not short the strobe pin to ground; it should be current driven at 3 to 5 mA. Note 19: Human body model, 1.5 k in series with 100 pF.
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LM111/LM211/LM311
DS005704-43
DS005704-44
DS005704-46 DS005704-45
DS005704-47
DS005704-48
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LM111/LM211/LM311
(Continued)
DS005704-49
DS005704-50
DS005704-51
DS005704-52
DS005704-54
DS005704-53
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LM111/LM211/LM311
(Continued)
DS005704-55
DS005704-56
Leakage Currents
DS005704-57
DS005704-58
DS005704-59
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LM111/LM211/LM311
(Continued)
Input Characteristics
DS005704-60
DS005704-61
Transfer Function
DS005704-62
DS005704-63
DS005704-64
DS005704-65
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LM111/LM211/LM311
(Continued)
DS005704-66
DS005704-67
DS005704-69
DS005704-68
Supply Current
Supply Current
DS005704-70
DS005704-71
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LM111/LM211/LM311
(Continued)
DS005704-72
5.
6.
in oscillations that are very hard to damp. Twisting these input leads tightly is the only (second best) alternative to placing resistors close to the comparator. Since feedback to almost any pin of a comparator can result in oscillation, the printed-circuit layout should be engineered thoughtfully. Preferably there should be a groundplane under the LM111 circuitry, for example, one side of a double-layer circuit card. Ground foil (or, positive supply or negative supply foil) should extend between the output and the inputs, to act as a guard. The foil connections for the inputs should be as small and compact as possible, and should be essentially surrounded by ground foil on all sides, to guard against capacitive coupling from any high-level signals (such as the output). If pins 5 and 6 are not used, they should be shorted together. If they are connected to a trim-pot, the trim-pot should be located, at most, a few inches away from the LM111, and the 0.01 F capacitor should be installed. If this capacitor cannot be used, a shielding printed-circuit foil may be advisable between pins 6 and 7. The power supply bypass capacitors should be located within a couple inches of the LM111. (Some other comparators require the power-supply bypass to be located immediately adjacent to the comparator.) It is a standard procedure to use hysteresis (positive feedback) around a comparator, to prevent oscillation, and to avoid excessive noise on the output because the comparator is a good amplifier for its own noise. In the circuit of Figure 2, the feedback from the output to the positive input will cause about 3 mV of hysteresis. However, if RS is larger than 100, such as 50 k, it would not be reasonable to simply increase the value of the positive feedback resistor above 510 k. The circuit of Figure 3 could be used, but it is rather awkward. See the notes in paragraph 7 below.
LM111/LM211/LM311
(Continued)
When both inputs of the LM111 are connected to active signals, or if a high-impedance signal is driving the positive input of the LM111 so that positive feedback would be disruptive, the circuit of Figure 1 is ideal. The positive feedback is to pin 5 (one of the offset adjustment pins). It is sufficient to cause 1 to 2 mV hysteresis and sharp transitions with input triangle waves from a few Hz to hundreds of kHz. The positive-feedback signal across the 82 resistor swings 240 mV below the posi-
tive supply. This signal is centered around the nominal voltage at pin 5, so this feedback does not add to the VOS of the comparator. As much as 8 mV of VOS can be trimmed out, using the 5 k pot and 3 k resistor as shown. 8. These application notes apply specifically to the LM111, LM211, LM311, and LF111 families of comparators, and are applicable to all high-speed comparators in general, (with the exception that not all comparators have trim pins).
DS005704-29
Pin connections shown are for LM111H in the H08 hermetic package
DS005704-30
Pin connections shown are for LM111H in the H08 hermetic package
11
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LM111/LM211/LM311
(Continued)
DS005704-31
(Pin numbers refer to H08 package) 100 kHz Free Running Multivibrator
DS005704-13
DS005704-14
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12
LM111/LM211/LM311
DS005704-15
*Adjust for symmetrical square wave time when VIN = 5 mV Minimum capacitance 20 pF Maximum frequency 50 kHz
DS005704-17
DS005704-16
DS005704-18
*Values shown are for a 0 to 30V logic swing and a 15V threshold. May be added to control speed and reduce susceptibility to noise spikes.
13
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LM111/LM211/LM311
(Pin numbers refer to H08 package) (Continued) Comparator and Solenoid Driver
DS005704-20
DS005704-19
Precision Squarer
DS005704-21
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14
LM111/LM211/LM311
(Pin numbers refer to H08 package) (Continued) Low Voltage Adjustable Reference Supply
DS005704-22
*Solid tantalum
DS005704-24 DS005704-23
*Solid tantalum
DS005704-25
*Solid tantalum
15
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LM111/LM211/LM311
DS005704-26
*R2 sets the comparison level. At comparison, the photodiode has less than 5 mV across it, decreasing leakages by an order of magnitude.
DS005704-27
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16
LM111/LM211/LM311
DS005704-28
17
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LM111/LM211/LM311
(Note 20)
DS005704-5
Note 20: Pin connections shown on schematic diagram are for H08 package.
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18
LM111/LM211/LM311
DS005704-6
Top View Order Number LM111H, LM111H/883(Note 21) , LM211H or LM311H See NS Package Number H08C Dual-In-Line Package
Dual-In-Line Package
DS005704-34
Top View Order Number LM111J-8, LM111J-8/883(Note 21), LM311M, LM311MX or LM311N See NS Package Number J08A, M08A or N08E
DS005704-35
Top View Order Number LM111J/883(Note 21) See NS Package Number J14A or N14A
DS005704-33
Order Number LM111W/883(Note 21), LM111WG/883 See NS Package Number W10A, WG10A
Note 21: Also available per JM38510/10304
19
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LM111/LM211/LM311
Metal Can Package (H) Order Number LM111H, LM111H/883, LM211H or LM311H NS Package Number H08C
Cavity Dual-In-Line Package (J) Order Number LM111J-8, LM111J-8/883 NS Package Number J08A
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20
LM111/LM211/LM311
Dual-In-Line Package (M) Order Number LM311M, LM311MX NS Package Number M08A
21
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LM111/LM211/LM311
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22
Notes
LIFE SUPPORT POLICY NATIONALS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com www.national.com National Semiconductor Europe Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Franais Tel: +33 (0) 1 41 91 8790
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: ap.support@nsc.com
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
FDP038AN06A0 / FDI038AN06A0
August 2002
FDP038AN06A0 / FDI038AN06A0
N-Channel PowerTrench MOSFET 60V, 80A, 3.8m
Features
r DS(ON) = 3.5m (Typ.), V GS = 10V, ID = 80A Qg(tot) = 95nC (Typ.), VGS = 10V Low Miller Charge Low QRR Body Diode UIS Capability (Single Pulse and Repetitive Pulse) Qualified to AEC Q101
Formerly developmental type 82584
Applications
Motor / Body Load Control ABS Systems Powertrain Management Injection Systems DC-DC converters and Off-line UPS Distributed Power Architectures and VRMs Primary Switch for 12V and 24V systems
DRAIN (FLANGE)
G
DRAIN (FLANGE)
TO-220AB
FDP SERIES
TO-262AB
FDI SERIES
Ratings 60 20
Units V V
Thermal Characteristics
RJC RJA Thermal Resistance Junction to Case TO-220, TO-262 Thermal Resistance Junction to Ambient TO-220, TO-262 (Note 2) 0.48 62
o o
C/W C/W
This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. For a copy of the requirements, see AEC Q101 at: http://www.aecouncil.com/ Reliability data can be found at: http://www.fairchildsemi.com/products/discrete/reliability/index.html. All Fairchild Semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification.
FDP038AN06A0 / FDI038AN06A0
Off Characteristics
B VDSS IDSS IGSS Drain to Source Breakdown Voltage Zero Gate Voltage Drain Current Gate to Source Leakage Current ID = 250A, VGS = 0V VDS = 50V VGS = 0V VGS = 20V TC = 150oC 60 1 250 100 V A nA
On Characteristics
VGS(TH) Gate to Source Threshold Voltage VGS = VDS, ID = 250A ID = 80A, VGS = 10V rDS(ON) Drain to Source On Resistance ID = 40A, VGS = 6V ID = 80A, VGS = 10V, TJ = 175oC 2 4 V 0.0035 0.0038 0.0049 0.0074 0.0071 0.0078
Dynamic Characteristics
CISS COSS CRSS Qg(TOT) Qg(TH) Qgs Qgs2 Qgd Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge at 10V Threshold Gate Charge Gate to Source Gate Charge Gate Charge Threshold to Plateau Gate to Drain Miller Charge VDS = 25V, VGS = 0V, f = 1MHz VGS = 0V to 10V VGS = 0V to 2V VDD = 30V ID = 80A Ig = 1.0mA 6400 1123 367 95 12 30 18 24 124 15 pF pF pF nC nC nC nC nC
FDP038AN06A0 / FDI038AN06A0
0.8
150
0.6
100
0.4
0.2
50
0 25
50
75
100
125 (o C)
150
175
PDM 0.1 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC x RJC + TC 10-3 10-2 t, RECTANGULAR PULSE DURATION (s) 10-1 100 101
10 10-5 10-4 10-3 10-2 t, PULSE WIDTH (s) 10-1 100 101
FDP038AN06A0 / FDI038AN06A0
STARTING TJ = 150oC 10
10
10ms 1 SINGLE PULSE TJ = MAX RATED TC = 25o C 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V) DC
If R = 0 tAV = (L)(I AS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] 1 0.01 0.1 1 10 tAV, TIME IN AVALANCHE (ms) 100
0.1
100
160
PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = 15V ID, DRAIN CURRENT (A)
120
80
TJ = 175 oC
40
TJ = 25o C TJ = -55 C
o
TC = 25o C 1.5
0 3.0 3.5 4.0 4.5 5.0 5.5 VGS , GATE TO SOURCE VOLTAGE (V) 6
1.5
1.0
VGS = 10V, ID =80A 0.5 -80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC) 200
FDP038AN06A0 / FDI038AN06A0
1.0
1.1
0.8
0.6
1.0
0.4
0.2 -80 -40 0 40 80 120 160 200 TJ, JUNCTION TEMPERATURE (oC)
1000
CRSS = CGD
VGS = 0V, f = 1MHz 100 0.1 1 10 60 VDS , DRAIN TO SOURCE VOLTAGE (V)
FDP038AN06A0 / FDI038AN06A0
VGS = 10V
Qgs2
VDS
VGS
VDD DUT 0
10%
10%
90% 50%
FDP038AN06A0 / FDI038AN06A0
RSLC2
DBODY
FDP038AN06A0 / FDI038AN06A0
dp.dbody n7 n5 = model=dbodymod dp.dbreak n5 n11 = model=dbreakmod dp.dplcap n10 n5 = model=dplcapmod spe.ebreak n11 n7 n17 n18 = 69.3 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evthres n6 n21 n19 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 i.it n8 n17 = 1 l.lgate n1 n9 = 4.81e-9 l.ldrain n2 n5 = 1.0e-9 l.lsource n3 n7 = 4.63e-9 res.rlgate n1 n9 = 48.1 res.rldrain n2 n5 = 10 res.rlsource n3 n7 = 46.3
GATE 1
6 8
11 DBODY MWEAK
MMED
RLGATE
EBREAK + 17 18 -
LSOURCE 7 RLSOURCE
SOURCE 3
RSOURCE S1A 12 S1B CA 13 + EGS 6 8 EDS 13 8 S2A 14 13 S2B CB + 5 8 8 RVTHRES 14 IT VBAT + 22 15 17 RBREAK 18 RVTEMP 19
m.mmed n16 n6 n8 n8 = model=mmedmod, temp=m_temp, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, temp=m_temp, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, temp=m_temp, l=1u, w=1u res.rbreak n17 n18 = 1, tc1=9e-4,tc2=-9e-7 res.rdrain n50 n16 = 1e-4, tc1=4e-2,tc2=3e-4 res.rgate n9 n20 = 1.36 res.rslc1 n5 n51 = 1e-6, tc1=1e-3,tc2=1e-5 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 2.8e-3, tc1=5e-3,tc2=1e-6 res.rvthres n22 n8 = 1, tc1=-6.7e-3,tc2=-1.5e-5 res.rvtemp n18 n19 = 1, tc1=-2.5e-3,tc2=1e-6 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/250))** 10)) }
FDP038AN06A0 / FDI038AN06A0
RTHERM1
CTHERM1
RTHERM2
CTHERM2
RTHERM4
CTHERM4
RTHERM5
CTHERM5
RTHERM6
CTHERM6
tl
CASE
TRADEMARKS
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DISCLAIMER
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LIFE SUPPORT POLICY FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component is any component of a life 1. Life support devices or systems are devices or support device or system whose failure to perform can systems which, (a) are intended for surgical implant into be reasonably expected to cause the failure of the life the body, or (b) support or sustain life, or (c) whose support device or system, or to affect its safety or failure to perform when properly used in accordance with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design First Production Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.
Preliminary
No Identification Needed
Full Production
Obsolete
Not In Production
Rev. I1
HIP4081A
Data Sheet February 2003 FN3659.6
Features
Independently Drives 4 N-Channel FET in Half Bridge or Full Bridge Configurations Bootstrap Supply Max Voltage to 95VDC Drives 1000pF Load at 1MHz in Free Air at 50oC with Rise and Fall Times of Typically 10ns User-Programmable Dead Time On-Chip Charge-Pump and Bootstrap Upper Bias Supplies DIS (Disable) Overrides Input Control Input Logic Thresholds Compatible with 5V to 15V Logic Levels Very Low Power Consumption Undervoltage Protection
Applications
Medium/Large Voice Coil Motors Full Bridge Power Supplies Switching Power Amplifiers High Performance Motor Controls Noise Cancellation Systems
Ordering Information
PART NUMBER HIP4081AIP HIP4081AIB TEMP RANGE (oC) -40 to 85 -40 to 85 PACKAGE 20 Ld PDIP 20 Ld SOIC (W) PKG. NO. E20.3 M20.3
Pinout
HIP4081A (PDIP, SOIC) TOP VIEW
1 2 3 4 5 6 7 8 9
20 19 18 17 16 15 14 13 12 11
BHO BHS BLO BLS VDD VCC ALS ALO AHS AHO
AHB 10
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2003. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
12V BHO BHS BHI BLI HIP4081A ALI AHI ALO AHS AHO BLO LOAD
GND
GND
(1/2 HIP4081A)
AHB 10 HIGH VOLTAGE BUS 80VDC
UNDERVOLTAGE
CHARGE PUMP
DRIVER 11
ALO CBF
1 BHB HIP4081/HIP4081A 12V DIS PWM INPUT 2 BHI 3 DIS 4 VSS 5 BLI 6 ALI 7 AHI 8 HDEL 9 LDEL 10 AHB
BHO 20 BHS 19 BLO 18 BLS 17 VDD 16 VCC 15 ALS 14 ALO 13 AHS 12 AHO 11 12V LOAD
+ 6V
GND
HIP4081A
Absolute Maximum Ratings
Supply Voltage, VDD and VCC . . . . . . . . . . . . . . . . . . . . -0.3V to 16V Logic I/O Voltages . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD +0.3V Voltage on AHS, BHS . . . -6.0V (Transient) to 80V (25oC to 125oC) Voltage on AHS, BHS . . . -6.0V (Transient) to 70V (-55oC to 125oC) Voltage on ALS, BLS . . . . . . . -2.0V (Transient) to +2.0V (Transient) Voltage on AHB, BHB . . . . . . . . VAHS, BHS -0.3V to VAHS, BHS +VDD Voltage on ALO, BLO. . . . . . . . . . . . . .VALS, BLS -0.3V to VCC +0.3V Voltage on AHO, BHO . . . . . . . .VAHS, BHS -0.3V to VAHB, BHB +0.3V Input Current, HDEL and LDEL . . . . . . . . . . . . . . . . . . -5mA to 0mA Phase Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V/ns NOTE: All Voltages relative to VSS, unless otherwise specified.
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Storage Temperature Range. . . . . . . . . . . . . . . . . . . -65oC to 150oC Operating Max. Junction Temperature . . . . . . . . . . . . . . . . . . 125oC Lead Temperature (Soldering 10s)) . . . . . . . . . . . . . . . . . . . . 300oC (For SOIC - Lead Tips Only
Operating Conditions
Supply Voltage, VDD and VCC . . . . . . . . . . . . . . . . . . +9.5V to +15V Voltage on ALS, BLS . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +1.0V Voltage on AHB, BHB . . . . . . . . . VAHS, BHS +5V to VAHS, BHS +15V Input Current, HDEL and LDEL . . . . . . . . . . . . . . . .-500A to -50A Operating Ambient Temperature Range . . . . . . . . . . -40oC to 85oC
CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100K and TA = 25oC, Unless Otherwise Specified TJ = 25 C
o
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
SUPPLY CURRENTS AND CHARGE PUMPS VDD Quiescent Current VDD Operating Current VCC Quiescent Current VCC Operating Current AHB, BHB Quiescent Current Qpump Output Current AHB, BHB Operating Current AHS, BHS, AHB, BHB Leakage Current AHB-AHS, BHB-BHS Qpump Output Voltage IDD IDDO ICC ICCO IAHB, IBHB IAHBO, IBHBO IHLK VAHB-VAHS VBHB-VBHS All inputs = 0V Outputs switching f = 500kHz All Inputs = 0V, IALO = IBLO = 0 f = 500kHz, No Load All Inputs = 0V, IAHO = IBHO = 0 VDD = VCC = VAHB = VBHB = 10V f = 500kHz, No Load VBHS = VAHS = 80V, VAHB = VBHB = 93V IAHB = IAHB = 0, No Load 8.5 9.5 1 -50 0.6 11.5 10.5 12.5 0.1 1.25 -30 1.2 0.02 12.6 14.5 15.5 10 2.0 -11 1.5 1.0 14.0 7.5 8.5 0.8 -60 0.5 10.5 14.5 15.5 20 3 -10 1.9 10 14.5 mA mA A mA A mA A V
INPUT PINS: ALI, BLI, AHI, BHI, AND DIS Low Level Input Voltage High Level Input Voltage Input Voltage Hysteresis Low Level Input Current High Level Input Current IIL IIH VIN = 0V, Full Operating Conditions VIN = 5V, Full Operating Conditions VIL VIH Full Operating Conditions Full Operating Conditions 2.5 -130 -1 35 -100 1.0 -75 +1 2.7 -135 -10 0.8 -65 +10 V V mV A A
TURN-ON DELAY PINS: LDEL AND HDEL LDEL, HDEL Voltage VHDEL, VLDEL IHDEL = ILDEL = -100A 4.9 5.1 5.3 4.8 5.4 V
GATE DRIVER OUTPUT PINS: ALO, BLO, AHO, AND BHO Low Level Output Voltage High Level Output Voltage Peak Pullup Current VOL VCC-VOH IO + IOUT = 100mA IOUT = -100mA VOUT = 0V 0.7 0.8 1.7 0.85 0.95 2.6 1.0 1.1 3.8 0.5 0.5 1.4 1.1 1.2 4.1 V V A
HIP4081A
Electrical Specifications
VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100K and TA = 25oC, Unless Otherwise Specified (Continued) TJ = 25oC PARAMETER Peak Pulldown Current Undervoltage, Rising Threshold Undervoltage, Falling Threshold Undervoltage, Hysteresis SYMBOL IO UV+ UVHYS TEST CONDITIONS VO UT = 12V MIN 1.7 8.1 7.6 0.25 TYP 2.4 8.8 8.3 0.4 MAX 3.3 9.4 8.9 0.65 TJS = -40oC TO 125oC MIN 1.3 8.0 7.5 0.2 MAX 3.6 9.5 9.0 0.7 UNITS A V V V
Switching Specifications
VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 10K, CL = 1000pF. TJ = 25oC TJS = -40oC TO 125oC MAX 60 70 70 90 25 25 75 85 70 550 620 MIN 50 40 40 30 200 MAX 80 90 90 110 35 35 95 105 90 600 690 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
PARAMETER Lower Turn-off Propagation Delay (ALI-ALO, BLI-BLO) Upper Turn-off Propagation Delay (AHI-AHO, BHI-BHO) Lower Turn-on Propagation Delay (ALI-ALO, BLI-BLO) Upper Turn-on Propagation Delay (AHI-AHO, BHI-BHO) Rise Time Fall Time Turn-on Input Pulse Width Turn-off Input Pulse Width Turn-on Output Pulse Width Turn-off Output Pulse Width Disable Turn-off Propagation Delay (DIS - Lower Outputs) Disable Turn-off Propagation Delay (DIS - Upper Outputs) Disable to Lower Turn-on Propagation Delay (DIS - ALO and BLO) Refresh Pulse Width (ALO and BLO) Disable to Upper Enable (DIS - AHO and BHO)
SYMBOL TLPHL THPHL TLPLH THPLH TR TF TPWIN-ON TPWIN-OFF TPWOUT-ON TPWOUT-OFF TDISLOW TDISHIGH TDLPLH TREF-PW TUEN
TEST CONDITIONS
MIN -
RHDEL = RLDEL = 10K RHDEL = RLDEL = 10K RHDEL = RLDEL = 10K RHDEL = RLDEL = 10K
50 40 40 30 240 -
TRUTH TABLE INPUT ALI, BLI X 1 0 0 X NOTE: AHI, BHI X X 1 0 X U/V X 0 0 0 1 DIS 1 0 0 0 X ALO, BLO 0 1 0 0 0 OUTPUT AHO, BHO 0 0 1 0 0
BHI
DIS
4 5
VSS BLI
ALI
AHI
HDEL
LDEL
10
AHB
11 12 13 14 15 16 17 18 19 20
AHO AHS ALO ALS VCC VDD BLS BLO BHS BHO
XLI
XHI
XLO
XHO
THPLH
TLPLH
TR (10% - 90%)
TF (10% - 90%)
XLI
XLO
XHO
(10% - 90%)
(10% - 90%)
TDIS
XLI
XHI
XLO
XHO TUEN
10.0
9.5
9.0
8.5
8.0 0 100 200 300 400 500 600 700 800 900 1000 SWITCHING FREQUENCY (kHz)
4.0
75oC 25oC
20.0
3.0
0 oC -40oC
15.0
10.0
2.0
5.0
1.0
0.0 0 100 200 300 400 500 600 700 800 900 1000 0.0 0 100 200 300 400 500 600 700 800 900 1000 SWITCHING FREQUENCY (kHz) SWITCHING FREQUENCY (kHz)
-100
1.5
-110
0.5
1000
-120 -50
-25
100
125
FIGURE 9. ALI, BLI, AHI, BHI LOW LEVEL INPUT CURRENT IIL vs TEMPERATURE
VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 10K and TA = 25oC, Unless Otherwise Specified
15.0
80
14.0
70
13.0
60
12.0
50
11.0
40
10.0 -40
100
120
30 -40
-20
20
40
60
80
100
120
JUNCTION TEMPERATURE ( C)
FIGURE 10. AHB - AHS, BHB - BHS NO-LOAD CHARGE PUMP VOLTAGE vs TEMPERATURE
525
500
70
60
475
50
450
40
JUNCTION TEMPERATURE
60
400
50
40
375
30 350 -50
100
125 150
JUNCTION TEMPERATURE ( C)
VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 10K and TA = 25oC, Unless Otherwise Specified (Continued)
80
70
60
60
50
50
40
40
30
30
20 -40
-20
20
40
60
80
100
120
70
70
60
60
50
50
40
40
30
30 20 -40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120 JUNCTION TEMPERATURE (oC) JUNCTION TEMPERATURE (oC)
20
12.5
12.5
11.5
11.5
10.5
10.5
9.5
9.5
8.5 -40
-20
120
8.5 -40
-20
20
40
60
80
100
120
10
VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100K and TA = 25oC, Unless Otherwise Specified
1500
5.0
750 -40oC 500 0oC 25oC 250 75oC 125oC 12 BIAS SUPPLY VOLTAGE (V) 14
4.5
4.0 -40
-20
120
0 10
FIGURE 23. HIGH LEVEL OUTPUT VOLTAGE VCC - VOH vs BIAS SUPPLY AND TEMPERATURE AT 100mA
3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0
1250
750 -40oC 500 0 oC 25oC 250 75oC 125oC 0 10 12 BIAS SUPPLY VOLTAGE (V) 14
14
15
16
FIGURE 24. LOW LEVEL OUTPUT VOLTAGE VOL vs BIAS SUPPLY AND TEMPERATURE AT 100mA
11
VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100K and TA = 25oC, Unless Otherwise Specified (Continued)
500 200 100 50 20 10 5 2 1 0.5 0.2 0.1 1 2 5 10 20 50 100 200 500 1000 SWITCHING FREQUENCY (kHz) 10,000pF 3,000pF 1,000pF 100pF
FIGURE 27. LOW VOLTAGE BIAS CURRENT IDD (LESS QUIESCENT COMPONENT) vs FREQUENCY AND GATE LOAD CAPACITANCE
200 100 50
FIGURE 28. HIGH VOLTAGE LEVEL-SHIFT CURRENT vs FREQUENCY AND BUS VOLTAGE
9.0 UV+ BIAS SUPPLY VOLTAGE, VDD (V) 120 8.8 DEAD-TIME (ns) 75
o
150
90
8.6
60
UV8.4
30
12
IN2
IN1
+12V Q1 R29 JMPR5 CONTROL LOGIC SECTION + C6 DRIVER SECTION CR2 HIP4080A/81A U1 C4 1 BHB BHO 20 2 HEN/BHI BHS 19 3 DIS BLO 18 4 V SS 5 OUT/BLI 6 IN+/ALI 7 IN-/AHI 8 HDEL 9 LDEL R33 10 JMPR4 3 IN-/AHI 2 CW CD4069UB 1 2 CW 1 R34 3 CR1 C3 CX C5 CY 10 AHB BLS 17 16 V
DD
POWER SECTION B+ 2 C8
R21
1 3 1 Q3 2
U2 CD4069UB
JMPR1
OUT/BLI
13
13 5 11 ENABLE IN I R32
U2 CD4069UB U2 CD4069UB
12
JMPR2
IN+/ALI
JMPR3 HEN/BHI
HIP4081A HIP4081A
U2
R30
R31 COM
U2
CD4069UB 9 U2 8 O
1. DEVICE CD4069UB PIN 7 = COM, PIN 14 = +12V. 2. COMPONENTS L1, L2, C1, C2, CX, CY, R30, R31, NOT SUPPLIED. REFER TO APPLICATION NOTE FOR DESCRIPTION OF INPUT LOGIC OPERATION TO DETERMINE JUMPER LOCATIONS FOR JMPR1 - JMPR4.
CD4069UB
GND
+12V
JMPR5
R29
R27
R28
R26
C7
C6
R32
L1
IN1 I O IN2
JMPR1 JMPR2 JMPR3 JMPR4
L2
U2
HIP4080/81
HDEL
C5
CX
ALS
R30
CY
BLS
R31
14
B+
COM
HIP4081A HIP4081A
R23
O LDEL
C3
-C-
A2 B B1 C D D1 E E1 e eA eB L N
eA eC
C
C A B S
eB
NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the MO Series Symbol List in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
2.93
15
M20.3 (JEDEC MS-013-AC ISSUE C) 20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INCHES SYMBOL A MIN 0.0926 0.0040 0.013 0.0091 0.4961 0.2914 MAX 0.1043 0.0118 0.0200 0.0125 0.5118 0.2992 MILLIMETERS MIN 2.35 0.10 0.33 0.23 12.60 7.40 MAX 2.65 0.30 0.51 0.32 13.00 7.60 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93
L SEATING PLANE
A1 B
h x 45o
-A-
D -C-
C D
A1 0.10(0.004) C
E e H h L N
e
B 0.25(0.010) M C A M B S
NOTES: 1. Symbols are defined in the MO Series Symbol List in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width B, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporations quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 16
December 2001
100 dB
Features
Advantages n Replace expensive hybrid and module FET op amps n Rugged JFETs allow blow-out free handling compared with MOSFET input devices n Excellent for low noise applications using either high or low source impedance very low 1/f corner n Offset adjust does not degrade drift or common-mode rejection as in most monolithic amplifiers n New output stage allows use of large capacitive loads (5,000 pF) without stability problems n Internal compensation and large differential input voltage capability
Uncommon Features
LF155/ LF355
j Extremely
Units
5 2.5 20
12 5 12
50 20 12
V/s MHz
rate
j Wide gain
Applications
n n n n Precision high speed integrators Fast D/A and A/D converters High impedance buffers Wideband, low noise, low drift amplifiers
bandwidth
j Low input
noise voltage
Simplified Schematic
00564601
DS005646
www.national.com
LF155/LF156/LF256/LF257/LF355/LF356/LF357
(Note 1)
If Military/Aerospace specified devices are required, contact the National Semiconductor Sales Office/Distributors for availability and specifications. LF155/6 Supply Voltage Differential Input Voltage Input Voltage Range (Note 2) Output Short Circuit Duration TJMAX H-Package N-Package M-Package Power Dissipation at TA = 25C (Notes 1, 8) H-Package (Still Air) H-Package (400 LF/Min Air Flow) N-Package M-Package Thermal Resistance (Typical) JA H-Package (Still Air) H-Package (400 LF/Min Air Flow) N-Package M-Package (Typical) JC H-Package Storage Temperature Range Soldering Information (Lead Temp.) Metal Can Package Soldering (10 sec.) Dual-In-Line Package Soldering (10 sec.) Small Outline Package Vapor Phase (60 sec.) Infrared (15 sec.) 215C 220C 215C 220C 260C 260C 260C 300C 300C 300C 23C/W 65C to +150C 23C/W 65C to +150C 23C/W 65C to +150C 160C/W 65C/W 160C/W 65C/W 130C/W 195C/W 160C/W 65C/W 130C/W 195C/W 560 mW 1200 mW 400 mW 1000 mW 670 mW 380 mW 400 mW 1000 mW 670 mW 380 mW 150C 115C 100C 100C 115C 100C 100C LF256/7/LF356B LF355/6/7
See AN-450 Surface Mounting Methods and Their Effect on Product Reliability for other methods of soldering surface mount devices. ESD tolerance (100 pF discharged through 1.5k) 1000V 1000V 1000V
DC Electrical Characteristics
(Note 3) Symbol VOS VOS/T TC/VOS IOS Parameter Input Offset Voltage Average TC of Input Offset Voltage Change in Average TC with VOS Adjust Input Offset Current Conditions Min RS =50, TA =25C Over Temperature RS =50 RS =50, (Note 4) TJ =25C, (Notes 3, 5) TJTHIGH 5 0.5 3 20 20 LF155/6 Typ 3 Max Min 5 7 5 0.5 3 20 1 LF256/7 LF356B Typ 3 Max Min 5 6.5 5 0.5 3 50 2 LF355/6/7 Typ 3 Max 10 13 mV mV V/C V/C per mV pA nA Units
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LF155/LF156/LF256/LF257/LF355/LF356/LF357
DC Electrical Characteristics
(Note 3) Symbol IB RIN AVOL Parameter Input Bias Current Input Resistance Large Signal Voltage Gain Output Voltage Swing Input Common-Mode Voltage Range Common-Mode Rejection Ratio Supply Voltage Rejection Ratio (Note 6)
Conditions Min TJ =25C, (Notes 3, 5) TJTHIGH TJ =25C VS = 15V, TA =25C VO = 10V, RL =2k Over Temperature
LF155/6 Typ 30
Typ 30 10
12
Max 200 8
200
50 25
200
200
12 10 11
85 85
13 12
+15.1 12 100 100
12 10 11
85 85
13 12 15.1
12 100 100
12 10
+10 80 80
13 12
+15.1 12 100 100
V V V V dB dB
DC Electrical Characteristics
TA = TJ = 25C, VS = 15V Parameter Supply Current LF155 Typ 2 Max 4 LF355 Typ 2 Max 4 LF156/256/257/356B Typ 5 Max 7 LF356 Typ 5 Max 10 LF357 Typ 5 Max 10 Units mA
AC Electrical Characteristics
TA = TJ = 25C, VS = 15V LF155/355 Symbol SR Parameter Slew Rate Conditions Typ LF155/6: AV =1, LF357: AV =5 GBW ts en Gain Bandwidth Product Settling Time to 0.01% Equivalent Input Noise Voltage (Note 7) RS =100 f=100 Hz f=1000 Hz in Equivalent Input Current Noise Input Capacitance f=100 Hz f=1000 Hz 25 20 0.01 0.01 3 15 12 0.01 0.01 3 15 12 0.01 0.01 3 pF 2.5 4 5 1.5 5 LF156/256/ 356B Min 7.5 LF156/256/356/ LF356B Typ 12 50 20 1.5 LF257/357 Units Typ V/s V/s MHz s
CIN
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LF155/LF156/LF256/LF257/LF355/LF356/LF357
15V VS 20V
55C TA +125C +125C
15V VS 20V
25C TA +85C +85C
15V VS 20V
0C TA +70C +70C
and VOS, IB and IOS are measured at VCM = 0. Note 4: The Temperature Coefficient of the adjusted input offset voltage changes only a small amount (0.5V/C typically) for each mV of adjustment from its original unadjusted value. Common-mode rejection and open loop voltage gain are also unaffected by offset adjustment. Note 5: The input bias currents are junction leakage currents which approximately double for every 10C increase in the junction temperature, TJ. Due to limited production test time, the input bias currents measured are correlated to junction temperature. In normal operation the junction temperature rises above the ambient temperature as a result of internal power dissipation, Pd. TJ = TA + JA Pd where JA is the thermal resistance from junction to ambient. Use of a heat sink is recommended if input bias current is to be kept to a minimum. Note 6: Supply Voltage Rejection is measured for both supply magnitudes increasing or decreasing simultaneously, in accordance with common practice. Note 7: Settling time is defined here, for a unity gain inverter connection using 2 k resistors for the LF155/6. It is the time required for the error voltage (the voltage at the inverting input pin on the amplifier) to settle to within 0.01% of its final value from the time a 10V step input is applied to the inverter. For the LF357, AV = 5, the feedback resistor from output to input is 2k and the output step is 10V (See Settling Time Test Circuit). Note 8: Max. Power Dissipation is defined by the package characteristics. Operating the part near the Max. Power Dissipation may cause the part to operate outside guaranteed limits.
Curves are for LF155 and LF156 unless otherwise Input Bias Current
00564637
00564638
Voltage Swing
00564639
00564640
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LF155/LF156/LF256/LF257/LF355/LF356/LF357
Supply Current
00564641
00564642
00564643
00564644
00564645 00564646
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LF155/LF156/LF256/LF257/LF355/LF356/LF357
00564647
00564648
00564649
00564650
Output Impedance
00564651
00564652
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LF155/LF156/LF256/LF257/LF355/LF356/LF357
00564605
00564653
00564606
00564608
00564609
00564655
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LF155/LF156/LF256/LF257/LF355/LF356/LF357
00564656
00564657
Bode Plot
Bode Plot
00564658
00564659
Bode Plot
00564660
00564661
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LF155/LF156/LF256/LF257/LF355/LF356/LF357
00564662
00564663
00564664 00564665
00564666
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LF155/LF156/LF256/LF257/LF355/LF356/LF357
Detailed Schematic
00564613
Connection Diagrams
00564614
Order Number LF155H, LF156H, LF256H, LF257H, LF356BH, LF356H, or LF357H See NS Package Number H08C
*Available per JM38510/11401 or JM38510/11402
00564629
Order Number LF356M, LF356MX, LF355N, or LF356N See NS Package Number M08A or N08E
Application Hints
These are op amps with JFET input devices. These JFETs have large reverse breakdown voltages from gate to source and drain eliminating the need for clamps across the inputs. Therefore large differential input voltages can easily be accommodated without a large increase in input current. The maximum differential input voltage is independent of the supply voltages. However, neither of the input voltages should be allowed to exceed the negative supply as this will cause large currents to flow which can result in a destroyed unit. Exceeding the negative common-mode limit on either input will force the output to a high state, potentially causing a
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LF155/LF156/LF256/LF257/LF355/LF356/LF357
Application Hints
(Continued)
reversal of phase to the output. Exceeding the negative common-mode limit on both inputs will force the amplifier output to a high state. In neither case does a latch occur since raising the input back within the common-mode range again puts the input stage and thus the amplifier in a normal operating mode. Exceeding the positive common-mode limit on a single input will not change the phase of the output however, if both inputs exceed the limit, the output of the amplifier will be forced to a high state. These amplifiers will operate with the common-mode input voltage equal to the positive supply. In fact, the common-mode voltage can exceed the positive supply by approximately 100 mV independent of supply voltage and over the full operating temperature range. The positive supply can therefore be used as a reference on an input as, for example, in a supply current monitor and/or limiter. Precautions should be taken to ensure that the power supply for the integrated circuit never becomes reversed in polarity or that the unit is not inadvertently installed backwards in a socket as an unlimited current surge through the resulting forward diode within the IC could cause fusing of the internal conductors and result in a destroyed unit. All of the bias currents in these amplifiers are set by FET current sources. The drain currents for the amplifiers are therefore essentially independent of supply voltage. As with most amplifiers, care should be taken with lead dress, component placement and supply decoupling in order to ensure stability. For example, resistors from the output to an input should be placed with the body close to the input to minimize pickup and maximize the frequency of the feedback pole by minimizing the capacitance from the input to ground. A feedback pole is created when the feedback around any amplifier is resistive. The parallel resistance and capacitance from the input of the device (usually the inverting input) to AC ground set the frequency of the pole. In many instances the frequency of this pole is much greater than the expected 3dB frequency of the closed loop gain and consequently there is negligible effect on stability margin. However, if the feedback pole is less than approximately six times the expected 3 dB frequency a lead capacitor should be placed from the output to the input of the op amp. The value of the added capacitor should be such that the RC time constant of this capacitor and the resistance it parallels is greater than or equal to the original feedback pole time constant.
00564667
VOS is adjusted with a 25k potentiometer The potentiometer wiper is connected to V+ For potentiometers with temperature coefficient of 100 ppm/C or less the additional drift with adjust is 0.5V/ C/mV of adjustment Typical overall drift: 5V/C (0.5V/C/mV of adj.) Driving Capacitive Loads
00564668
* LF155/6 R = 5k
LF357 R = 1.25k Due to a unique output stage design, these amplifiers have the ability to drive large capacitive loads and still maintain stability. CL(MAX) . 0.01F. Overshoot 20% Settling time (ts) . 5s LF357. A Large Power BW Amplifier
00564615
For distortion 1% and a 20 Vp-p VOUT swing, power bandwidth is: 500kHz.
11
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LF155/LF156/LF256/LF257/LF355/LF356/LF357
Typical Applications
Settling Time Test Circuit
00564616
Settling time is tested with the LF155/6 connected as unity gain inverter and LF357 connected for AV = 5 FET used to isolate the probe capacitance Output = 10V step AV = 5 for LF357
00564617
00564619
LF356
00564618
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12
LF155/LF156/LF256/LF257/LF355/LF356/LF357
Typical Applications
00564620
VOUT/T = 0.002%/C All resistors and potentiometers should be wire-wound P1: drift adjust P2: VOUT adjust Use LF155 for
j Low IB j Low drift j Low supply current
00564621
Dynamic range: 100A Ii 1mA (5 decades), |VO| = 1V/decade Transient response: 3s for Ii = 1 decade C1, C2, R2, R3: added dynamic compensation VOS adjust the LF156 to minimize quiescent error RT: Tel Labs type Q81 + 0.3%/C
13
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LF155/LF156/LF256/LF257/LF355/LF356/LF357
Typical Applications
00564631
VO = 5 R1/R2 (V/mA of IS) R1, R2, R3: 0.1% resistors Use LF155 for
j Common-mode range to supply range j Low IB j Low VOS j Low Supply Current
00564632
R1, R2 should be matched within 0.05% Full-scale response time: 3s EO +9.920 +0.040 0.040 9.920 B1 B2 B3 B4 B5 B6 B7 B8 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Comments Positive Full-Scale (+) Zero-Scale () Zero-Scale Negative Full-Scale
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14
LF155/LF156/LF256/LF257/LF355/LF356/LF357
Typical Applications
00564670
Parasitic input capacitance C1 . (3pF for LF155, LF156 and LF357 plus any additional layout capacitance) interacts with feedback elements and creates undesirable high frequency pole. To compensate add C2 such that: R2 C2 . R1 C1. Boosting the LF156 with a Current Amplifier
00564673
15
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LF155/LF156/LF256/LF257/LF355/LF356/LF357
Typical Applications
00564624
00564622
Overshoot 6% ts 10s When driving large CL, the VOUT slew rate determined by CL and IOUT(MAX):
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16
LF155/LF156/LF256/LF257/LF355/LF356/LF357
Typical Applications
00564623
By adding D1 and Rf, VD1 =0 during hold mode. Leakage of D2 provided by feedback path through Rf. Leakage of circuit is essentially Ib (LF155, LF156) plus capacitor leakage of Cp. Diode D3 clamps VOUT (A1) to VINVD3 to improve speed and to limit reverse bias of D2. Maximum input frequency should be << 12RfCD2 where CD2 is the shunt capacitance of D2. Non-Inverting Unity Gain Operation for LF157
00564675
00564625
17
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LF155/LF156/LF256/LF257/LF355/LF356/LF357
Typical Applications
00564626
System VOS adjusted via A2 VOS adjust Trim R3 to boost up CMRR to 120 dB. Instrumentation amplifier resistor array recommended for best accuracy and lowest drift
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18
LF155/LF156/LF256/LF257/LF355/LF356/LF357
Typical Applications
00564633
Both amplifiers (A1, A2) have feedback loops individually closed with stable responses (overshoot negligible) Acquisition time TA, estimated by:
LF156 develops full Sr output capability for VIN 1V Addition of SW2 improves accuracy by putting the voltage drop across SW1 inside the feedback loop Overall accuracy of system determined by the accuracy of both amplifiers, A1 and A2
19
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LF155/LF156/LF256/LF257/LF355/LF356/LF357
Typical Applications
00564627
By closing the loop through A2, the VOUT accuracy will be determined uniquely by A1. No VOS adjust required for A2. TA can be estimated by same considerations as previously but, because of the added propagation delay in the feedback loop (A2) the overshoot is not negligible. Overall system slower than fast sample and hold R1, CC: additional compensation Use LF156 for
j Fast settling time j Low VOS
00564628
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20
LF155/LF156/LF256/LF257/LF355/LF356/LF357
Typical Applications
00564634
2R1 = R = 10M 2C = C1 = 300pF Capacitors should be matched to obtain high Q fNOTCH = 120 Hz, notch = 55 dB, Q > 100 Use LF155 for
j Low IB j Low supply current
21
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LF155/LF156/LF256/LF257/LF355/LF356/LF357
Physical Dimensions
Metal Can Package (H) Order Number LF155H, LF156H, LF256H, LF257H, LF356BH, LF356H or LF357H NS Package Number H08C
Small Outline Package (M) Order Number LF356M or LF356MX NS Package Number M08A
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22
Physical Dimensions
Molded Dual-In-Line Package (N) Order Number LF356N NS Package Number N08E
LIFE SUPPORT POLICY NATIONALS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
National Semiconductor Corporation Americas Email: support@nsc.com National Semiconductor Europe Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Franais Tel: +33 (0) 1 41 91 8790
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: ap.support@nsc.com
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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
SN54HC74, SN74HC74 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
SCLS094D DECEMBER 1982 REVISED JULY 2003
D D D D D D
Wide Operating Voltage Range of 2 V to 6 V Outputs Can Drive Up To 10 LSTTL Loads Low Power Consumption, 40-A Max ICC Typical tpd = 15 ns 4-mA Output Drive at 5 V Low Input Current of 1 A Max
description/ordering information
The HC74 devices contain two independent D-type positive-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of CLK. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.
1 2 3 4 5 6 7
14 13 12 11 10 9 8
2D NC 2CLK NC 2PRE
NC No internal connection
ORDERING INFORMATION
TA PDIP N SOIC D 40C to 85C SOP NS SSOP DB TSSOP PW CDIP J 55C to 125C CFP W LCCC FK PACKAGE Tube of 25 Tube of 50 Reel of 2500 Reel of 250 Reel of 2000 Reel of 2000 Tube of 90 Reel of 2000 Reel of 250 Tube of 25 Tube of 150 Tube of 55 ORDERABLE PART NUMBER SN74HC74N SN74HC74D SN74HC74DR SN74HC74DT SN74HC74NSR SN74HC74DBR SN74HC74PW SN74HC74PWR SN74HC74PWT SNJ54HC74J SNJ54HC74W SNJ54HC74FK SNJ54HC74J SNJ54HC74W HC74 HC74 HC74 HC74 TOP-SIDE MARKING SN74HC74N
SNJ54HC74FK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
1Q GND NC 2Q 2Q
SN54HC74, SN74HC74 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
SCLS094D DECEMBER 1982 REVISED JULY 2003
H H L X Q0 Q0 This configuration is nonstable; that is, it does not persist when PRE or CLR returns to its inactive (high) level.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Package thermal impedance, JA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65C to 150C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7.
SN54HC74, SN74HC74 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
SCLS094D DECEMBER 1982 REVISED JULY 2003
VCC = 6 V 400 400 TA Operating free-air temperature 55 125 40 85 C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC 2V IOH = 20 A VOH VI = VIH or VIL IOH = 4 mA IOH = 5.2 mA IOL = 20 A VOL VI = VIH or VIL IOL = 4 mA IOL = 5.2 mA II ICC Ci VI = VCC or 0 VI = VCC or 0, IO = 0 4.5 V 6V 4.5 V 6V 2V 4.5 V 6V 4.5 V 6V 6V 6V 2 V to 6 V 3 MIN 1.9 4.4 5.9 3.98 5.48 TA = 25C TYP MAX 1.998 4.499 5.999 4.3 5.8 0.002 0.001 0.001 0.17 0.15 0.1 0.1 0.1 0.1 0.26 0.26 100 4 10 SN54HC74 MIN 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4 1000 80 10 MAX SN74HC74 MIN 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 1000 40 10 nA A pF V V MAX UNIT
SN54HC74, SN74HC74 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
SCLS094D DECEMBER 1982 REVISED JULY 2003
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
VCC 2V fclock Clock frequency 4.5 V 6V 2V PRE or CLR low tw Pulse duration CLK high or low 4.5 V 6V 2V 4.5 V 6V 2V Data tsu Setup time before CLK PRE or CLR inactive 4.5 V 6V 2V 4.5 V 6V 2V th Hold time, data after CLK 4.5 V 6V 0 100 20 17 80 16 14 100 20 17 25 5 4 0 0 0 TA = 25C MIN MAX 6 31 36 0 150 30 25 120 24 20 150 30 25 40 8 7 0 0 0 SN54HC74 MIN MAX 4.2 21 25 0 125 25 21 100 20 17 125 25 21 30 6 5 0 0 0 ns ns ns SN74HC74 MIN MAX 5 25 29 MHz UNIT
switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER FROM (INPUT) TO (OUTPUT) VCC 2V fmax 4.5 V 6V 2V PRE or CLR tpd d CLK Q or Q Q or Q 4.5 V 6V 2V 4.5 V 6V 2V tt Q or Q 4.5 V 6V TA = 25C MIN TYP MAX 6 31 36 10 50 60 70 20 15 70 20 15 28 8 6 230 46 39 175 35 30 75 15 13 SN54HC74 MIN 4.2 21 25 345 69 59 250 50 42 110 22 19 MAX SN74HC74 MIN 5 25 29 290 58 49 220 44 37 95 19 16 ns ns MHz MAX UNIT
SN54HC74, SN74HC74 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
SCLS094D DECEMBER 1982 REVISED JULY 2003
LOAD CIRCUIT
Reference Input
50%
Input
tr
VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr = 6 ns, tf = 6 ns. C. For clock inputs, fmax is measured when the input duty cycle is 50%. D. The outputs are measured one at a time with one input transition per measurement. E. tPLH and tPHL are the same as tpd.
MECHANICAL DATA
MCFP002A JANUARY 1995 REVISED FEBRUARY 2002
W (R-GDFP-F14)
0.050 (1,27)
4040180-2 / C 02/02 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification only. Falls within MIL STD 1835 GDFP1-F14 and JEDEC MO-092AB
MECHANICAL DATA
MLCC006B OCTOBER 1996
FK (S-CQCC-N**)
28 TERMINAL SHOWN
18
17
16
15
14
13
12
NO. OF TERMINALS ** 11 10 28 9 8 7 6 68 5 84 44 52 20
A MIN 0.342 (8,69) 0.442 (11,23) 0.640 (16,26) 0.739 (18,78) 0.938 (23,83) 1.141 (28,99) MAX 0.358 (9,09) 0.458 (11,63) 0.660 (16,76) 0.761 (19,32) 0.962 (24,43) 1.165 (29,59) MIN 0.307 (7,80) 0.406 (10,31) 0.495 (12,58) 0.495 (12,58) 0.850 (21,6) 1.047 (26,6)
B MAX 0.358 (9,09) 0.458 (11,63) 0.560 (14,22) 0.560 (14,22) 0.858 (21,8) 1.063 (27,0)
19 20 21 B SQ 22 A SQ 23 24 25
26
27
28
4040140 / D 10/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold plated. Falls within JEDEC MS-004
MECHANICAL
MPDI002C JANUARY 1995 REVISED DECEMBER 20002
N (R-PDIP-T**)
16 PINS SHOWN
A MIN
MS-100 VARIATION
AA
BB
AC
AD
0.325 (8,26) 0.300 (7,62) 0.015 (0,38) 0.200 (5,08) MAX Seating Plane 0.125 (3,18) MIN 0.010 (0,25) NOM Gauge Plane
D 4040049/E 12/2002
NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001, except 18 and 20 pin minimum body lrngth (Dim A). D. The 20 pin end lead shoulder width is a vendor option, either half or full width.
MECHANICAL DATA
MSOI002B JANUARY 1995 REVISED SEPTEMBER 2001
D (R-PDSO-G**)
8 PINS SHOWN 0.050 (1,27) 8 5 0.020 (0,51) 0.014 (0,35) 0.010 (0,25)
0.010 (0,25)
Seating Plane 0.069 (1,75) MAX 0.010 (0,25) 0.004 (0,10) 0.004 (0,10)
4040047/E 09/01 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). Falls within JEDEC MS-012
MECHANICAL DATA
MSSO002E JANUARY 1995 REVISED DECEMBER 2001
DB (R-PDSO-G**)
28 PINS SHOWN 0,65 28 0,38 0,22 15 0,15 M
PLASTIC SMALL-OUTLINE
14
16
20
24
28
30
38
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
NOTES: A. B. C. D.
All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150
MECHANICAL DATA
MTSS001C JANUARY 1995 REVISED FEBRUARY 1999
PW (R-PDSO-G**)
14 PINS SHOWN
0,65 14 8
0,30 0,19
0,10 M
0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 A 7 0 8 0,75 0,50
14
16
20
24
28
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153
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