Aspect Ratio Driven Floorplan for IR Drop and Die Size Reduction

Abstract A technique to improve the voltage drop and die size by correctly specifying the aspect ratio of a die is being proposed. The approach establishes a relationship between the metal directions and the aspect ratio of the die design and proposes the direction in which the aspect ratio of a die should be chosen (< 1 or > 1) so that the die level voltage drop and its distribution improves. If the metal flow direction and the respective resistivity of the metal layers is used as one of the determinants of the eventual aspect ratio of the die, the voltage drop and its distribution is improved and consequently, the die size can be reduced.

Introduction During the floor-planning of a design, the intent always has been to have a square chip with the aspect ratio of 1. With design implementation moving more towards the maximum IP reuse and SoC approach, more and more hard IP blocks like Flash, Analog blocks, custom IPs, get designed for one IC, considering the aspect ratio and placement constraints of that IC but get re-used on multiple ICs thereafter. As a result, more and more die designs tend to have asymmetrical X/Y dimensions, which get driven by the placement of these big hard IPs which constrains each of X/Y die dimensions and inturn, lead to a non squarish aspect ratio.

There are many factors, which need to be kept in mind, while deciding the X/Y dimensions of the design, the primary one being understanding of the total good die per wafer number corresponding to a particular X/Y dimension and then swapping these X/Y dimensions to check if the number of good dies per wafer changes. Accordingly, the dimensions (and hence the aspect ratio) get locked, corresponding to X/Y that gives better wafer yield, without considering anything else.

Description of the Proposed Approach This paper discusses one more such factor, which should be kept in mind, besides the primary factor discussed above, since it helps with the better utilization of the power grid, thereby improving voltage drop and saving precious die area. This concept entails considering the direction and the resistivity of the interconnect metal as one of the additional factors for deciding the aspect ratio of the chip. This implies that the direction of the higher level metal layer with lesser resistivity be used as a starting point for analyzing as to which of the two dimensions of the chip (X or Y) be more, for same area and any growth in the die dimensions should happen only in the direction of least resistive metal, such that the longer dimension is the in the direction of the flow of least resistive metal. This approach has shown to greatly improve the die level IR drop in with the same power grid. Advantages clearly are in terms of the yield improvement and lesser IR drop in the die. The approach adds a step in the design process, where, a conscious analysis is done for the aspect ratio of the design considering the metal

resistivity. It is to be noted here that in the conventional approach, aspect ratio is an output of the floorplanning stage whereas, in the proposed approach, the aspect ratio is an input. Figure 1, shows the stage, where this step fits into the design flow

Figure 1 Comparison between the conventional and proposed flow steps

Example to Illustrate the Proposed Approach The approach is being illustrated taking a sample technology node and noting the metal resistivity and the direction of flow of the metals Metal Metal 4 Metal5 Metal6 Sheet Resistance (ohms/square) 0.065 0.065 0.022
Table 1

Metal Flow Direction Horizontal Vertical Horizontal

As can be seen in table1, the sheet resistance of metal6 is approximately 3 times lesser than that of metal5. So, leaving aside other factors, theoretically, a single metal6 wire of a particular width/length will have 3 times lesser voltage drop than the same length/width wire laid out in metal5, when carrying same amount of current.

The point, therefore, is that for a non-squarish die, we must floorplan the die in such a way that the longer dimension is the dimension of lesser resistive metal. So, as shown in the above table, a die based on this proposal would have its X-dimension greater than the Y dimension, since metal6 is horizontal). This improves the IR drop, without having to use additional metal resources, apart from providing a better voltage drop distribution in the die and fully utilizing the existing grid.

Figure 2 and Figure 3 show the IR drop profile for 2 different aspect ratios. As per the proposed approach, if there is a toss-up between 2 aspect ratios, as shown in Figure 2 and Figure 3 (and considering that all other factors weigh equally on both), Figure 3 should be preferred and the die be floorplanned, accordingly. (For simplicity, the IR drop analysis has been done using one current source per side of the design).

Figure 2 Case I 6100um x 8200um

Figure 3 Case II 8200um x 6100um

Results The results of the IR drop analysis, done on the two cases, as shown in figure 2 and figure 3 are tabulated in table 2. Current Number 100 mA 900 mA Case I Voltage Drop 13.86 mV 124.75 mV
Table 2

Case II Voltage Drop 13.39 mV 120.47 mV

Percentage Change 3.5% 3.5%

The results indicate that there is a positive reduction in the IR drop in Case-II which has the aspect ratio as proposed. Additionally, another

important point to note here is that the hot-spot region is lesser along Y direction (direction of metal5), as can be seen in case-II. Removing this hot-spot along the vertical direction would be a lot easier exercise than doing so for case-I where the metal5 resistivity is high enough to become a bottleneck towards reducing the IR drop along Y direction

Impact on Die Size The impact on die size can be best understood in an indirect manner by trading IR drop for die area. The IR drop reduction is directly implemented in terms of the reduced die size. In Case-II scenario, to make the proposed aspect ratio floorplan have the same IR drop as Case-I (that is 3.5% more), we can afford to decrease the widths of Metal3, Metal4 and Metal5, by a track each (0.13um) per stripe. The total decrease (for complete die) in respective metal areas for Metal3, Metal4 and Metal5 and resultant die area is tabulated in table 3

Metal Layer

Number of Metal Stripes Metal3 273 Metal4 273 Metal5 273

Total Power Total Power Metal Area Metal Metal Area (For Case-I IR = Case-II IR) Area Saving 2.39mm^2 2.19mm^2 0.2 mm^2 2.39mm^2 2.19mm^2 0.2 mm^2 2.39mm^2 2.19mm^2 0.2 mm^2

Total effective die area saving (to maintain same IR drop) = 0.4 mm^2

Summary The proposed approach has shown to give an improvement of nearly 4mV of IR drop in the sample test-case chosen, using the same power mesh between the conventional approach and the proposed approach. Apart from the savings on the IR drop (without using any additional metal resources), the approach also provides better and realistic voltage profile in the chip, thereby utilizing the existing mesh most optimally. In an indirect way, by trading IR drop for die area, the approach has shown to provide good die area improvement, if the designer is ready to maintain the IR drop and let go any improvements in IR drop, for the sake of die area improvement.