ECE 474a/574a Optional Practice Problems

1. Convert the following Moore FSM to a Mealy FSM.

ab A w=1 ab ab b C w=0 b b + ab D w=1 a Inputs: ab; Outputs: w B w=1 ab

2.

Convert the following Mealy FSM to a Moore FSM

Inputs: y; Outputs: e y/e=0 y / e = 1 A y/e=1 B y / e = 0

3.

Create a high-level state machine for a simple data encryption/decryption device. If a bitinput b is 1, the device stores the data from a 32-bit input I as what is know as an offset value. If b is 0 and another bit-input e is 1, then the device encrypts its input I by adding the stored offset value to I, and outputs this encrypted value over a 32-bit output J. If instead another bit-input d is 1, the device should decrypt the data on output J by subtracting the offset value before outputting the decrypted value of J. Be sure to explicitly handle all possible combinations of the three input bits (input b has the highest priority, then e, then d).

I 32 b e d Encrypt/Decrypt Circuit 32

4.

Create a high-level state machine that loads the data from a digital camera into a RAM, beginning at the address specified by input start, and ending at the address specified by input stop. Input go initiates loading data from the digital camera into the RAM. Setting RCPY = 1 signals the digital camera to output a data item on every clock cycle. Once the loading process starts, it will continue until all values have been processed. Lastly, the data bus may be shared by other peripherals.

Data

Addr

Digital Camera

65K x 8 ROM
R/w En

RBUF RCPY

RA

RW RE

Processor

5.

Create a datapath for the following high-level FSM.

Inputs: A (8-bits), B (8-bits), go, hold Outputs: M (16-bits) Local Register: Sum (16-bits), A_reg (8-bits), B_reg (8-bits), count (8-bits) hold go go A Sum = 0 M=0 B A_reg = A B_reg = B count = 0 C Sum = Sum + A count++ D count < B (count < B) E M = Sum hold

go

start stop

6.

Perform two-level logic optimization for F(a, b, c, d) = abcd + acd + acd + bcd + acd using K-maps.

7.

Using the K-map provided, identify a) minterms b) implicants c) prime implicants d) essential prime implicants

bc a 0 1 00 1 1 1 01 11 1 1 10 1

8.

Assuming muxes have a delay of 5 ns, adders and shifters have 10 ns delay, multipliers have 20 ns delay, and wires have 2 ns delay, a) b) c) What is the critical path of the datapath and its corresponding delay? What is maximum system clock frequency given the current datapath? What modifications can be made to the datapath to increase the system clock frequency?

A + *

* << +2

9.

Convert the following C-like code to a high-level finite state machine.

Z
Inputs: byte a[32], wait Outputs: byte max MAX_VALUE: byte temp; while(1){ while(wait); temp = 0; for( i=0; i<32; i++) { if( a[i] > temp)[ temp = a[i]; } } max = temp; }

10. Using Quine-McCluskey (tabular minimization method) minimize F(a, b, c, d) = m(1, 2, 3, 4, 5) + d(12, 13, 14, 15). 11. What is the difference between an exact algorithm and a heuristic? 12. Using the Shannon expansion theorem, determine the positive and negative cofactors of F(a, b, c) = ac + b + abc with respect to c. 13. Convert the following state table to and FSM.

A B C D

s1 0 0 0 0 1 1 1 1

s0 0 0 1 1 0 0 1 1

gcnt 0 1 0 1 0 1 0 1

n1 0 0 0 1 1 1 1 0

n0 0 1 1 0 0 1 1 0

x 0 0 0 0 1 1 1 1

z 0 0 1 1 1 1 0 0

14. What is the difference between a FSM and a high-level FSM? 15. Describe the functionality of a 3-input XOR gate using an ASM chart.