Topic05 Dealing With Interrupts On The Freescale MC9S12X

Topic Video 05
Interrupts: Not just one of Lifes little annoyances.
Tuesday, 7 July 2009
What is an interrupt?
Pete... Take the rubbish out Please...
Ill do it later... Pete... Take the rubbish out Please...
Ill do it later... Pete... Take the rubbish out Please...
You will do it now or no computer for a week...
Why?
All tasks are not created equal. Not all tasks are predictable.
What is a Hardware Interrupt...

D PC X Y CCR SP
Running
CPUS12
Stack
4

D PC X Y CCR SP
Running
CPUS12
Stack
4

D PC X Y CCR SP
Halted
CPUS12
Stack
4

D PC X Y CCR SP PC
Halted
CPUS12
Stack
4

D PC X Y CCR SP Y PC
Halted
CPUS12
Stack
4

D PC X Y CCR SP X Y PC
Halted
CPUS12
Stack
4

D PC X Y CCR SP D X Y PC
Halted
CPUS12
Stack
4

D PC X Y CCR SP CCR D X Y PC
Halted
CPUS12
Stack
4

D PC X Y
Interrupts Disabled
Halted
CCR D X Y PC
CCR SP
CPUS12
Stack
4

D PC X Y
Interrupts Disabled
Halted
CCR D X Y PC
CCR SP
CPUS12
Stack
5

D PC X Y
Interrupts Disabled
Halted
CCR D X Y PC
CCR SP
CPUS12
Stack
5

D PC X Y
Interrupts Disabled
Halted
CCR D X Y PC
CCR SP
CPUS12
Stack
5

D PC X Y
Interrupts Disabled
Running
CCR D X Y PC
CCR SP
CPUS12
Stack
5

D PC X Y
Interrupts Disabled
Running
CCR D X Y PC
CCR SP
CPUS12
Stack
5

D PC X Y
Interrupts Disabled
Halted
CCR D X Y PC
CCR SP
CPUS12
Stack
5

D PC X Y
Interrupts Disabled
Halted
CCR D X Y PC
CCR SP
CPUS12
Stack
6

D PC X Y
Interrupts Disabled
Halted
CCR D X Y PC
CCR SP
CPUS12
Stack
6

Halted
CPUS12
Stack
6

Halted
CPUS12
Stack
6

Halted
CPUS12
Stack
6

D PC X Y CCR SP PC
Halted
CPUS12
Stack
6

D PC X Y CCR SP
Halted
CPUS12
Stack
6

D PC X Y CCR SP
Running
CPUS12
Stack
6
SCPU12 Interrupts
The MC9S12XDP512 contains vectored interrupts with hardware priority resolution that can be customized with software. The MC9S12XDP512 contains two external dedicated interrupt lines IRQ and XIRQ located on port E. The IRQ The XIRQ The MC9S12XDP512 contains numerous internal interrupt sources that are associated with the various internal subsystems.
Questions that need to be answered...

Do we need an interrupt? Who will trigger the interrupt and under what conditions?
Internal or External source? Run some code?
What must be done when it occurs?
Interrupt Vector Table
What is an Interrupt Vector Table?
A table of pointers in memory that point to subroutines that need to be executed once the interrupt it triggered. Each interrupt source has its own special location in this table.
Vector Address $FFFE $FFFC $FFFA Interrupt Source System reset Clock Monitor Reset COP Watchdog Reset Unimplemented OpCode SWI XIRQ IRQ CCR Mask None None None None None X-bit I-bit Local Enable None PLLCTL COP Rate select None None None IRQCR
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Vector Base + $F8 Vector Base + $F6 Vector Base + $F4 Vector Base + $F2
Setting the Vector Base

Apart from the vectors for the three reset sources (Reset, Clock Reset and Watchdog Reset) the vector table can be located anywhere inside system memory. The vector base address must be set using the IVBR register.
IVBR ($0121)
VB7 VB6 VB5 VB4 VB3 VB2 VB1 VB0
Holds the MSB of the vector base address.
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What else?

The vector table makes the connection between a interrupt source and the corresponding code that must be executed. Code that is executed as a result of an interrupt is referred to as an interrupt service routine (ISR). By putting the address of the ISR into a particular position of the vector table, will ensure that the ISR will be executed if that interrupt source is triggered. So as long as the interrupt source is enabled, the ISR will run.
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Controlling Interrupts
The X bit in the CCR is used to control the XIRQ interrupt source. The I bit in the CCR is used to control the remaining interrupt sources. The interrupts will only work if they have been properly enabled.
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Controlling Interrupts
The Interrupt Process
Using the two bits in the CCR namely the X and I bits, it is possible to control the entire interrupt subsystem. Each maskable interrupt can be individually disabled or enabled by setting the appropriate bit in the devices control registers. During an interrupt, the X bit remains unchanged, this means a non maskable interrupt can occur within an interrupt service routine. The use of nested interrupts should be avoided, however it is possible to have nested interrupts if the I bit is cleared during an interrupt service routine (recommended only for experts). Interrupts are disabled on reset.
Tuesday, 7 July 2009 13
Things you need to do...

Initialising Interrupt Vectors
Before using interrupts, the interrupt vectors must be initialised to point to the appropriate interrupt service routines. If a subsystem uses the interrupt facility then the interrupt vector must be set and a interrupt service routine provided. The Hardware Reset interrupt vector must be set to point to the beginning of the code. When the processor is originally powered up or reset, the routine pointed to by the hardware interrupt service will be executed.
Reset Vector Example

Entry: LDS CLI mainLoop: BRA * #RAMEnd+1 ; initialize the stack pointer ; enable interrupts
;************************************************************** ;* Interrupt Vectors *
;************************************************************** ORG $FFFE DC.W Entry ; Reset Vector
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Interrupt Sources
Inside the MC9S12XDP512 there are approximately 128 possible subsystem interrupt sources that can be enabled or disabled by bits locally contained within the control registers of the particular I/O subsystem. Each of these sources has its own interrupt vector associated with it and therefore has space allocated inside the vector table. When an interrupt request is generated the value located in the interrupt vector for the particular source is fetched and loaded into the program counter.
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Interrupt Sources
External Interrupt Sources (IRQ) An interrupt request on the IRQ pin is generated by external logic. The IRQ pin is an active low signal and you may set it to a level active or a negative edge response. The Interrupt Control Register located at $001E contains bits to select which response is needed and to enable or disable the IRQ pin.
Interrupt Control Register (IRQCR): ($001E)

IRQE IRQEN DLY 0 0 0 0 0
IRQE: IRQ Select Edge Sensitivity (0=level triggered, 1=falling edge triggered). IRQEN: Enable IRQ pin (1=enabled, 0=GPIO)
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Other Interrupt Sources

Exceptions
In a system, there are always events that are so important that they should never be ignored. These events are usually referred to as exceptions. RESET This the hardware reset, this usually take place when the system is reset or rstly powered up. This interrupt has the highest priority of all the interrupts.
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Exceptions
CLOCK MONITOR FAILURE If the CPU clock signals slow down or fails and the Clock monitor is enabled. The clock monitor will detect a problem and issue a CME reset signal. However it is impossible for the CPU to execute the interrupt until the clock signal reappears.
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Exceptions
COMPUTER OPERATING NORMALLY Also referred to as the watchdog timer. If your program crashes or hangs then this exception is triggered.
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Exceptions
UNIMPLEMENTED OPCODE TRAP If for some reason the program gets lost and begins executing data, it is highly likely that it will try to execute an unimplemented op-code. If this does occur the CPU will trigger the an interrupt and the unimplemented opcode trap vector will be fetched and executed.
21
SOFTWARE INTERRUPT The software interrupt is effectively a branch to the subroutine whose address is located in the software interrupt vector. It is a software triggered interrupt.
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NON-MASKABLE INTERRUPT REQUEST XIRQ is an external non-maskable interrupt input. It is controlled using only the X bit in the CCR. Once the X bit has been cleared it is impossible to set this bit again once the program has commenced.
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Interrupt Flags / Internal Interrupt Sources
Interrupts
There exists many internal interrupt sources form the various built-in subsystems. In order to use the interrupt capability of these subsystems, global interrupts must be enabled and the enable bit set in the appropriate control register for the I/O device. Some subsystems set a ag bit in a status register when an interrupt occurs and if this ag isnt reset then an interrupt will trigger again once ISR is complete.
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Interrupt Subsystem
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Waiting for an Interrupt...

What to do while waiting for an interrupt:
Spin Loops
The simplest way to make the CPU wait is to implement a spin loop. A spin loop consists of a branch instruction back to itself. For example: LOOP: BRA LOOP
When an interrupt occurs the loop will be interrupted and will continue the loop when the ISR completes.
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WAI: Wait for interrupt

The WAI performs two functions: Firstly, it pushes the CPU contents onto the stack in preparation for the upcoming interrupt, this reduces the delay involved in executing the ISR. Secondly, it places the CPU into a wait state, reducing the overall power consumption. When the interrupt is triggered the ISR is executed and upon returning from the interrupt, the interrupted program will continue from the next instruction following the WAI instruction.
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Stop: Stop clocks instruction
The nal method involves using the STOP instruction, this will stop the clocks, and dramatically reduce the power consumption of the CPU. Only the interrupts IRQ, XIRQ and RESET can remove the CPU from this state.You should also ensure that the watchdog timer is disabled otherwise this instruction will trigger a watchdog interrupt.
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Whats so special about an ISR?
An interrupt service routine (ISR) is simply a subroutine terminated by an RTI instead of RTS.
The interrupt service routine is only executed once the interrupt vector has been initialised properly, interrupts have been enabled and unmasked, an interrupt has occurred, the CPU registers have been pushed onto the stack, and the vector has been fetched.
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Great care must be taken when using the stack inside an ISR. All PSH commands must have corresponding PUL commands of equal size. All JSR must have corresponding RTS at the end of the subroutine. Failure to restore the stack to its original state will result in the register set being reloaded incorrectly at the end of the ISR. Hints to writing successful Interrupt Services Routines are:
Re-enable Interrupts in the ISR only if you need them, if there are higher level interrupts that need servicing then you can re-enable the interrupts by clearing the I bit. Do not use nested interrupts, unless you really have to. Reset any interrupt generating ags in the I/O devices prior to exiting the ISR. If you do not reset the ag the device will immediately generate another interrupt upon exiting the ISR.
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Do not worry about using registers in the ISR. Do not assume any register contents. Keep ISRs simple to begin with. Keep ISR short.
31
Another example
Virgin System
TCO: Entry: EQU ORG $FFEE ROMSTART ; Address of vector for Timer channel 0 LDS
#RAMEnd+1
; initialize the stack pointer ; enable interrupts
MOVB #$FF,IVBR CLI

MainLoop: BRA * TCOISR: NOP RTI ORG TCO DC.W TCOISR
;Location of TC0 interrupt vector ; The label of the address is the TCO ISR.
32
Another example
uBug12 System
TCO: Entry: EQU ORG $FFEE ROMSTART ; Address of vector for Timer channel 0 LDS
#RAMEnd+1
; initialize the stack pointer ; enable interrupts
MOVB #$F7,IVBR CLI

MainLoop: BRA * TCOISR: NOP RTI ORG TCO DC.W TCOISR
;Location of TC0 interrupt vector ; The label of the address is the TCO ISR.
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ReCap: The interrupt process...

D PC X Y CCR SP
Running
CPUS12
Stack
34

D PC X Y CCR SP
Running
CPUS12
Stack
34

D PC X Y CCR SP
Halted
CPUS12
Stack
34

D PC X Y CCR SP PC
Halted
CPUS12
Stack
34

Halted
CPUS12
Stack
34

Halted
CPUS12
Stack
34

Halted
CPUS12
Stack
34

D PC X Y CCR SP CCR D X Y PC
Halted
CPUS12
Stack
34

D PC X Y
Interrupts Disabled
Halted
CCR D X Y PC
CCR SP
CPUS12
Stack
34

D PC X Y
Interrupts Disabled
CCR SP
... IRQ IRQ ... Reset

35
CPUS12

D PC X Y
Interrupts Disabled
CCR SP
... IRQ ... Reset

35
CPUS12

D PC X Y
Interrupts Disabled
Halted
CCR D X Y PC
CCR SP
CPUS12
Stack
36

D PC X Y
Interrupts Disabled
Halted
CCR D X Y PC
CCR SP
CPUS12
Stack
36

D PC X Y
Interrupts Disabled
Running
CCR D X Y PC
CCR SP
CPUS12
Stack
36

D PC X Y
Interrupts Disabled
Running
CCR D X Y PC
CCR SP
CPUS12
Stack
36

D PC X Y
Interrupts Disabled
Halted
CCR D X Y PC
CCR SP
CPUS12
Stack
36

D PC X Y
Interrupts Disabled
Halted
CCR D X Y PC
CCR SP
CPUS12
Stack
37

D PC X Y
Interrupts Disabled
Halted
CCR D X Y PC
CCR SP
CPUS12
Stack
37

Halted
CPUS12
Stack
37

Halted
CPUS12
Stack
37

Halted
CPUS12
Stack
37

D PC X Y CCR SP PC
Halted
CPUS12
Stack
37

D PC X Y CCR SP
Halted
CPUS12
Stack
37

D PC X Y CCR SP
Running
CPUS12
Stack
37
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Topic Video 05

Interrupts: Not just one of Lifes little annoyances.

Tuesday, 7 July 2009

Tuesday, 7 July 2009

Tuesday, 7 July 2009

Tuesday, 7 July 2009

Tuesday, 7 July 2009

You will do it now or no computer for a week...

Tuesday, 7 July 2009

Tuesday, 7 July 2009

What is a Hardware Interrupt...

What is a Hardware Interrupt...

What is a Hardware Interrupt...

What is a Hardware Interrupt...

What is a Hardware Interrupt...

What is a Hardware Interrupt...

What is a Hardware Interrupt...

What is a Hardware Interrupt...

What is a Hardware Interrupt...

What is a Hardware Interrupt...

What is a Hardware Interrupt...

What is a Hardware Interrupt...

What is a Hardware Interrupt...

What is a Hardware Interrupt...

What is a Hardware Interrupt...

What is a Hardware Interrupt...

What is a Hardware Interrupt...

What is a Hardware Interrupt...

What is a Hardware Interrupt...

What is a Hardware Interrupt...

What is a Hardware Interrupt...

What is a Hardware Interrupt...

What is a Hardware Interrupt...

Tuesday, 7 July 2009

Questions that need to be answered...

Internal or External source? Run some code?

What must be done when it occurs?

Tuesday, 7 July 2009

Interrupt Vector Table

What is an Interrupt Vector Table?

Setting the Vector Base

Holds the MSB of the vector base address.

Tuesday, 7 July 2009

Tuesday, 7 July 2009

Things you need to do...

Reset Vector Example

;************************************************************** ;* Interrupt Vectors *

;************************************************************** ORG $FFFE DC.W Entry ; Reset Vector

Tuesday, 7 July 2009

Tuesday, 7 July 2009

Interrupt Control Register (IRQCR): ($001E)

Tuesday, 7 July 2009

Other Interrupt Sources

Tuesday, 7 July 2009

Other Interrupt Sources

Tuesday, 7 July 2009

Other Interrupt Sources

Tuesday, 7 July 2009

Other Interrupt Sources

Tuesday, 7 July 2009

Other Interrupt Sources

Tuesday, 7 July 2009

Other Interrupt Sources