Topic08 Introduction To The Serial Interfaces On The Freescale MC9S12X

Topic Video 08
Serial Subsystems: Clocked or Unclocked...
Thursday, 22 October 2009
Cereal Communications
Hows it going? OK, Cant Complain
Cereal Communications
Hows it going? OK, Cant Complain
Serial Communication
Even though the use of parallel communication seems more logical it does require the use of more external pins on the device. More pins means bigger IC packaging is required. One of the advantages of serial communication is the fact that it uses only a small number of pins.
Serial I/O is the transmission of of data over a single communication line. The data is transmitted sequentially, one bit at a time. This process requires a conversion of the data from a parallel format to serial one. The conversion process is achieved using a shift register on both the transmitter when it is sent and on the receiver when it is received. Both shift registers are driven by a clock that can be either encoded into the signal or transmitted in parallel on a separate channel.
How it Works...
Transmitter
Double Buffered, LSB rst example.
Thursday, 22 October 2009 5
How it Works...
Transmitter
5
$82
How it Works...
$82
Transmitter
How it Works...
10000010
Transmitter
5
$64
How it Works...
10000010
$64
Transmitter
How it Works...
10000010 01100100 Transmitter

How it Works...
01100100 Transmitter
How it Works...
Transmitter
How it Works...
Receiver
How it Works...
01100100 Receiver
10000010
How it Works...
01100100 Receiver
10000010
How it Works...
01100100 Receiver
Double Buffered, LSB rst example. $82
How it Works...
Receiver
01100100
$82
How it Works...
Receiver
$64
$82
How it Works...
Receiver
Double Buffered, LSB rst example. $64
How it Works...
Receiver
How it Works...
Transmitter
Double Buffered, MSB rst example.
How it Works...
Transmitter
Double Buffered, MSB rst example. $82
How it Works...
Transmitter
$82
How it Works...
Transmitter
10000010
$64
How it Works...
How it Works...
01100100
How it Works...
How it Works...
Transmitter
How it Works...
Receiver
How it Works...
10000010
01100100 Receiver
How it Works...
01100100 10000010 Receiver

How it Works...
01100100
$82
Receiver
How it Works...
01100100
Receiver
$82
How it Works...
$64
Receiver
$82
How it Works...
Receiver
How it Works...
Receiver
There are two methods of serial communication: Synchronous Serial Communication Asynchronous Serial Communication
On-Chip Serial Devices

The MC9S12XDP512 contains a large range of possible serial solutions, including:
Six Asynchronous Serial Communications Interfaces (RS232), Three Synchronous Serial Peripheral Interface (SPI), and A single Synchronous Inter-Intergrated Chip (I2C) Interface.
10
A common form of Asynchronous Serial is RS232. The receiver and transmitter have separate independent local clocks. The receiver phase locks its local clock to the transmitters clock by detecting the start and end of a transmission. TX RX GND
Asynchronous Serial Communication
11

In asynchronous serial communication, the start of transmission is signied by a start bit. The start bit is a logical 1. The end of transmission is represented by one or two stop bits. The stop bits are logical 0.
Start bit
Data
Stop bits
12

Therefore at the start of a transmission there is a transition from 0 to 1. The receivers clock is phase aligned to the positive edge of this transition. The stop bit also acts as an error checking mechanism.
Start bit
Data
Stop bits
13

An asynchronous serial transmission consists of one more additional element; the parity bit. Using this single parity bit it is possible to detect single bit errors. Parity bit
P
Start bit
Data
Stop bits
14

Via programmable registers it is possible to enable or disable the parity bit. Is also possible to set the parity bit to be even or odd parity. Parity bit
P
Start bit
Data
Stop bits
15
Data
Even Parity bit

P
Data
Even Parity bit

P
Start bit
Data
Stop bits
16
Data
Odd Parity bit

P
Data
Odd Parity bit

P
Start bit
Data
Stop bits
17

The communication rates for serial transmission are denoted by two terms:
Characters per second (CPS): The rate at which 8 bit data is transmitted. Baud rate (Baud): Frequency of the carrier used to transmit the data.
The relationship between CPS and Baud is CPS = Baud ( Numberbits in Character + NumberStop bits + NumberStart bits + NumberParity bits)
18
Full duplex or Half duplex?
Full-duplex:
TX RX
Two Channels
Half-duplex:
One Channel
20
Half-duplex:
One Channel
20
Half-duplex:
One Channel
20
On-Chip RS232 Serial Devices - SCI5) are The six on Chip RS232 devices (SCI0
SCI0 SCI2 SCI3 SCI4
provided through a number of different ports on the MC9S12XDP512.

SCI1
PortS PortJ PortM
SCI5
PortH
21
On-Chip RS232 Serial Devices

The SCIs are full duplex asynchronous serial interfaces. Each with an independent on-chip baud rate generator . The receiver and transmitted are both double buffered, they use the same baud rate and frame format even though they operate independently. The SCI interface can send either 8 bit or 9 bit data. Each device is fully programmable and provides a variety of interrupt sources.
22
The Programmers Model

All interaction with the SCIs is done via there I/O register set. (Note that the x in the register name should be replaced with device number [0-5])
SCIxBDH SCIxCR1 SCIxBDL SCIxCR2 SCIxSR1 SCIxACR1 SCIxSR2 SCIxACR2 SCIxASR1 SCIxDRL SCIxDRH
23

The I/O register for each device is located in a different area of the memory. When referring to each register, the address of the register is shown relative to an offset.
Device
SCI0 SCI1 SCI2 SCI3 SCI4 SCI5
Offset
$00C8 $00D0 $00B8 $00C0 $0130 $0138
24
Controlling the SCI

SCIxCR1 (Offset + $02)
LOOPS SCISWAI RSRC M WAKE ILT PE PT
LOOPS (Loop Select bit) 0 means the SCI reciever is disconnected from the RX pin and connect to the TX pin (useful for half-duplex). 1 means TX and RX pins are used (Normal Operation). SCISWAI (SCI Stop in Wait Mode bit) 0 means SCI operates normally in WAIT mode. 1 means SCI is disabled in WAIT mode.
25
Controlling the SCI

RSRC (Receiver Source bit) 0 means the receiver is connected to the transmitter internally. 1 means Reciever is connected to TX pin, if LOOPS =1. M (Data Format Mode bit) 0 means one start bit, eight data bits and one stop bit. 1 means one start bit, nine data bits and one stop bit. WAKE (Wake up Condition bit) 0 means idle line wake up (wake up once the line goes active). 1 means address mark wake up (a 1 in the MSB of a received character is required to wake it up).
26
Controlling the SCI

ILT (Idle Line Type bit) Good for discovering it the line is idle for half duplex modes. 0 means Short Idle detect. 1 means Long idle detect. PE (Parity Enable bit) 0 means parity is disabled. 1 means parity is enabled. PT (Parity Type bit) 0 means even parity. 1 means odd parity.
Controlling the SCI

TIE TCIE RIE ILIE TE RE RWU SBK
TIE (Transmitter Interrupt Enable bit) 0 means interrupt source is disabled. 1 means interrupt source is enabled. TCIE (Transmitter Complete Interrupt Enable bit) 0 means interrupt source is disabled. 1 means interrupt source is enabled. RIE (Receiver Interrupt Enable bit) 0 means interrupt source is disabled. 1 means interrupt source is enabled.
28
Controlling the SCI

ILIE (Idle Line Interrupt Enable bit) 0 means interrupt source is disabled. 1 means interrupt source is enabled. TE (Transmitter Enable bit) 0 means Transmitter is disabled. 1 means Transmitter is enabled. RE (Receiver Enable bit) 0 means Receiver is disabled. 1 means Receiver is enabled.
29
Controlling the SCI

RWU (Receiver Wake Up Bit) 0 means Receiver works normally. 1 means the wake up function is enabled and prevents any further receiver interrupt requests. Hardware can wake the receiver by clearing the RWU bit. SBK (Send Break bit) 0 means no break character. 1 means send break character ( a break character is 10 or 11 logical 0s.
30
Controlling the SCI

SCIxACR1 (Offset + $01) (Requires AMAP bit in SCIxSR2 to be set)
RXEDGIE 0 0 0 0 0 BERRIE BKDIE
RXEDGIE (Receiver Active Edge Interrupt Enable bit) 0 means RXEDGIF interrupt disabled. 1 means RXEDGIF interrupt enabled. BERRIE (Bit Error Interrupt Enable bit) 0 means BERRIF interrupt disabled. 1 means BERRIF interrupt enabled. BKDIE (Break Detect Interrupt Enable bit) 0 means BKDIF interrupt disabled. 1 means BKDIF interrupt enabled.
31
Controlling the SCI

SCIxACR2 (Offset + $02) (Requires AMAP bit in SCIxSR2 to be set)
0 0 0 0 0 BERRM1 BERRM0 BKDFE
BERRM[1:0] (Bit Error Mode) These bit determine the functionality of the Bit Error Detect feature.
BKDFE (Break Detect Feature Enable) 0 means Break Detect Circuit is disabled. 1 means Break Detect Circuit is enabled.
Controlling the SCI

SCIxBDH (Offset + $00)
IREN TNP1 TNP0 SBR12 SBR11 SBR10 SBR9 SBR8
SCIxBDL (Offset + $01)

SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0
IREN (Infrared Enable bit) 0 means IR is disabled. 1 means IR is enabled. TNP[1:0] (Transmitter Narrow Pulse) Set the Narrow Pulse width for IR. SBR[12:0] (SCI Baudrate bits) when IREN = 0, SCI Baudrate = SCI bus clock / (16 * SBR[12:0]) when IREN = 1, SCI Baudrate = SCI bus clock / (32 * SBR[12:1])
33
Status of the SCI

SCIxSR1 (Offset + $04)
TDRE TC RDRF IDLE OR NF FE PE
TDRE (Transmit Data Register Empty ag) 0 means no data was moved from the data register to the shift register. 1 means data has moved to shift register, leaving the data register empty. TC (Transmit Complete ag) 0 means the transmitter is active. 1 means all data has been transmitted, both the data and shift registers are empty.
34
Status of the SCI

RDRF (Receive Data Register Full ag) 0 means the receive data register is empty. 1 means the receive data register has received new data. IDLE (IDLE line ag) 0 means the receiver input is active or hasnt been active since the IDLE ag was cleared . 1 means the receiver input is idle.
35
Status of the SCI

OR (Overrun ag) 0 means no overrun error has occurred. 1 means an overrun error has occurred, due to data no being read for the receive register before it was overwritten. NF (Noise ag) 0 means no noise. 1 means there is noise on the receiver input.
36
Status of the SCI

FE (Framing Error ag) 0 means no framing error occurred. 1 means a framing error occurred (the stop bit wasnt detected properly). PE (Parity Error ag) 0 means no parity error occurred. 1 means there was a parity error.
37
Status of the SCI

AMAP 0 0 TXPOL RXPOL BRK13 TXDIR RAF
AMAP (Alternative Map) 0 means the registers SCIxBDL, SCIxBDH and SCIxCR1 are available. 1 means the registers SCIxASR1, SCIxACR1 and SCIxACR2 are available. TXPOL (Transmitter Polarity) 0 means normal polarity. 1 means inverted polarity.
38
Status of the SCI

RXPOL (Receiver Polarity) 0 means normal polarity. 1 means inverted polarity. BRK13 (Break Transmit Length) 0 means 10 to 11 logical 0s are sent. 1 means 13 to 14 logical 0s are sent.
39
Status of the SCI

TXDIR (Transmitter Pin Data Direction in Single Wire Mode) 0 means input. 1 means output. RAF (Receiver Active Flag) 0 means no reception in progress. 1 means reception in progress.
40
Status of the SCI

SCIxASR1 (Offset + $00)
RXEDGIF 0 0 0 0 BERRV BERRIF BKDIF
RXEDGIF (Receiver Edge Active Input Flag) 0 means no active edge has been detected on the receiver. 1 means an active edge has been detected on the receiver. BERRV (Bit Error Value) 0 means a low input was sampled when a high input was expected. 1 means a high input was sampled when a low input was expected. BERRIF (Bit Error Interrupt Flag) 0 means no mismatch occurred. 1 means a mismatch occurred.
41
Controlling the SCI

SCIxDRH (Offset + $06)
R8 T8 0 0 0 0 0 0
R8 (Receiver Bit 8) When the SCI is used in 9bit mode this is the location for the 9 bit from the receiver. T8 (Transmitter Bit 8) When the SCI is used in 9bit mode this is the location for the 9 bit to be transmitted (this bit must be set prior to setting the lower eight bits).
42
Controlling the SCI

SCIxDRL (Offset + $07)
R7/T7 R6/T6 R5/T5 R4/T4 R3/T3 R2/T2 R1/T1 R0/T0
R[7:0] (Receiver Data Register) Data that has been recieved by the SCI device is stored in this register. T[7:0] (Transmitter Data Register) Data written to this register is transmitted out of the SCI device.
This memory address is a window to two register when reading from this address it refers to the receivers data register. When writing to this address the memory location refers to the transmitters data register.
43
On-Chip RS232 Serial Device
44
Using the SCI Device

Before the SCI can be used it must rst be initialized, so we rstly need to ask some questions. What are the communication characteristics? Baudrate, bit format, parity Single wire (half-duplex) or Two wire (fullduplex) Will my use of the SCI be interrupt driven or will I use polled mode? The control registers need to be set to reect these decisions.
Using the SCI Device

Once the SCI has been initialized, you then want to use it to send or receive data. Since the SCI device is slower than the uP we need to ensure the data register of the SCI is empty before writing a new value to it. This will require us to check the TDRE ag in SCIxSR1, and ensure it is set before writing a second value to register. Also before reading a value from the register we need to ensure that new data has arrived. This means we will have to check that the RDRF ag is set in SCIxSR1 before reading the data register.
46
SCI Example
Entry: LDS #RAMEnd+1 CLI mainLoop: JSR InitSCI LDAB #A JSR PutChar LDAB #$0D JSR PutChar Spin: BRA Spin Serial_Base EQU $00d0 INCLUDE 'Serial.inc' ; initialize the stack pointer ; enable interrupts ; Initialize the SCI ; print a A ; print a newline ('\n') ; while(1); ; Use the auxiliary serial port ; similar to #include<stdio.h> in C
main.asm
SCI Example
;Requires that Serial_base be set in main assembly le ;Register denes SCISR1 EQU Serial_Base + $04 SCISR2 EQU Serial_Base + $05 SCICR1 EQU Serial_Base + $02 SCICR2 EQU Serial_Base + $03 SCIBDH EQU Serial_Base + $00 SCIACR1 EQU Serial_Base + $01 SCIACR2 EQU Serial_Base + $02 SCIDRL EQU Serial_Base + $07 ;Bit denes AMAP EQU $80 TDRE EQU $80 RDFR EQU $20 ;Register Settings SCIControl1 EQU $00 ;8 bit, no parity SCIControl2 EQU $0C Baudrate EQU 52 ;Set Baudrate to 9600
Serial.inc
48
SCI Example
InitSCI: BSET SCISR2,AMAP MOVB #0,SCIACR1 MOVB #0,SCIACR2 BCLR SCISR2,AMAP MOVB #SCIControl1,SCICR1 MOVB #SCIControl2,SCICR2 MOVW #Baudrate,SCIBDH RTS SCISR1,TDRE,* SCIDRL
PutChar: BRCLR STAB RTS
Serial.inc
Interrupt Driven Serial Communication

In situations were you need fast response to serial events, it is best to use the interrupt mechanism. Each serial device has a single interrupt line associated with it. This interrupt can be triggered under four possible conditions: The transmit buffer is empty (TIE) The serial transmission is complete (TCIE), The receive buffer is full (RIE), or The line is idle (ILIE)
50

In situations were you need fast response to serial events, it is best to use the interrupt mechanism. Each serial device has a single interrupt line associated with it. This interrupt can be triggered under four possible conditions: The transmit buffer is empty (TIE) The serial transmission isUsed during(TCIE), complete half The receive buffer is fullduplex or (RIE), operation The line is idle (ILIE)
50

Depending on when you want the interrupt to be triggered you should set the appropriate interrupt enable bit in the SCIxCR2 register. You should also enable the global maskable interrupt subsystem by clearing the I bit in the CCR. Create an ISR and insert the appropriate vector into the vector table location for the serial subsystem you are using.
51
Synchronous Serial Communication

Uses a common clock to synchronize the receiver with the transmitter. Requires a separate line to carry the clock signal. SPI and I2C are two common forms of Synchronous Serial. TX RX Clock GND
Master
Slave
52

The Serial Peripheral Interface is a form of synchronous serial communication. SPI is a high speed interface capable of transmitting and receiving data up to a rate of 12.5 Mbits/second. SPI is an interface that is available on many devices including: MCUs I/O devices Memories devices
53
Synchronous Serial Communication - SPI

SPI is synchronous therefore both the receiver ad transmitter are driven by the same clock source. SPI has a physical interface that consists of four pins: MOSI MISO SCLK SS
Master
MOSI MISO SCLK SS GND
Slave
54

When two SPI capable devices are connected together, they need to synchronize their shift registers, This is done by using the same clock to drive both shift registers. But they both cant generate the clock. One of the SPI devices becomes the master and the other device becomes the slave. The master generates the clock signal and therefore controls the transfer of information on this interface.
Master
MOSI MISO SCLK SS GND
Slave
55
The Role of the Master
The master generates the clock for both itself and the slave devices. The master controls when the slave can send and receive information. Just does what the master tells it to do...
The Role of the Slave
56
Single Buffered
The data register is the actual shift register responsible for serial conversion. Has a single status ag to show when a transmission is complete.
57

Single Buffered Example
Master
Shift Register Data Register Clock Source
MISO MOSI
Slave
Shift Register Data Register
SCLK SS
The connection between the master and slave SPI devices


Master
Single MISO Buffered

MOSI
Slave
Clock Source
SCLK SS


Master
MISO MOSI
Slave 00010011
10110010
Clock Source SCLK SS


Master 00010011
MISO MOSI
Slave 10110010
00010011
Clock Source Transmission Complete Flag The connection SCLK SS
10110010
between the master and slave SPI devices

59

Single Buffered Example (a second time)
Master
MISO MOSI
Slave 00010011
10110010
Clock Source SCLK SS


Single Buffered Example (a second time)
Master 00010011
MISO MOSI
Slave 10110010
00010011
Clock Source Transmission Complete Flag The connection SCLK SS
10110010

60
Double Buffered
There are two data registers, one writing and one for reading. When a transmission is complete the data in the shift register is moved in the receive data register and the data from the transmit data register is copied into the shift register. Has two ags; one to show when a transmission is complete, a second ag to show if the transmit data register can be written to.
61

Double Buffered Example
Master
MISO MOSI
Slave
Shift Register
Shift Register
Data Register
Data Register
SCLK SS


Master
MISO Double Buffered MOSI
Slave
Shift Register
Shift Register
Data Register
Data Register
SCLK SS


Master
MISO MOSI
Slave
Shift Register
Shift Register
Data Register
Data Register
SCLK SS


Master
Shift Register
MISO MOSI
Slave
Shift Register
00010011
Data Register Data Register
Clock Source
SCLK SS


Master
Shift Register
MISO MOSI
Slave 00010011
Data Register
Clock Data Source Register Empty Flag
SCLK SS


Master
Shift Register
MISO MOSI
Slave
Shift Register
00010011
Data Register
10110010
Data Register
Clock Source Transmission Complete The Flag connection
SCLK SS

63

Master
Shift Register
MISO MOSI
Slave
Shift Register
00010011
Clock Source
SCLK SS


Master
Shift Register
MISO MOSI
Slave
Shift Register
Data Register
Data Register
Clock Source
SCLK SS


Double Buffered Example (a second time)
Master
Shift Register
MISO MOSI
Slave
Shift Register
00010011
Clock Source
SCLK SS


Master
Shift Register
MISO MOSI
Slave 00010011
Data Register
Clock Data Source Register Empty Flag
SCLK SS


Master
Shift Register
MISO MOSI
Slave
Shift Register
00010011
Data Register
10110010
Data Register
Clock Source Transmission Complete The Flag connection
SCLK SS

64

Master
Shift Register
MISO MOSI
Slave
Shift Register
00010011
Clock Source
SCLK SS


Master
Shift Register
MISO MOSI
Slave
Shift Register
Data Register
Data Register
Clock Source
SCLK SS


The MC9S12XDP512s SPI Subsystem
The three SPI subsystems provided on the MC9S12XDP512 have the following features:

Double buffered, Capable of a maximum SPI clock speed of 4MHz at the default system clock of 8MHz, Master or Slave modes, Slave Select Output Serial clock, with programmable speed, phase and polarity Bidirectional mode
65

All interaction with the SPIs is done via there I/O register set. (Note that the x in the register name should be replaced with device number [0-2])
SPIxCR1 SPIxSR SPIxCR2 SPIxDR SPIxBR
66
Controlling the SPI

SPIxCR1
SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE
SPIE (SPI Interrupt Enable) : 0 means SPI Interrupts are inhibited. 1 means hardware interrupt is requested each time the SPIF or MODF status ag is set. SPE (SPI System Enable): 0 means SPI internal hardware is initialized and SPI system is in a low power disabled state. 1 means SPI is enabled and IO pins are dedicated to the SPI function.
67
Controlling the SPI

SPIxCR1
SPTIE (SPI Transmit Interrupt Enable bit): 0 means SPTEF interrupts are disabled. 1 means SPTEF interrupts are enabled. MSTR (SPI Master/Slave Mode Select) : 0 means Slave Mode 1 means Master Mode
68
Controlling the SPI

SPIxCR1
CPOL, CPHA (SPI Clock Polarity, Clock Phase): These two bits are used to specify the clock format to be used in SPI operations. When the clock polarity bit (CPOL) is cleared and data is not being transmitted the SCLK line idles low. When CPOL is set the SCLK line idles high. SSOE (Slave Select Output Enable): The SS output feature is enabled only in master mode by asserting the SSOE and DDS7.
69
Controlling the SPI

SPIxCR1
LSBFE (SPI LSB First Enable bit): 0 = Data is transferred most-signicant bit (MSB) rst. 1 = Data is transferred least-signicant bit (LSB) rst. The setting of this bit does not alter the location of the MSB in the data register.
70
Controlling the SPI

SPIxCR1
SPI Clock Format
SPI Clock Format 0 CPHA=0
SPI Clock Format 1 CPHA=1
71
Controlling the SPI

SPIxCR2
0 0 0
MODFEN BIDIROE
SPISWAI
SPC0
MODFEN (Mode Fault Enable bit): This bit allows the MODF failure to be detected. If the SPI is in master mode and MODFEN is cleared, then the SS port pin is not used by the SPI. In slave mode, the SS is available only as an input regardless of the value of MODFEN. 0 means SS port pin is not used by the SPI device. 1 means SS port pin with MODF feature.
72
Controlling the SPI

SPIxCR2
0 0 0
MODFEN BIDIROE
SPISWAI
SPC0
BIDIROE (Output Enable in Bidirectional Mode of Operation): This bit controls the operation of the output buffer when bidirectional mode is set (SPC0=1). 0 means output buffer is disabled. 1 means output buffer enabled.
73
Controlling the SPI

SPIxCR2
0 0 0
MODFEN BIDIROE
SPISWAI
SPC0
SPISWAI (SPI Stop in Wait mode): This bit controls the behaviour of the SPI device when in WAIT mode. 0 means SPI clock operates normally. 1 means SPI clock is disabled.
74
Controlling the SPI

SPIxCR2
0 0 0
MODFEN BIDIROE
SPISWAI
SPC0
SPC0 (Serial Pin Control bit 0): This bit enables bidirectional pin conguration.
75
Controlling the SPI

SPIxBR
0 SPPR2 SPPR1 SPPR0 0 SPR2 SPR1 SPR0
SPPR[2:0] (SPI Baud Rate Preselection bits): These bits specify the baud rate. SPR[2:0] (SPI Baud Rate Selection bits): These bits also specify the baud rate. Baud rate divisor = (SPPR + 1) 2 (SPR+1) Baudrate = Bus Clock / Baud rate divisor
76
Controlling the SPI

SPIxSR
SPIF 0 SPTEF MODF 0 0 0 0
SPIF (SPI Interrupt Request Flag): SPIF is set after the eighth SCK clock cycle in a data transfer, and it is cleared by reading the SPIxSR register (with SPIF set) followed by an access (read or write) to the SPIxDR data register. SPTEF (SPI Transmit Empty Interrupt Flag): This bit indicates if the transmit data register is empty. 0 means register is not empty. 1 means it is empty.
77
Controlling the SPI

SPIxSR
SPIF 0 SPTEF MODF 0 0 0 0
MODF SPI Mode Error Interrupt Status Flag: This bit is set automatically by SPI hardware, if the MSTR control bit is set and the slave select input pin becomes 0. This condition is not permitted in normal operation. In the case of SPI0 where DDRS bit 7 is set, the PS7 pin is a general-purpose output pin or SS output pin rather than being dedicated as the SS input input for the SPI system. In this special case, the mode fault function is inhibited and MODF remains cleared. This ag is cleared automatically by a read of the SPIxSR (with MODF set) followed by a write to the SPIxCR1 register.
78
Controlling the SPI
SPIxDR
SPD7
SPD6
SPD5
SPD4
SPD3
SPD2
SPD1
SPD0
SPD7-0 SPI Data: Data written to this register is serially transmitted via the SPI port, data received by the SPI port is made available through this register also. Data written to this register will not overwrite data received by the SPI port.
79
Block Diagram of the Serial Peripheral Interface

Using the SPI device
When using the SPI subsystem, you need to ask yourself some questions:

Who is the Master, who is the slave? What is the speed of communication? What is the clock format? What size is the slaves buffer?
81
Example
Application example were two MC9S12XDP512s are connected together.
MOSI MISO SCLK SS

Example
Master Code
SPIF: SPTEF SPE: MSTR: SS: SMASK SPISETUP ... MainLoop: EQU %10000000 EQU %00100000 EQU %01000000 EQU %00010000 EQU %10000000 EQU %11100000 EQU MSTR|SPE
Spin: INITSPI:
JSR BSET BRCLR MOVB BRCLR LDAB BCLR BRA
INITSPI PORTS,SS SPI0SR,SPTEF,* #43,SPI0DR SPI0SR,SPIF,* SPI0DR PORTS,SS Spin
; Wait until Data register is empty ; Write $43 to SPI Data Register ; Wait until Data is shifted ; Reset SPIF ;Select Slave HC912
MOVB MOVB MOVB MOVB RTS
#SMASK,DDRS #SPISETUP,SPI0CR1 #0,SPI0CR2 #$00,SPI0BR
;Set Port S bits 7-5 for output. ;Enable SPI in master mode ;Normal SPI mode ;Set up the clock rate to be max.
83
Example
Slave Code
SPIF: EQU %10000000 SPE: EQU %01000000 SS: EQU %10000000 SMASK EQU %000100000 SPISETUP EQU SPE ... MainLoop: JSR INITSPI BRCLR SPI0SR,SPIF,* BRSET PORTS,SS,* LDAA SPI0DR Spin: BRA Spin INITSPI:
;Select Slave HC912
MOVB MOVB MOVB MOVB RTS
#SMASK,DDRS #SPISETUP,SPI0CR1 #0,SPI0CR2 #$00,SPI0BR
;Set Port S bits 7-5 for input. ;Enable SPI in slave mode ;Normal SPI mode ;No effect, since it is a slave.
84

The popularity of SPI is increasing, and it becoming a standard feature on all MCUs. Many peripherals are also SPI enabled, including:
Digital-to-Analog Converters Analog-to-Digital Converters LCD Displays RAM / ROM chips Protocol Conversion Devices (SPI to RS232) And many more
85
Need Further Assistance?

Ask your Demonstrator, Post a question on the Forum, Email the Convener, or Make an appointment.

Topic08 Introduction To The Serial Interfaces On The Freescale MC9S12X

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Topic08 Introduction To The Serial Interfaces On The Freescale MC9S12X

Uploaded by

Copyright:

Available Formats

Topic Video 08

Serial Subsystems: Clocked or Unclocked...

Thursday, 22 October 2009

Thursday, 22 October 2009

Thursday, 22 October 2009

Thursday, 22 October 2009

Thursday, 22 October 2009

Thursday, 22 October 2009

Thursday, 22 October 2009

10000010 01100100 Transmitter

Thursday, 22 October 2009

Thursday, 22 October 2009

Thursday, 22 October 2009

Thursday, 22 October 2009

Thursday, 22 October 2009

Thursday, 22 October 2009

Thursday, 22 October 2009

Thursday, 22 October 2009

Thursday, 22 October 2009

Thursday, 22 October 2009

Thursday, 22 October 2009

Thursday, 22 October 2009

Thursday, 22 October 2009

01100100 10000010 Receiver

Thursday, 22 October 2009

Thursday, 22 October 2009

Thursday, 22 October 2009

Thursday, 22 October 2009

On-Chip Serial Devices

Thursday, 22 October 2009

Asynchronous Serial Communication

Thursday, 22 October 2009

Asynchronous Serial Communication

Asynchronous Serial Communication

Thursday, 22 October 2009

Asynchronous Serial Communication

Thursday, 22 October 2009

Asynchronous Serial Communication

Thursday, 22 October 2009

Asynchronous Serial Communication

Asynchronous Serial Communication

Even Parity bit

Asynchronous Serial Communication

Even Parity bit

Asynchronous Serial Communication

Asynchronous Serial Communication

Odd Parity bit

Asynchronous Serial Communication

Odd Parity bit

Asynchronous Serial Communication

Thursday, 22 October 2009

Asynchronous Serial Communication

Full duplex or Half duplex?

Asynchronous Serial Communication

Full duplex or Half duplex?

Thursday, 22 October 2009

Asynchronous Serial Communication

Full duplex or Half duplex?

Thursday, 22 October 2009

Asynchronous Serial Communication

Full duplex or Half duplex?

Thursday, 22 October 2009

provided through a number of different ports on the MC9S12XDP512.