3472

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 8, AUGUST 2012

An Improved Pulse Width Modulation Method for Chopper-Cell-Based Modular Multilevel Converters
Zixin Li, Member, IEEE, Ping Wang, Haibin Zhu, Zunfang Chu, and Yaohua Li
AbstractIn this paper, an improved pulse width modulation (PWM) method for chopper-cell (or half-bridge)- based modular multilevel converters (MMCs) is proposed. This method can generate an output voltage with maximally 2 N+1 (where N is the number of submodules in the upper or lower arm of MMC) levels, which is as great as that of the carrier-phase-shifted PWM (CPSPWM) method. However, no phase-shifted carrier is needed. Compared with the existing submodule unied pulse width modulated (SUPWM) method, the level number of the output voltage is almost doubled and the height of the step in the staircase voltage is reduced by 50%. Meanwhile, the equivalent switching frequency in the output voltage is twice that of the conventional SUPWM method. All these features lead to much reduced harmonic content in the output voltage. What is more, the voltages of the submodule capacitors can be well balanced without any close-loop voltage balancing controllers which are mandatory in the CPSPWM schemes. Simulation and experimental results on a MMC-based inverter show validity of the proposed method. Index TermsModular multilevel converter (MMC), pulse width modulation (PWM), voltage balancing.

I. INTRODUCTION

ONSTRUCTING power converters that are suitable for medium to high voltage range applications is a great challenge for power electronics. To achieve this goal, many multilevel converters have been proposed. Among the existing circuits, the cascaded, diode-clamped, and capacitor-clamped topologies are usually recognized as the three most common types [1][5]. With regard to the cascaded topologies, for example, the cascaded H-bridge converters are generally modular, but they cannot be operated as back-to-back converters without the help of transformers. The diode-/capacitor-clamped topologies can be employed as inverters, rectiers, or back-to-back converters. However, they are essentially not modular and are quite complex as the number of the output voltage level increases. Recently, the modular multilevel converter (MMC), which is highly suitable for medium to high voltage applications, has attracted much research interest. Compared with the existing multilevel converters, one of the most desirable advantages offered by MMC may be its ability to process both active power

and reactive power with its terminals directly connected to directly high-voltage networks. This means an MMC can be used as a high-voltage inverter, rectier, or four-quadrant converter, without bulky transformers. Actually, many academic papers have been published on MMC [5][20] in recent years. These papers mainly focus on modeling, pulse width modulation (PWM), voltage balancing, digital control, loss analysis, low-frequency operation, simulation techniques, and so forth. As to the PWM methods for MMC with chopper-cell (or halfbridge) as the submodules, there exist generally two types of methods. They include the carrier-phase-shifted PWM (CPSPWM) method in [10] and [11] and the submodules unied pulse width modulated (SUPWM) method in [12][15]. The SUPWM method can balance the submodule capacitor voltages by sorting and selecting the different submodules without close-loop voltage balancing controllers. Meanwhile, this method can ensure that N submodule capacitors are connected to the dc-link in each phase all the time. This characteristic of the SUPWM method is attractive because it will lead to small buffer inductors. On the other hand, the CPSPWM method modulates each submodule separately, so it cannot guarantee that N submodule capacitors are selected all the time. If CPSPWM is adopted, the buffer inductors will be larger than that with the SUPWM method because high-voltage pulses containing fundamental component will be imposed on them. What is more, dedicated controllers for capacitor voltage balancing are mandatory with the CPSPWM method, which is not an easy task for the processors when the number of the submodules is great. Anyway, the CPSPWM method can produce greater number of voltage levels than that of the SUPWM method, leading to much reduced harmonic content. To improve the performance of the SUPWM method, this paper presents an improved method with which the number of voltage levels can be as great as that with the CPSPWM. Meanwhile, the height of the staircase output voltage can be reduced by 50% compared with the existing SUPWM method. Unlike the CPSPWM method, the proposed approach does not need any close-loop voltage balancing controller. Simulation and experimental results have both been presented to justify the presented method. II. CONVENTIONAL SUPWM METHOD FOR MMC Fig. 1 shows one phase of MMC as an inverter where Udc is the dc-link voltage, SMU 1 SMU N and SML 1 SML N are the N submodules in the upper and lower arms, respectively, LU and LL are the two buffer inductors in the upper and lower arms, uU and iU are the voltage and current of the upper arm, uL and iL are the voltage and current of the lower arm. The two

Manuscript received July 12, 2011; revised November 26, 2011; accepted February 5, 2012. Date of current version April 20, 2012. Recommended for publication by Associate Editor A. Mertens. The authors are with the Institute of Electrical Engineering, Chinese Academy of Sciences, Beijing 100190, China (e-mail: lzx@mail.iee.ac.cn; wangping@mail.iee.ac.cn; hedera@mail.iee.ac.cn; chuzf@mail.iee.ac.cn; yhli@mail.iee.ac.cn). Color versions of one or more of the gures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identier 10.1109/TPEL.2012.2187800

0885-8993/$31.00 2012 IEEE

LI et al.: AN IMPROVED PULSE WIDTH MODULATION METHOD FOR CHOPPER-CELL-BASED MODULAR MULTILEVEL CONVERTERS

3473

where m(0 m 1) is the modulation index and is the angular frequency. In Fig. 1, if S1 is on and S2 is off, the capacitor of this submodule will be connected in the arm irrespective of the direction of iSM and this state of the submodule is dened as IN. If S2 is on and S1 is off, the capacitor of this submodule will be bypassed and out of the arm irrespective of the direction of iSM and this state of the submodule is dened as OUT. With the conventional SUPWM method, there will always be N submodule capacitors selected as IN. Therefore, the following equation must be satised: uL + uU = Udc . (5)

Fig. 1.

One arm of MMC-based inverter.

buffer inductors can be selected as separate ones or coupled (center-tapped) ones. The use of coupled inductors will result in considerable reductions in size, weight, and cost to the magnetic core [5], [10]. Therefore, this paper adopts coupled inductors. Taking the neutral point n of the dc link as the reference point, the voltage equations can be written as LU diU + M diL = uwn uan dt dt (1) L diL + M diU = u u L an zn dt dt where M is the mutual inductance of LU and LL . Suppose the two inductors are closely coupled and the leakage inductance can be ignored, i.e., LU = LL = M. From (1) and according to Kirchhoffs current law, one can obtain iU = iL + ia . From (1) and (2), the output voltage can be expressed as (Udc /2 uU ) + (uL Udc /2) uwn + uzn = 2 2 uL uU = . (3) 2 In the following analysis, all the voltages of the submodule capacitors are supposed to be well balanced, i.e., USM = Udc /N. As the output voltage of each submodule has two levels, i.e., 0 and USM , uU and uL will both have N+1 voltage levels. It is seen from (3) that uan may have maximally 2N+1 voltage levels with the minimum voltage step of USM /2. Generally, the reference voltage for one phase of MMC can be expressed as uan = uan
ref

From (3) to (5), the reference voltage for the upper and lower arms can be expressed as uU ref = Udc uan ref = Udc [1 m cos(t)] 2 2 (6) Udc Udc u + uan ref = [1 + m cos(t)]. L ref = 2 2 To understand the SUPWM method, the upper arm will be taken as an example. Given that USM = Udc /N and suppose that K1 USM < uU ref < (K1 +1)USM where K1 is a positive integer. To generate a voltage of uU at certain time, K1 submodule capacitors (with voltage of USM ) is not enough, but K1 +1 submodule capacitors will be surplus. Hence, K1 submodules should be selected as IN to provide the major part of uU ref rst. Then, one more submodule should be pulse width modulated to generate the left voltage. Obviously, K1 can be calculated as K1 = int uU ref (Udc /N ) (7)

in which the function int(x) will get the integer part of x. In the meantime, NK1 1 submodules will be selected as OUT permanently and the last submodule will be switching or pulse width modulated within one Tc . The reference voltage for this switching submodule can be calculated as uU
SW ref

= uU

ref

K1

Udc N

(8)

(2)

Udc m cos(t) 2

(4)

This reference voltage is obtained by considering the staircase waveform of uan and uU [13]. To balance the voltages of the submodule capacitors, the N submodules in the upper arm are rst sorted in ascending order (with series number from 1 to N) according to their capacitor voltages. Then, the submodules with series number from 1 to K1 will be selected as IN if iU > 0 (i.e., charging of the selected submodule capacitors) while the submodules with series number from NK1 +1 to N will be selected as IN if iU < 0 (i.e., discharging of the selected submodule capacitors) [13]. The states of the lower arm submodules can be determined in a similar manner. Finally, there will always be N submodules in IN state at any time. Obviously, the submodules are unied modulated. In practice, this SUPWM method can be realized by applying 180 phase-shifted triangle carriers to the upper and lower arms. Fig. 2 shows an example where all the submodules in the upper take C1 and those in the lower arm use C2 as the carrier for PWM. The reference voltage for the switching submodule in the upper arm is calculated by (8). To ensue

3474

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 8, AUGUST 2012

close-loop controller and almost zero voltage stress on the buffer inductor, but the level number of the output voltage is much less than that with the CPSPWM method [5], [10]. This section will present an improved SUPWM method. With the presented method, the number of output voltage level can be as great as that with the CPSPWM method, but still no close-loop voltage balancing controller is needed. The improved method in this paper can be illustrated by Fig. 3 in which the submodules in the upper and lower arms all use the same carrier, i.e., C1 and C2 are of the same phase. The submodule selection algorithm and the reference voltages calculation for the switching submodules in the upper and lower arms are the same as those of the conventional SUPWM method. However, this little change in the carrier phase will lead to substantially increased voltage level. With the conventional method, the number of IN state submodules in the upper arm will be K1 or K1 + 1 while that in the lower arm will be N K1 1 or N K1 . As the sum of the IN state submodules in the upper and lower arms is N, the voltages of the upper and lower arms can be expressed as uU uL or
Fig. 2. Modulation of the switching submodules in the upper and lower arms with the conventional SUPWM method.
conventional conventional

= K1 USM = (N K1 )USM

(11)

uU uL

conventional conventional

= (K1 + 1)USM = (N K1 1)USM .

(12)

From (3), the output voltage uan can be expressed as N submodules selected as IN state, the voltage reference for the switching submodule in the lower arm can be expressed as uL
SW ref

uan or uan

conventional

uL uU = 2

N K1 2

USM

(13)

= USM uU

SW ref .

(9)

By using the reference voltages from (8) and (9) as shown in Fig. 2, the state of the switching submodules in the upper and lower arms will always be complementary. The sum of the output voltages of the two switching submodules will always be USM , just like one submodule selected as IN state. Meanwhile, the numbers of the IN state submodules in the upper and lower arms are K1 and N 1 K1 , respectively. Hence, there will always be N submodules selected as IN. Besides, the voltage on the buffer inductors will always be zero as shown in Fig. 2. It is also clear from Fig. 2 that the height of the staircase in uan is USM and uan switches once within one Tc , i.e., the equivalent switching frequency of uan is equal to the carrier frequency. Whereas, from (3) and (5), one can obtain uan = 2uL Udc Udc 2uU = . 2 2 (10)

conventional

uL uU = 2

N K1 1 USM . (14) 2

So, the staircase output voltage uan will alternate between the two levels within one Tc as expressed in (13) and (14). In the meantime, the height of the step in the output voltage is USM . A. Mechanism of Increasing Output Voltage Level With the improved method, as shown in Fig. 3, one can see that the number of IN state submodules in the upper arm will be K1 or K1 + 1 while that in the lower arm will be N K1 1 or N K1 . However, the number of IN state submodules will not be constantly N as with the conventional method, but will be N 1, N or N + 1. The voltages of the upper and lower arms can be expressed as four cases. The rst case is from t0 to t1 or from t4 to t5 in Fig. 3(a) or (b) uU uL
im proved im proved

Actually, uU and uL both have maximally N+1 voltage levels (0, USM , 2USM , . . ., (N1)USM , NUSM ). From (10), it is clear that the output voltage of the MMC-based inverter will also have maximally N+1 levels with the conventional SUPWM. III. IMPROVED SUPWM METHOD As analyzed earlier, it is clear that the SUPWM can balance the capacitor voltages of the submodules with no dedicated

= K1 USM = (N K1 1)USM .

(15)

The second case is from t1 to t2 or from t3 to t4 in Fig. 3(a) uU uL

im proved im proved

= (K1 + 1)USM = (N K1 1)USM .

(16)

LI et al.: AN IMPROVED PULSE WIDTH MODULATION METHOD FOR CHOPPER-CELL-BASED MODULAR MULTILEVEL CONVERTERS

3475

Fig. 3.

Modulation of the switching submodules in the upper and lower arms with the proposed method. (a) uU

SW r ef

> US M /2. (b) uU

S W re f

< US M /2.

The third case is from t1 to t2 or from t3 to t4 in Fig. 3(b) uU uL

im proved im proved

= K1 USM = (N K1 )USM .

(17)

The second case is from t1 to t2 or from t3 to t4 in Fig. 3(a) or (b) uU uL

im proved im proved

= (K1 + 1)USM = (N K1 )USM .

(18)

From (3), the output voltage uan can now be expressed as uan or uan or uan or uan
im proved im proved im proved im proved

uL uU = 2 uL uU = 2 uL uU = 2

N 1 K1 2 2

USM

(19)

N K1 1 USM 2 N K1 2 N 1 K1 2 2

(20)

USM

(21)

uL uU = 2

USM .

(22)

Comparing (13)(14) and (19)(22), one can see that the improved method introduces a new voltage level ((N/2)K1 1/2)USM , besides the two adjacent voltage levels ((N/2) K1 )USM and ((N/2)K1 1)USM in the conventional method. Namely, the improved method inserts a new voltage level to each pair of adjacent voltage levels in the conventional method. As the conventional method can output maximally N+1 levels, the improved method can introduce maximally N new levels. Therefore, the proposed method will have 2N+1 levels in the output voltage, which is almost double that of the conventional method. It is also clear from Fig. 3 that the height of the staircase in uan is USM /2, meaning 50% reduction compared with the conventional method as shown in Fig. 2. Meanwhile, uan switches twice within one Tc in Fig. 3, i.e., the equivalent switching frequency of uan is twice the carrier frequency, which means a 100% increase in the equivalent switching frequency compared with the conventional method. The reduced step height together with the increased equivalent switching frequency will lead to considerable suppression of voltage harmonics and dv/dt caused electromagnetic interference noise. It should be pointed out that the increased voltage levels can be obtained thanks to the coupled inductors. As shown in (3), the coupled inductors in fact act as an adder/subtracter of the upper and lower arm voltages. Thus, an extra voltage level can be

3476

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 8, AUGUST 2012

TABLE I COMPARISON OF THE CONVENTIONAL AND THE IMPROVED PWM METHOD

produced. If the buffer inductors are separate, the 2N+1 levels cannot be obtained clearly for the inuence of the circulating current between the dc link and the arms [5]. B. Voltage Stress on the Buffer Inductors Besides the level number difference, the proposed method will also affect the voltage on the buffer inductors. From Fig. 3(a) and (b) and (9), the average voltage on the buffer inductors can be calculated as uwz
ave

= = =

1 Tc

t5

uwz dt
t0

USM [(t1 t0 ) + (t2 t3 ) + (t5 t4 )] Tc uU SW ref uL SW ref USM Tc Tc Tc Tc USM USM

SW ref

= USM uU

uL

SW ref

= 0.

(23)
Fig. 4. Setup of the single-phase inverter for simulation and experiment.

Equation (23) shows that the average voltage on the buffer inductors within one Tc is zero with the proposed method. This means no dc or low-frequency voltage exist, which is very desirable for design of the inductor cores. C. Inuences on Voltage Balancing of the Submodules The improved method actually does not inuence the selection of IN or OUT state submodules as calculated by the conventional SUPWM method. Only the phase of the carrier for the submodules in the lower arm is changed. Therefore, the voltage balancing algorithm in the SUPWM method is still valid with the improved scheme and no close-loop voltage balancing controller is needed. To summarize, the conventional and the improved SUPWM methods are compared with the results listed in Table I. Obviously, the voltage on the buffer inductors will be USM , 0 or USM with the improved method while that with the conventional method is zero ideally. The voltage stress on the buffer inductors seems larger with the proposed approach. However, the power switches are not ideal and dead time must be added to the gating signals in reality. If the dead time effect is considered, highvoltage narrow-pulses will be imposed on the buffer inductors

TABLE II PARAMETERS OF THE MMC-BASED SINGLE-PHASE INVERTER FOR SIMULATION

even with the conventional SUPWM method [20]. Therefore, the improved method will not increase the voltage stress on the buffer inductors.

LI et al.: AN IMPROVED PULSE WIDTH MODULATION METHOD FOR CHOPPER-CELL-BASED MODULAR MULTILEVEL CONVERTERS

3477

Fig. 5. Output voltage ua n (black line) and load current ilo a d 50 (red line). The conventional SUPWM method is adopted when t < 0.06 s and the improved method is adopted when t 0.06 s.

Fig. 6. 0.06 s.

Voltage across the coupled inductors uw z . The conventional SUPWM method is adopted when t < 0.06 s and the improved method is adopted when t

With the improved method, the level number of the output voltage can be as great as that with the CPSPWM method. The differences between the two methods are also apparent. First, the CPSPWM method modulates each submodule separately with 2N phase-shifted carriers while with the improved method the carriers for the submodules are all the same. The 2N+1 voltage levels are obtained by the phase-shifted carriers in the CPSPWM, but the improved method achieves this goal via the coupled inductors. Second, with the CPSPWM method, dedicated capacitor voltage balancing controllers for each submodule are mandatory [10], [11] while the improved method does not need any close-loop controller for balancing submodule capacitor voltages. IV. SIMULATION AND EXPERIMENTAL RESULTS In order to verify the validity of the proposed method in this paper, an MMC-based single-phase inverter is taken as the test example. The setup of the inverter for simulation and experiment is shown in Fig. 4. Computer simulation is carried out rst in MATLAB/Simulink software and the parameters are listed in Table II. Figs. 58 show the simulation results. It is seen from Fig. 5 that the output voltage level increases from 6 to 11 after 0.06 s and the height of the step in the output voltage reduces from

600 to 300 V. As a result, the ripple current in the load current has been substantially suppressed. It is clear from Fig. 6 that the voltage across the coupled inductors uwz is around zero with the conventional method while narrow pulses appear in uwz with the improved method. The amplitude of the pulses is 600 V or USM as summarized in Table I. The spectrum of uan with both methods is also displayed in Fig. 7. Obviously, the lowest harmonics is around the carrier frequency fcarrier with the conventional method as shown in Fig. 7(a) while around the 2fcarrier with the improved method as shown in Fig. 7(b). These results match the theoretical analyses well. With the improved method as shown in Fig. 7(b), the harmonic of the highest amplitude at fcarrier with the conventional method in Fig. 7(a) is eliminated although the harmonics around fcarrier exist. This is because the voltages of the submodule capacitors are not constant as ac currents ow through them [6] and subharmonics are introduced to uan . Anyway, the total harmonic distortion (THD) of uan decreases from 24.76% to 13.27% with the improved method, meaning substantial improvement in the output voltage quality. What is more, the improved method has almost no inuence on the balancing of the submodule capacitor voltages which is manifested in Fig. 8. Note that no close-loop voltage balancing controllers are adopted. Obviously, the conventional and the

3478

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 8, AUGUST 2012

Fig. 7.

Spectrum and THD of the output voltage ua n . (a) With the conventional method. (b) With the improved method.

Fig. 8. Capacitor voltages of the submodules in the upper and lower arm. The conventional SUPWM method is adopted when t < 0.06 s and the improved method is adopted when t 0.06 s.

improved method have almost the same performance in terms of submodule capacitor voltage balancing. Experiments on an MMC-based inverter are also carried out to test the improved method. The parameters for experiment are listed in Table III. The photo of the inverter is shown in Fig. 9 and uses insulated gate bipolar transistor as the power switch. The main modulation and control algorithms are implemented in DSP+FPGA and the voltages of the submodule capacitors are sampled via optical bers. The dc-link voltage is obtained via a three-phase diode rectier connected to the secondary side of a three-phase autotransformer. Due to the limitations of the

autotransformer and dc-link capacitors in the laboratory, the dc-link voltage can be maximally around 500 V. Figs. 1012 show the experimental results with the conventional SUPWM method. As the modulation index is 0.96, the output voltage has 11 levels and the height of the step is about 50 V as displayed in Fig. 10. Figs. 1315 display the results with the propose method in this paper. Obviously, the level number of the output voltage is increased to 21 with the step height reduced to 25 V which is shown in Fig. 13. The ripple or harmonic component in the load current iload is also apparently reduced by the improved method as shown in Figs. 10 and 13. The

LI et al.: AN IMPROVED PULSE WIDTH MODULATION METHOD FOR CHOPPER-CELL-BASED MODULAR MULTILEVEL CONVERTERS

3479

TABLE III PARAMETERS OF THE MMC-BASED SINGLE-PHASE INVERTER FOR EXPERIMENT

Fig. 10. Output voltage ua n (yellow line, 200 V/div), load current ilo a d (pink line, 5 A/div), and the voltage across the buffer inductors uw z (green line, 10 V/div) with the conventional method.

Fig. 11. Spectrum and THD of the output voltage ua n with the conventional method.

Fig. 9.

Photo of the MMC-based inverter for experiment.

voltage across the buffer inductors uwz is obviously around zero with the conventional method as shown in Fig. 10 while that becomes pulses with the amplitude of 50 V, which matches the theoretical analysis as shown in Fig. 3(a) and (b) well. The spectrum of the output voltage uan is measured by a Fluke 43B Power Quality Analyzer. Comparing Figs. 11 and 14, one can see that the improved method can reduce the harmonics in the output voltage, especially those around the carrier frequency, i.e., 2 kHz or 40th harmonic of 50 Hz. Please note that the measured THD of the output voltage is lower than the simulation

Fig. 12. Capacitor voltages of SMU4 (green line, 20 V/div) and SML4 (yellow line, 20 V/div) and the load current ilo a d (pink line, 2 A/div) with the conventional method.

3480

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 8, AUGUST 2012

results. This is because harmonics higher than 51st cannot be measured by the Fluke 43B Power Quality Analyzer. The voltages of the submodules are measured by differential probes. As there are not enough probes, only the two capacitor voltages of SMU 4 and SML 4 are displayed. It is clear that the capacitor voltages of the submodules are well balanced in both cases that are manifested in Figs. 12 and 15. V. CONCLUSION This paper proposed an improved PWM method for choppercell based MMCs. The proposed method can output maximally 2N+1 voltage levels in the output voltage, which is almost double that with the conventional SUPWM method and as great as that with the CPSPWM method. The equivalent switching frequency of the output voltage is doubled compared with conventional method. The submodule capacitor voltages can be well balanced with the presented method, but no close-loop voltage balancing controllers are necessary in the CPSPWM method. The average voltage on the buffer inductors can also be kept at zero within each carrier period. Simulation and experimental results both proved the validity of this method.

Fig. 13. Output voltage ua n (yellow line, 200 V/div), load current ilo a d (pink line, 5 A/div), and the voltage across the buffer inductors uw z (green line, 10 V/div) with the improved method.

REFERENCES
[1] J. Rodriguez, J.-S. Lai, and F. Z. Peng, Multilevel inverters: A survey of topologies, controls, and applications, IEEE Trans. Ind. Electron., vol. 49, no. 4, pp. 724738, Aug. 2002. [2] M. Malinowski, K. Gopakumar, J. Rodriguez, and M. A. Perez, A survey on cascaded multilevel inverters, IEEE Trans. Ind. Electron., vol. 57, no. 7, pp. 21972206, Jul. 2010. [3] J. Rodriguez, S. Bernet, P. K. Steimer, and I. E. Lizama, A survey on neutral-point-clamped inverters, IEEE Trans. Ind. Electron., vol. 57, no. 7, pp. 22192230, Jul. 2010. [4] S. Kouro, M. Malinowski, K. Gopakumar, J. Pou, L. G. Franquelo, B. Wu, J. Rodriguez, M. A. P rez, and J. I. Leon, Recent advances and industrial e applications of multilevel converters, IEEE Trans. Ind. Electron., vol. 57, no. 8, pp. 25532580, Aug. 2010. [5] H. Akagi, Classication, terminology, and application of the modular multilevel cascade converter (MMCC), IEEE Trans. Power Electron., vol. 26, no. 11, pp. 31193130, Nov. 2011. [6] A. Lesnicar and R. Marquardt, A new modular voltage source inverter topology, presented at the Conf. Rec. Eur. Power Electron., Toulouse, France, 2003. [7] A. Lesnicar and R. Marquardt, An innovative modular multilevel converter topology suitable for a wide power range, presented at the Conf. Rec. 2003 IEEE Bologna PowerTech Conf., Bologna, Italy, Jun. 2326, 2003. [8] M. Glinka, Prototype of multiphase modular-multilevel-converter with 2MW power rating and 17-level-output-voltage, in Proc. IEEE Power Electron. Spec. Conf. (PESC), 2004, pp. 25722576. [9] M. Glinka and R. Marquardt, A new AC/AC multilevel converter family, IEEE Trans. Ind. Electron., vol. 52, no. 3, pp. 662669, Jun. 2005. [10] M. Hagiwara and H. Akagi, Control and experiment of pulsewidthmodulated modular multilevel converters, IEEE Trans. Power. Electron., vol. 24, no. 7, pp. 17371746, Jul. 2009. [11] M. Hagiwara and H. Akagi, Control and analysis of the modular multilevel cascade converter based on double-star chopper-cells (MMCCDSCC), IEEE Trans. Power. Electron., vol. 26, no. 6, pp. 16491658, Jun. 2011. [12] S. Rohner, S. Bernet, M. Hiller, and R. Sommer, Pulsewidth modulation scheme for the modular multilevel converter, in Proc. 13th Eur. Conf. Power Electron. and Appl. (EPE), 2009, pp. 110. [13] S. Rohner, S. Bernet, M. Hiller, and R. Sommer, Modulation, losses, and semiconductor requirements of modular multilevel converters, IEEE Trans. Ind. Electron., vol. 57, no. 8, pp. 26332642, Aug. 2010.

Fig. 14. method.

Spectrum and THD of the output voltage ua n with the improved

Fig. 15. Capacitor voltages of SMU4 (green line, 20 V/div) and SML4 (yellow line, 20 V/div) and the load current ilo a d (pink line, 2 A/div) with the improved method.

LI et al.: AN IMPROVED PULSE WIDTH MODULATION METHOD FOR CHOPPER-CELL-BASED MODULAR MULTILEVEL CONVERTERS

3481

[14] S. Rohner, S. Bernet, M. Hiller, and R. Sommer, Modelling, simulation and analysis of a modular multilevel converter for medium voltage applications, in Proc. IEEE Int. Conf. Ind. Technol. (ICIT), 2010, pp. 775782. [15] M. Saeedifard and R. Iravani, Dynamic performance of a modular multilevel back-to-back HVDC system, IEEE Trans. Power Del., vol. 25, no. 4, pp. 29032912, Oct. 2010. [16] U. N. Gnanarathna, A. M. Gole, and R. P. Jayasinghe, Efcient modeling of modular multilevel HVDC converters (MMC) on electromagnetic transient simulation programs, IEEE Trans. Power Del., vol. 26, no. 1, pp. 316324, Jan. 2011. [17] Q. Tu and Z. Xu, Impact of sampling frequency on harmonic distortion for modular multilevel converter, IEEE Trans. Power Del., vol. 26, no. 1, pp. 298306, Jan. 2011. [18] A. Antonopoulos, L. Angquist, and H. P. Nee, On dynamics and voltage control of the modular multilevel converter, in Proc. Eur. Conf. Power Electron. and Appl. (EPE), 2009, pp. 110. [19] A. J. Korn, M. Winkelnkemper, and P. Steimer, Low output frequency operation of the modular multi-level converter, in Proc. IEEE Energy Convers. Congr. and Expo. (ECCE), 2010, pp. 39933997. [20] Z. Li, Y. Li, P. Wang, H. Zhu, Z. Chu, and S. Wang, Improving the performance of modular multilevel converter by reducing the dead time effect, in Proc. 14th Eur. Conf. Power Electron. Appl. (EPE), 2009, pp. 1 10.

Haibin Zhu was born in Wuhu, China, in 1975. He received the M.S. degree from Yanshan University, Qinhuangdao, China, in 2002. He is currently working toward the Ph.D. degree at the Institute of Electrical Engineering, Chinese Academy of Sciences, Beijing, China. He is also an Assistant Researcher at the Chinese Academy of Sciences. His research interests include inverter-based power supply and green power

Zunfang Chu was born in Shandong, China, in 1982. He received the B.Eng. degree in automation from Shandong University, Weihai, China, in 2005. He is currently working toward the Ph.D. degree in power electronics and power drives at the Institute of Electrical Engineering, Chinese Academy of Sciences, Beijing, China.

Zixin Li (S08M10) was born in Hebei Province, China, in 1981. He received the B.Eng. degree in industry automation from North China University of Technology, Beijing, China, in 2001, and the Ph.D. degree (Hons.) in power electronics and power drives from the Institute of Electrical Engineering, Chinese Academy of Sciences, Beijing, in 2010. He joined the Institute of Electrical Engineering, Chinese Academy of Sciences, in 2010, where he is currently an Associate Professor. His research interests include circuit topology, control and analysis of power converters, especially multilevel converters in high-voltage and highpower elds. Dr. Li has received many honors and awards, including a scholarship awarded to excellent Ph.D. candidates in the Graduate University of Chinese Academy of Sciences offered by the Australia-based company BHP-Billiton in 2009 and the student scholarship from the IEEE ISIE in 2009.

Yaohua Li was born in Henan, China, in 1966. He received the Ph.D. degree in 1994 from Tsinghua University, Beijing, China. From 1995 to 1997, he was a Postdoctoral Research Fellow at the Institute of Electrical Machine, Technical University of Berlin, Berlin, Germany. He joined the Institute of Electrical Engineering, Chinese Academy of Sciences, Beijing, China, in 1997, where he is currently a Professor and Director of the Laboratory of Power Electronics and Electrical Drives. His research interests include analysis and control of electrical machines, and power electronics.

Ping Wang was born in Shanghai, China, in 1955. He received the B.S. degree from Lanzhou University, Lanzhou, China, in 1980. Since 1980 he has been with the Institute of Electrical Engineering, Chinese Academy of Sciences, Beijing, China, where he became an Assistant Engineer in 1985, a Senior Engineer in 1993, and a Professor of Power Electronics and Drives in 2008. From 1995 to 1996, he was a Visiting Researcher at the Fraunhofer Institute for Production Systems and Design Technology, Berlin, Germany. His research interests include power electronics, static power converters, active lter, and ac drives. Mr. Wang is a member of the China Electrotechnical Society.