The 2010 International Power Electronics Conference

A design of FPGA based hardware controller for DC-DC converter using SDRE Approach
,

Takeaki Fujimoto , Fumitoshi Tabuchi , and Tomoki Yokoyama TOKYO DENKI UNIVERSITY, 2-2 Kanda, Nishiki-cho, Chiyodaku, Tokyo, Japan

Abstract A new control method based on State-Dependent Ricatti Equation(SDRE) control for DC-DC converter with FPGA based hardware controller is proposed. Deadbeat control is one effective digital control approach, and the robustness for the variation of the system parameter is the key issue. Some approaches were proposed, for exsample, a single-rate deadbeat control with disturbance observer, a multi-rate deadbeat control, and so on. In the SDRE approach, state conditions which include parameter variations were reected to the feedback system. In the case of power electronics applications, a fast calculation capability of the controller is required compared with the process control and/or the robotics control. In this paper, SDRE control is designed for DC-DC converter. And SDRE control is compared with the various conventional deadbeat control in the point of view from the robustness for the variation of the system parameter. Through simulations and experiments, the proposed method is veried with FPGA based hardware controller, and compared with single-rate deadbeat control, quasi multi-rate deadbeat control and quasi multi-rate 2 degree of freedom deadbeat control.

multi-rate deadbeat control and quasi multi-rate 2 degree of freedom deadbeat control. II. D IGITAL CONTROL A. Modeling Fig.1 shows the system conguration of the proposed method. The state equation of the continuous time model becomes as (1).
L

Vi

Ic = IL-

Vo Rnominal

Vo

Gate Signal

Drive Circuit
FPGA Gate Signal PI control

AD Converter FPGA

Tu uc [k] E

Vo
Reference data

Steady state error compensation

k+1

Vref
V ref Pulse Generation Pulse Width Control Method
,

Fig. 2.

Discrete time model

I. I NTRODUCTION Recently, SDRE control has been proposed to design the nonlinear control system, and practical applications were proposed [1], [2], [3]. As for the nonlinear system, many approaches of the linear control design technique were tried to apply to develop the nonlinear controller, but the satisfying result is still not derived. Each of the proposed methods has a different model and assumptions which cannot be applied easily to another plant, and some trade-off is necessary to satisfy the performance and robustness. A different approach to state estimation of nonlinear system is the SDRE technique. The nonlinear system is assumed as a frozen-in-time linear time varying system, and the Riccati equations used in the state estimation of linear systems are used to determine the feedback gain. So SDRE can handle the nonlinear system as the extension of the Linear Quadratic formulation and can realize the real time implementation of the control system. Some papers were presented in the process control eld and the robotics eld. Also SDRE can introduce the cost evaluation function to determine the control gain, the balance of the control input and the responsibility of the system can be adjusted. On the other hand, various kinds of digital control method for DC-DC converter were proposed like deadbeat control[6]. In this paper, SDRE control method is applied to DC-DC converter with the FPGA based hardware controller to realize the real time digital feedback control. Through simulations and experiments, the advantage of the proposed method is compared with single-rate deadbeat control, quasi

Fig. 1.

DC-DC converter

x(t) = Ac x(t) + Bc u(t) , where AC = [ x(t) = [ vo (t) 0

1 LC

(1)

vo (t) ]T , ] [ ] 0 , BC = . 1
LC

1
1 RC

To derive the discrete time model, it is assumed that the PWM pulse is outputted in the center of the carrier interval as shown in Fig.2, where Tu is the sampling interval and uc [k] is the pulse width, the discrete time model becomes (2) [4]. x[k + 1] = Ad x[k] + Bd uc [k]
, where Ad = eAc Tu = [ 11 21 12 22 ] , Bd = e
Ac Tu 2

(2)
Bc E = [ g1 g2 ] .

B. SDRE based control method In the discrete time model (2), state feedback control is dened as (3). uc [k] = F (x[k + 1] x[k]) , where F = [ f1 f2 ] . (3)

978-1-4244-5393-1/10/$26.00 2010 IEEE

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The performance index for SDRE is dened as (4), which allows to adjust the trade-off for the state error x versus the control input u, using the state dependent weighting matrices Q(x) and R(x). In order to ensure the local stability, the matrix Q(x) is required to be positive semidenite for all x and the matrix R(x) is required to be positive denite for all x. J(u) =
( ) x[k]T Q(x)x[k] + u[k]T R(x)u[k]

(4)

n=1

, where Q(x) =

q(vo [k]) 0 0 0

, R(x) =

Feedback gain F is determined to minimize the performance index J(u). To derive the state feedback gain F , discrete Riccati equation (5) is used and solved for a positive denite state dependent matrix P (x). P (x) AT P (x)Ad + AT P (x)Bd (R(x) + d d T 1 Bd P (x)Bd ) Bd P (x)T Ad Q(x) = 0 [ ]

r(u[k])

C. Selection of State Depend Weighting Matrices Q(x) and R(x) Weighting matrices should be decided based on the characteristics of the system and the state variables. In this paper, the main propose is to improve the tracking accuracy of the output voltage to the reference voltage, using the output voltage vo [k], the state depend weighting matrices Q(x) and R(x) are determined with stable region. (10) show the weighting matrices. In the proposed system, the state depend weighting matrix Q(x) has the portion to improve the tracking accuracy to the reference voltage against the disturbance, and the state depend weighting matrix R(x) has the portion to minimize the variation of the control input range. Q(x) = [ q(vo [k]) 0 0 0 ] , R(x) = [ r(u[k]) ] . (10)

q(vo [k]) = 100.0/(0.1+exp(10.0abs(vo [k +1]vo [k]))) (11) r(u[k]) = 1.0 (12) The weighting variation q(vo [k]) was dened to respond quickly for the variation of vo [k], and the weighting variation r(u[k]) is settled constant as 1.0. The following three types of deadbeat control methods are also considered for comparison. D. Single-rate Deadbeat Control(SRDB)[7] In this method, the carrier frequency and the sampling frequency are equal and the state variable is only the output voltage vo . From (2), using k s sampling data and (k 1) s sampling data, the pulse width uc [k] can be devived as (13).
uc [k] =
1 g1

(5)

, where P (x) =

p11 p12

p12 p22

Feedback gain F can be derived using P (x) of (5), the following equation can be derived.
T F = (Bd P (x)Bd + R(x))1 B T P (x)Ad

(6)

As the result, using (6), the pulse width of the converter can be derived using (3). In SDRE approach, the differentiation value of the output voltage is used for state variable. When IL can be mesuared with current sensor, vo [k] can be derived as (7) and (8). Ic = IL Vo R Ic vo [k] = C (7) (8)

(12 21 11 22 )vo [k 1] (12 g2 22 g1 )u[k 1]} (13)

{vo [k + 1] (11 + 22 )vo [k]

E. Quasi Multi-rate Deadbeat Control(QMRDB)[9] From (2), the discrete time model of the next carrier period becomes (14). Using (2) and (14), multi-rate model of this system can be derived as (15). x[k + 2] = Ad x[k + 1] + Bd u[k + 1] x[k + 2] = A2 x[k] + [Ad Bd , Bd ][u[k], u[k + 1]]T d (15) can be rewritten to (16) while the carrier interval. x[i + 1] = Am x[i] + Bm u[i] (16) (14) (15)

When vo [k] is derived by a backward difference method with only a voltage sensor, the following equation can be derived as (9) using inter-sampling data based on high-speed A/D converter. vo [k] vo pre [k] vo [k] = h 1 h= Ts T s : Sampling interval (9)

, where u[i] = [u[k], u[k + 1]]T , Am := A2 , Bm := [Ad Bd , Bd ]. d

This technique is applied also to quasi multi-rate deadbeat control and quasi multi-rate 2 degree of freedom deadbeat control.

In the multi-rate control, the sampling interval becomes half of a career interval. To keep the sampling frequency coincident with the carrier frequency, the career frequency is assumed to be twice. In the quasi multi-rate deadbeat control, the derived two pulse width uc [k] and uc [k +1] are combined in one pulse width uc [i] in (17) as follows. uc [i] = uc [k] + uc [k + 1] (17)

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Tu

Tu
Voltage[V]

5.2

5.2

400us
overshoot 3.04% 5.1
5.1

200us overshoot 1.38%

0.5%
5.0

Voltage[V]

0.5%
5.0

uc[k]

uc[k+1]

uc[i]

Vo

Vo

4.9 undershoot 2.43%

4.9

undershoot 2.60%
4.8 5

k i

k+1

k+2 i+1

k i

k+1

k+2 i+1
Current[A]

4.8 5

3 2 1 0

IL Io
0 0.0002 0.0004 0.0006 0.0008 0.001 0.0012

Current[A]

Fig. 3.

Quasi multi-rate Deadbeat Control(QMRDB)

4 3 2 1 0 -1

IL Io
0 0.0002 0.0004 0.0006 0.0008 0.001 0.0012 Time[sec]

F. Quasi Multi-rate 2 Degree of Freedom Deadbeat Control(QMR2DoFDB)[8] Carrier frequency is twice as the sampling frequency, and the state variables are the output voltage and derivation of the output voltage. In this method, the feedforward control guaranteed the traceability to the reference voltage for the nominal system, and the error to the nominal model is compensated by the feedback control. Pulse width uc [i] can be devived as (18). The derived two pulse width uc [k] and uc [k +1] are combined in one pulse width uc [i] as (17). ( ) 1 uc [i] = Bn I z 1 An x [i + 1] + F (x [k] x[i]) (18) x [i] = [vref [i], vref [i]]
T

-1

Time[sec]

(a) SRDB
5.2 5.2

(b) QMRDB

204us
5.1

401us overshoot 1.19% 0.5%

overshoot 2.84% 5.1

Voltage[V]

Voltage[V]

0.5%
5.0

5.0

Vo

Vo

4.9

4.9

undershoot 2.54%
4.8 5 4.8 5

undershoot 2.64%

Current[A]

3 2 1 0 -1

Current[A]

4 3 2 1 0 -1

Io IL
0 0.0002 0.0004 0.0006 0.0008 0.001 0.0012

Io IL
0 0.0002 0.0004 0.0006 0.0008 0.001 0.0012

III. S IMULATION Table.I shows the system parameters for simulations and experiments.
TABLE. I S IMULATION AND E XPERIMENT C ONDITIONS Carrier frequency:f c[kHz] 100 Input DC Voltage[V] 12 Reference Voltage[V] 5 Inductance[H] 95 Capacitance[F] 470 Rated Resistance[] 2 Fig. 4.

Time[sec]

Time[sec]

(c) 2DoFQMRDB

(d) SDRE

Step responce for each control method(R = 80 2) TABLE. III R ESPONSE VERIFICATION control low overshoot[%] SRDB 3.38 QMRDB 3.24 QMR2DoFDB 3.28 SDRE 2.79
FOR SIMLATION

convergence time[s]

1120 1080 1090 903

5.2 1.12ms 5.1 overshoot 3.38%

5.2 1.08ms 5.1

A. Ideal condition The carrier frequency of DC-DC converter is settled to 100 kHz. Fig.5 show the step response(R = 80 2) for each control method. In SDRE control, a fast transient response with 401 s convergence time that the output voltage is settled within 0.5 % was obtained.
TABLE. II R ESPONSE VERIFICATION FOR SIMLATION control low overshoot[%] undershoot[%] convergence time[s] SRDB 3.04 2.43 400 QMRDB 1.38 2.60 200 QMR2DoFDB 1.19 2.54 204 SDRE 2.84 2.64 401

Voltage[V]

5.0

Vo

Voltage[V]

0.5%

overshoot 3.24% 5.0

0.5%

Vo

4.9

4.9

4.8 5 4

4.8 5

Current[A]

Current[A]

3 2 1 0 -1

IL

4 3 2 1 0 -1

IL

Io

Io

0.0002

0.0004

0.0006 0.0008

0.001

0.0012 Time[sec]

0.0014

0.0016 0.0018

0.002

0.0022

0.0024

0.0002

0.0004

0.0006 0.0008

0.001

0.0012 0.0014 Time[sec]

0.0016

0.0018

0.002

0.0022

0.0024

5.2
5.2 1.09ms

903us 5.1

Voltage[V]

5.1 overshoot 3.28%

overshoot 2.79% 5.0

0.5%

Voltage[V]

0.5%

Vo

5.0

Vo

4.9
4.9

4.8
4.8

Current[A]

5 4

4 3 2 1 0 -1 0

IL

Current[A]

3 2 1 0 -1 0 0.0002 0.0004

IL

Io
0.0002 0.0004 0.0006 0.0008 0.001 0.0012 0.0014 0.0016 0.0018 0.002 0.0022 0.0024

Io

0.0006

0.0008

0.001

0.0012

0.0014

0.0016

0.0018

0.002

0.0022

0.0024

Time[sec]

Time[sec]

(d) SDRE

Fig. 5.

Step responce for each control method(R = 2 80)

B. Stability evaluation for parameter variations Stability for each control strategy was evaluated when the C value is changed from 0.01 to 500 against the nominal value

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of the LC lter, the pole locus of the closed loop system in the z domain is shown in Fig. 6, Fig. 7 and Fig. 8 respectively. In the case of MR2DoFDB, the feedback gain F is designed as the pole of the closed loop system is settled with the resonant frequency fc is 750Hz and the damping coefcient w is 0.112. These results indicates that in the SDRE control, the stable pole locus is conrmed with the wide C parameter variations compared with the other control method.
2

5.4 5.3 Voltage[V]

5.4 5.3 Voltage[V] 5.2 5.1 5 4.9 4.8 0.0

5.2 5.1 5 4.9 4.8 0.0

/
0.0001 0.0002 0.0003 Time[sec] 0.0004 0.0005

0.0001

0.0002 0.0003 Time[sec]

0.0004

0.0005

(a) SRDB

(b) QMRDB
5.4 5.3 Voltage[V] 5.2 5.1 5 4.9 4.8 0.0

5.4 5.3 5.2 5.1 5

1.5

Voltage[V]

4.9

Imaginary

0.34
0.5

4.8 0.0

0.0001

0.5

0.0002 0.0003 Time[sec]

0.0004

0.0005

0.0001

0.0002 0.0003 Time[sec]

0.0004

0.0005

10 1.0 500

(c) QMR2DoFDB

(d) SDRE

Fig. 9.

Robustness for the parameter variation(C:10%)

-0.5

IV. E XPERIMENT
-1.5 -1 -0.5 0 0.5 1 1.5 2

-1 -2

Real

Fig. 6.

Pole locus of C variation(MRDB)

2

1.5

Fig.10 shows the conguration of the experimental setup. Cyclone III was used as the FPGA controller, and the clock frequency of the FPGA is 60MHz. Fig.11 shows the timing chart of the control calculation in FPGA circuit. All the calculation was nished in 985.3ns for one carrier interval. So within the dead time of the MOS-FET, all the calculation can be nished, the real-time digital feedback control system can be realized.
Gate Drive Signal UP UN

Imaginary

0.5

1.0 10

FPGA Chip
Pulse Generation Carrier Carrier Generation Pulse width Pulse width Calculation Result Monitor Pulse width To various components 60MHz 50MHz

0.02
-0.5

0.1

500

-1 -2

-1.5

-1

-0.5

0.5

1.5

2
Control Calculation Timing Controller A/D Interface Reference Generation

Real

Fig. 7.

Pole locus of C variation(MR2DoFDB)

2

Main PLL

A/D Vo

Base Clock 50MHz

1.5

Fig. 10.

Internal Circuit of FPGA

Imaginary

10us (100kHz)

0.5

985.3ns

10
0

16.7ns(60MHz) ....... clock 0 1 Vo AD Conversion

Quasi differential voltage Generation

53

54

55 . . . 57 Control Calculation

58 Monitoring of pulse width calculation result

59 Pulse Generation and Gate Drive

.......

599

1.0 0.01 500

Vo_pre

-0.5

Vo Vo_ref

Gate Signal UP UN

-1 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2

Vo_ref Generation

Real

Fig. 8.

Pole locus of C variation(SDRE)

Control

C. Robustness for the parameter variations Fig.9 shows the output voltage when the output lter C is varied to 10% of the nominal value for each control method. It is obvious that in the case of SDRE, the output voltage is stable compared with the other method.
Fig. 11.

Control Calculation and Pulse Generation

Timing chart of control calculation in FPGA controller

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The 2010 International Power Electronics Conference

A. Ideal condition
Voltage[V]

6
301us

6
165us

5.5

overshoot 5.2%

5.5

overshoot 5.2%

Vo
5 undershoot 2.4% 4.5

2.0%

Voltage[V]

Fig.13 show the experimental waveforms for each control method. Each result shows the very fast transient response for the step load change. Overshoot and undershoot of the output voltage is well suppressed and the output current is stable.
TABLE. IV
EXPERIMENTAL RESULT FOR STEP RESPONSE (R

Vo
5 undershoot 2.2%

2.0%

4.5

4 3 Current[A]
Current[A]

4 3

2 1 0 -1 0

Io

2 1 0 -1

Io

0.0002

0.0004

0.0006

0.0008

0.001

0.0012

0.0014

0.0002

0.0004

0.0006

0.0008

0.001

0.0012

0.0014

(a) SRDB

Time[sec]

(b) QMRDB

Time[sec]

Current[A]

Current[A]

control low SRDB QMRDB QMR2DoFDB SDRE

overshoot[%] 1.4 1.0 4.2 2.0

undershoot[%] 10.0 9.2 8.2 5.4

= 80 2)

6
162us

settling time[s] 235 231 294 200

overshoot 6.2%
5.5

371us

5.5 Voltage[V]

overshoot 6.2%

Vo
5 undershoot 1.8% 4.5

2.0%

Voltage[V]

Vo
5 undershoot 1.6% 4.5

2.0%

4 3 2 1 0 -1 0 0.0002 0.0004 0.0006 0.0008 0.001 0.0012 0.0014 Time[sec]

4 3

Io

2 1 0 -1 0

Io

0.0002

0.0004

0.0006

0.0008

0.001

0.0012

0.0014

(c) 2DoFQMRDB
6 235us 5.5 overshoot 1.4% 5.5 2.0% 6 231us overshoot 1.0%

(d) SDRE

Time[sec]

Fig. 13.
2.0%

Step responce for each control method(R = 2 80)

Voltage[V]

Vo
5

Voltage[V]

Vo
5

A. Robustness for the parameter variations

undershoot 9.2%

4.5 undershoot 10.0% 4 3

4.5

4 3

Fig.14 shows the output voltage when the output lter C is varied to 46% of the nominal value for each control method.
6 6 5.5 Voltage[V] Voltage[V] 5.5

Current[A]

Current[A]

2 1

2 1 0 -1

Io
0 -1

Io

0.0002

0.0004 Time[sec]

0.0006

0.0008

0.0002

0.0004 Time[sec]

0.0006

0.0008

4.5

4.5

4 0 0.0002 0.0004 0.0006 0.0008 0.001 0.0012 0.0014 Time[sec]

4 0 0.0002 0.0004 0.0006 0.0008 0.001 0.0012 0.0014 Time[sec]

(a) SRDB
6 294us 5.5 overshoot 4.2%
5.5 6

(b) QMRDB

(a) SDRB

(b) QMRDB

200us overshoot 2.0%

Voltage[V] 5.5

5.5 Voltage[V]

Voltage[V]

Vo
5

2.0%

Voltage[V]

Vo
5

2.0%

4.5

4.5

4.5 undershoot 8.2% 4 3

4.5

undershoot 5.4%

4 0 0.0002 0.0004 0.0006 0.0008 0.001 0.0012 0.0014 Time[sec]

4 0 0.0002 0.0004 0.0006 0.0008 0.001 0.0012 0.0014 Time[sec]

(c) 2DoFQMRDB
4 3

(d) SDRE

Fig. 14.
Io

Robustness for the parameter variation(C:46%)

Current[A]

Current[A]

2 1 0 -1

2 1 0 -1

Io

R EFERENCES
0.0002 0.0004 Time[sec] 0.0006 0.0008

0.0002

0.0004 Time[sec]

0.0006

0.0008

(c) 2DoFQMRDB

(d) SDRE

Fig. 12.

Step responce for each control method(R = 80 2) TABLE. V

EXPERIMENTAL RESULT FOR STEP RESPONSE (R

control low SRDB QMRDB QMR2DoFDB SDRE

overshoot[%] 5.2 5.2 6.2 8.0

undershoot[%] 2.4 2.2 1.8 1.6

= 2 80)

settling time[s] 301 165 162 200

V. C ONCLUSION SDRE control of DC-DC converter with the FPGA based hardware controller was proposed and veried through simulations and experiments. SDRE approach is suitable to control nonlinear system with the extension of linear system methodology and can be implemented in real-time digital feedback system. To realize the fast calculation capability, FPGA based hardware controller was used for implementation, and desired performance was obtained.

[1] Cloutier, J.R., D Souza, C.N., Marcek, C.P. Nonlinear regulation and Nonlinear H Control via the State-Dependent Riccati Equation Technique: Part I, Theory; Part 2, Examples, Proc. 1st International Conderence on Nonlinear Problems in Aviation and Aerospace, May 1996. [2] Erdem, E.B., Alleyne, A.G., Experimental Real-Time SDRE Control of an Underactuated Robot , Proc. Of the 40th IEEE conference on Decision and Control, Orland, USA, 2001. [3] Masami Iwase, Kouki Watanabe, Nonlinear Control based on the StateDependent Riccati Equation , Trans of Simulation, No.27, vol.4, 2008. [4] K.P.Gokhale, A.Kawamura and R.G.Hoft Deadbeat Microprocessor Control of PWM Inverter for Sisusoidal Output Waveform Synthesis ,ibid.IA- 23,901, (1987) (originally published at PESC 85,1985) [5] A.Kawamura, H.Fujimoto, T.Yokoyama: Survey on the real time digital feedback control of PWM inverter and the extension to multiratesampling and FPGA based inverter control , IECON 2007 [6] Jingsheng Liao, and Mehdi Ferdowsi, Kai Wan, Control Methods in DC-DC Power Conversion - A Comparative Study, IEEE, PESC 2007 [7] T. Yokoyama, M. Horiuchi, S. Simogata, Instantaneous Deadbeat Control for PWM Inverter Using FPGA Based Hardware Controller, IECON 2003 [8] T. Yokoyama, M. Horiuchi, S. Simogata, A New Approach of Multirate Deadbeat Control for PWM Inverter, JIASC 2004 [9] T. Yokoyama, S. Tahara, T. Fujii, Variable Sampling Quasi Multirate Deadbeat Control Method for Single Phase PWM Inverter in Low Carrier Frequency LS3-2-2, pp.804-809 PCC 2007

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