201O Interational Conference on Computer, Mechatronics, Control and Electronic Engineering (CMCE)

OgIalrOpOrIOnal plu8OcrVaIVcLOnIrOllcrOr WIchngOL-OL

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OnL, JnOun VO, Kun ZhOn, unYun
School of Computer Science and Technology, Northwester Poly technical University
Xi'an China
tttlifeng@mail.nwpu.edu.cn
Ab5lr0ClDigital proportional plus derivative (D-PD)
controller with zero steady-state error is introduced for buck
dc-dc converters. The proposed D-PD controller decreases
the number of look-up tables from three to two, and
decreases the adder input from four to three in the
compensator circuits in contrast with digital proportional
plus integral plus derivative (D-PID) controller. A new
technique, called as error-shif technique, is proposed to
eliminate steady-state error without increasing any
hardware cost. Therefore, the proposed D-PD controller can
greatly reduce the layout area. Simulation shows that D-PD
controller is better than D-PID controller for the gross
performance of switching dc-dc converters.
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I. INTRODUCTION
Digital control of switching dc-dc converters has
attracted wide attentions in recent years due to the
advantages of programmability, robustness to noise and
high fexibility. Many digital control methods were
proposed [1-8].
For digital current mode control, the peak, valley or
average value of the inductor cur ent is compared with a
reference curent [1-3]. However, sampling the cur ent in
high fequency, keeping the reference cur ent constant and
current harmonic distorion need be solved. For digital
fzzy control which converts the expert knowledge into
linguistic rules, the fast transient response can be achieved.
However, the theory of digital fzzy control is still
immature, and it is usually combined with linear control
law to get the better performance [4-6]. Depending on the
existing mathematical model of dc-dc converter power
stage, linear control law such as digital proportional plus
integral plus derivative (D-PID) which uses fequency
domain design and analog-to-digital re-design is more
familiar for engineers ad more effective for dc-dc
converters than the above digital control methods [7-8].
Based on buck dc-dc converers, digital proporional
plus derivative (D-PD) controller which belongs to linear
control law is introduced and studied in this paper, and
eror-shif technique is proposed to realize zero steady
state error of the converter system for D-PD controller. In
section II, D-PD control law and eror-shif technique are
proposed, and the steady-state condition for D-PD
controller is analyzed. In section Ill, implementing of D
PD controller is discussed including digital compensator
and analog-to-digital converer (ADC). In section IV,
simulation shows the gross perforance of buck
978-1-4244-7956-611 0/$26.00 20 1 0 IEEE
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t R
l'' =
Figure !. block diagram of the buck dc-dc converter.
converters for both the proposed D-PD controller and D
PID controller. In section V, conclusions are given.
II. DIGITAL PROPORTIONAL PLUS DERIVATIVE
CONTROL
Fig. depicts the block diagram of buck dc-dc
converters, in which digital proportional plus derivative
contol law is applied. The feedback is composed of
analog-to-digital converter, digital compensator and digital
pulse-width modulator (DPWM), |, |,and |.,,are input
voltage, output voltage and reference voltage, respectively.
Digital compensator outputs digital cycle duty d based on
signal L which is the digital eror between output voltage
and reference voltage. In according with d, DPWM outputs
the square wave a(t which controls the power stage switch
on or off to regulate the output voltage.
A. Control Luw
Frequency domain design and analog-to-digital re
design are applied to get control law of the D-PD
controller in this study. For the buck dc-dc converter
shown in Fig 1, the transfer fnction of the power stage
fom control to outut voltage is [9]:
C {s)-
vO
LCs

{L1R)si

(1)
where L, C and R are flter inductor, flter capacitor and
load resistance, respectively. The power stage is a typical
resonance system, so proporional plus derivative
compensator with a non-zero pole is applied to control the
close-loop system, and the transfer fnction of the
compensator is:
CMCE 2010
(2)
where is the root locus gain, Y_ is zero to counteract one
pole of the power stage (1), w_ is high fequency pole to
restrain high fequency noise existing in the loop.
The discretization methods by which the s-domain
transfer fnction is mapped to z-domain include Euler
method, root-matchig method and equal-effect holder
method [10]. The difference of these methods for the gross
system performance can be ignored as the sampling rate
(switching fequency) achieves mega-level in low-voltage
converters, so backward Euler method which is relatively
simple is applied, and its transfer equation is:
l
j
-

]
(3)
where Ts is sampling cycle, and equal to switching cycle
for switching dc-dc converters. From (2) and (3), the
transfer difference equation of the digital compensator is
obtained:
d(k)- ad(k-l) oe(k) .e(k-l). (4.a)
l
a=
l W
]
I_
o-
K
'
l W_] )

l W
]
]
K
.-
l W
]
]
(4.b)
(4.c)
(4.d)
Equation (4) is the discrete time-domain control law of
D-PD controllers for dc-dc converters.
D. Steady-State Analysis
When the digitally controlled dc-dc converters gets
stable, digital cycle duty d[k} and digital error e[k} will
keep constant, so steady-state control law of D-PD
controller can be obtained fom (4):
d k |-
o .
e k|

ia
(5)
Digital error e[k} must never be equal to zero in the
steady state; otherwise d[k} is equal to zero, so this steady
state control law is different fom D-PID compensator that
the input digital error is equal to zero, and output cycle
duty is unlimited by the input error in the steady state. The
following equation is obtained based on the DPWM
operation for buck dc-dc converters:
1 -
|
-
dk|
| ,
^
'

(6)
where D is the steady cycle duty of the square wave,
^,is the DPWM resolution. From (5) and (6), the error
limit equation is obtained:
O1
(ia)|
ek|-
'
,
^

(o .)|

(7)
Equation (7) is the steady-state condition which digital
error e[k) must follow for D-PD controller.
C. Error-Shi Technique
Although the close-loop converter system shown in
Fig.l is zero-type system for D-PD controller [11], steady
state error can be eliminated by error-shif technique. Fig.2
(a) shows the transfer curve of the conventional ADC, |,
is LSB size, and the zero error-bin of dc-dc converters is
fom |.,,[ to |.,,+ | 2. The horizontal axis is
expressed as |.,,|,`,because the ADC input is equivalent
to the error between reference voltage and output voltage.
The ADC encodig fnction can be abstracted:
ek |-
1
..''

'
)

(8)
When steady-state error of the converter system is
equal to zero (} [|.,,| 2, |.,,+ | 2 ], e[k} also
becomes zero shown in Fig.2 (a), but this situation violates
the steady-state condition obtained in the above content.
Therefore, we must modif the ADC encoding fnction to
shif output eror as shown in Fig.2 (b), and then defne the
following equation:
(ia)|
e -
C
,
^

''J
(o .)|

(9)
where eshii is the shifed error. The modifed encoding
fnction is obtained based on Fig.2 (b), (8) and (9):
ek|-
1
(| |)
'
l-a)
'
,
^

(10)
.. C
(o.)|

When the digitally controlled converter gets stable, (7)

and (10) must be both followed, so |, must be located at
zero error-bin of dc-dc converters in order to force the
fnction ] (|.,,|,) equal to zero, then steady-state
error can be eliminated for D-PD controller. The above
shif process is called as eror-shif technique.
[|]
'4
Figure 2. transfer curve of ADC: (a) conventional ADC; (b) ADC with
error-shif technique
III. To IMPLEMENT DIGITAL PROPORTIONAL PLUS
DERIVATIVE CONTROLLER
A. Analog-to-Digital Converter
Error-shif technique must be implemented in ADC to
eliminate steady-state eror for D-PD controIler. Fig.3
depicts the simple block diagram of delay-line window
ADC with error-shif technique, the latched thermometer
code is encoded into elk}, and only the encoding rule is
different fom the conventional ADC. According to the
principle shown in Fig.2, the thermometer code
corresponding with zero-elk} in the conventional ADC is
encoded into eshi, and corresponding with one-elk} in the
conventional ADC is encoded into eshi ', and so on.
Therefore, only adjusting the encoding logic in the last
encoder and never chaging the other circuits, eror-shif
technique can be easily implemented in ADC.
D. Digital Compensator
The digital compensator input is one of only a few
different valves because window-ADC is applied in
switching dc-dc converters, so coeffcient multiplication of
the control law (4) ca be implemented by look-up tables
(LUTs) in order to decrease the loop delay. Considering
high-fequency pole w_ almost has no effect on the gross
system performance, we can set w_:
,
^
-l)

1 Z J (11)
S
From (4.b) and (11), coeffcient a is equal to 1I2N, so
coeffcient a look-up table can be replaced by one shifer.
The shifing number ^ should not be too big in order that
pole w_ can effectively restrain high-fequency noise
existing in the loop. FigA depicts the block diagram of D
PD compensator which mainly includes two look-up tables,
one adder and one shifer. Comparing to D-PID
compensator [8], the number ofJook-up tables is decreased
form three to two, and the adder input is decreases fom
four to three.
IV. SIMULATION
This section presents the simulation results by
30|O
I|O|00Ol
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- e[\]
Figure 3. block diagram of delay-line window-ADC with error-shif
technique.
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Figure 4. block diagram of digital compensator.
TLAB/Simulink to verif the validity of the proposed
D-PD controller. We choose the following circuit
parameters for continuous conduction mode (CCM) based
on the buck dc-dc converters shown in Fig.l :
/=l.OMHz, L=l.OjH C=22.0jF R=2.7Q, Vg=6.0V
Vo=Vre.2.7V, Vq=25.0mV
We set w,equal to 3wn14, w,is the comer fequency of
the power stage LC flter, and set ^ equal to two, so w_ is
equal to 3/. Adjusting root locus gain , the phase margin
of the open-loop converter system can be set to 60 as
shown in Fig. 5, and then the control law coeffcients are
obtained based on (4):
a=0.25, b=19.00, c=-16.00
It should be noted that the c-LUT can also be replaced
by another shifer because coefcient L is an exponential
fnction of two, but this does not always happen. The
ADC resolution should be 8 bit according to the LSB size
Vq, so the DPWM resolution is set to 9 bit in order to avoid
limit cycles [12]. The zero eror-bin of the dc-dc converter
is fom 2.6875V to 2.7125V which the ideal output with
zero steady-state error should be located in.
Fig. 6 shows the load transient characteristics of the
buck dc-dc converters for the proposed D-PD controIler
and D-PID controller, with the load step change fom 2A
to lA at 1.3ms and back to 2A at 2.3ms, the circuit
parameters of two converters are same. The two curves are
both located in the zero eror-bin of dc-dc converters afer
the stabilization of the systems, so this indicates that the
proposed D-PD controller has the same effectiveness as D
PID controller to eliminate steady-state error. However, for
the proposed D-PD controlled converter, overshoot is 3%,
and transitional time is 0.3ms afer the load step change,
40 .
~ 40
"
_ t:
_ '

-10
-20
= - . .. l
Pha c:ag 0
r-

_ _ _ _
|rcqucocy(rad/scc)
Figure 5. bode diagram of the open-loop converter system

t

t
^ll
.
~l-1
/
J
j

''\\\\' \

!'
!
!t
!
t
!

., .\_ ......,.
.
~
-+
' `r

4
.. . /.,


!
.2 .4 .6 .S 2 2.2 2.4 2.6 2.S J J.2
timc,ms)
Figure 6. Load transient waveforms obtained by M TLAB/Simulink
simulation for load step change fom 2A to lA and back to 2A
while overshoot is 6%, and transitional time is O.5ms for
the D-PID controlled converter, so the proposed D-PD
contoller is better than D-PID controllers for the dynamic
performance of dc-dc converter.
V. CONCLUSION
This paper introduces digital proportional plus
derivative (D-PD) controller which can signifcantly
decrease the layout area of digital compensator in contrast
with D-PID controller for switching dc-dc converters.
Error-shif technique which can be easily implemented in
delay-line window-AC is proposed to eliminate steady
state eror for the proposed D-PD controller. Simulation
shows that the proposed D-PD controller can achieve the
same steady-state performance and better dynamic
performance than D-PID controller for switching dc-dc
converters.
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