You are on page 1of 56

DSP Primer

Digital Logic Review

Return to...

Notes

Version 6.3/26/11

For Academic Use Only in Accordance with Licence-to-Use, see readme.pdf

THIS SLIDE IS BLANK

Digital Logic - the bottom line

Top

2.1

Digital Signal Processing (DSP) with FPGAs has the usual digital logic bottom line - logic gates! In this session we revisit a few fundamentals: Number Systems; Boolean algebra; Combinational Systems; Sequential Systems; Synchronous/Asynchronous Systems; Counters review; Synchronous Sequential Systems Design techniques.

Version 6.3/26/11 For Academic Use Only. All Rights Reserved

Notes:

Top

Logic Levels and Number Systems

2.2

Decimal Numbers - Base 10, based, or course on our ten fingers! Using two logic levels gives two distinct states or or HI and LO 1 and 0 True and False

and hence can be used to represent binary numbers (base 2). For electronic systems typically TTL voltage levels assigned Logic (or digit) 0 = 0 volts Logic (or digit) 1 = 5 volts

Distributed by: http://www.xilinx.com/univ/

Developed by:

Noise Margin
In modern logic the logic 1 is likely to 3.3 volts.

Top

2.3

Recalling that P V 2 , then going from 5 volts to 3.3 volts represents a power drop from 5 x 5 = 25 to 3.3 3.3 = 10.89 , or a reducing power requirements by more than 50%. Although lower voltage is lower power consumption the potential noise margin is higher:
5v 3v 2v 0v Input Logic 1 (HI) Not allowed Logic 0 (LO) Output 5v Logic 1 (HI) 4.4v VIH (min) VIL (max) Not allowed 0.33v 0v Logic 0 (LO) VOL (max)

VOH (min)

V NH = V OH(min) V IH(min) V NL = V IL(max) V OL(max)

Version 6.3/26/11 For Academic Use Only. All Rights Reserved

Notes:

Top

Decimal to Binary
27 128 0 26 64 1 25 32 0 24 16 1 23 8 0 22 4 1 21 2 1 20 1 0

2.4

To convert from binary to decimal we can set up a table of powers of two: Convert 10101102 to decimal

= 64 +16 + 4 + 2 = 8610 The binary point can also be represented: Convert 11.1011 to decimal
21 2 1 20 1 1 2-1 0.5 1 2-2 0.25 0 2-3 0.125 1 2-4 0.0625 1

= 2 + 1 + 0.5 + 0.125 + 0.0625 = 3.687510


Distributed by: http://www.xilinx.com/univ/ Developed by:

Decimal to Binary Conversion

Top

2.5

Inverse of Binary to Decimal is easiest to accomplish via successive subtraction method. For example, convert 27910 to binary (base 2). Recall powers of two are: 1, 2, 4, 8, 16, 32, 64, 128, 256, 512....
279 - 512 279 - 256 23 - 128 23 - 64 23 - 32 23 - 16 7-8 7-4 3-2 = -ve = +23 = -ve = -ve = -ve = +7 = -ve = +3 = +1 0 1 0 0 0 1 0 1 1

1-1

=0

i.e. 27910 = 1000101112


Version 6.3/26/11 For Academic Use Only. All Rights Reserved

Notes:

Top

Binary Arithmetic 1
0+0 = 0+1 = 1+0 = 1+1 = 1+1+1 = 0 1 1 10 11 (zero) (one) (one) (two) (three)

2.6

From our decimal point of view, easy to show that for binary:

i.e. zero carry one) i.e. one carry one)

Hence for Addition: 1011 + 1101 11000 ....and for Subtraction: 11101 -01011 10010 +29 -11 +18 +11 +13 +24

Distributed by: http://www.xilinx.com/univ/

Developed by:

Binary Arithmetic 2
Multiply 1011 by 1001 (11 x 9 = 99) 1011 1001 1011 0000 0000 +1011 1100011 Divide 11001 by 101 (25/5 = 5) 101 101 11001 101 101 101

Top

2.7

Version 6.3/26/11 For Academic Use Only. All Rights Reserved

Notes:

Top

Binary Numbers Range


e.g., 4 (a nibble), 8 (a byte), 16 (a word), 32,.....

2.8

In many applications wordlengths of a power of 2 are used

The numerical range of an N bit number is: 0 2N - 1 28 - 1 = 255 216 - 1 = 65536

For 8 bit numbers range is 0 For 16 bit numbers range is 0

The range of binary numbers chosen for a specific application must be sufficient to represent all numerical values likely to be encountered. If a calculation in a binary system has a result outwith the permissible range, then this is overflow.
Distributed by: http://www.xilinx.com/univ/ Developed by:

Signed Binary Numbers

Top

2.9

2s complement notation is the most common means of representing signed (+ve or -ve) number. In 2s comp. the MSB (most significant bit) has a -ve weighting. Consider 8 bit 2s complement number representation:
-27 -128 1 26 64 0 25 32 1 24 16 0 23 8 1 22 4 1 21 2 0 20 1 1

101011012 = -128 + 32 + 8 +4 +1 = -8310 For an N bit 2s complement representation numerical range is: -2N-1 2N-1 - 1

e.g. for 8 bit 2s complement, range is -128 to +127.

Version 6.3/26/11 For Academic Use Only. All Rights Reserved

Notes:

Top

Arithmetic with 2s Complement

2.10

When using 2s complement, we just add as normal. However for fixed wordlength problems, we detect overflow if a result is outside of the fixed wordlength. For example if 8 bit numbers are used, then the operands and result must lie in the range -128 to +127. For example (-73) + 127 = 54
Discard final 9th bit carry No overflow MSB bit indicate -ve result! Overflow

10110111 +01111111 1 00110110

100 + 64 = 164

01100100 +01000000 10100100

Adding +ve and -ve Adding +ve and +ve Adding -ve and -ve Distributed by:
http://www.xilinx.com/univ/

will never overflow! if a -ve result then overflow if a +ve result then overflow Developed by:

Hexadecimal
Hexadecimal or Hex is Base 16.

Top

2.11

Simply used because binary notation is prone to written error by humans, converting to decimal is inconvenient. Hex provides an easy-to-calculate-from-binary compact representation of binary values. The (sixteen) Hex digits are: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F Binary equivalents are all 4 bits, i.e. 0000 (0) to 1111 (F).

Version 6.3/26/11 For Academic Use Only. All Rights Reserved

Notes:

Top

Hexadecimal Example
163 4096 A 162 256 1 161 16 0 160 1 4

2.12

Hex to decimal can be accomplished via a tabular technique:

A10416 = (A x 4096) + (1 x 256) + 4 = 4122010 Easy to convert to binary: A10416 = 1010 0001 0000 01002
A 1 0 4

Simply replace Hex digits with 4 bit binary equivalents. Checking..... 1010 0001 0000 0100 = 32768 + 8192 + 256 + 4 = 4122010
Distributed by: http://www.xilinx.com/univ/ Developed by:

Questions 1
Convert 10510 to binary. Convert the binary number 100111101 to decimal. What is range of 10 bit 2s complement numbers? Convert the 8 bit 2s complement value 10010001 to decimal. Convert the 8 bit 2s complement value 01110001 to decimal.

Top

2.13

Add the 8 bit 2s complement values 11111111 + 11111110 together. Does this result overflow? If 16 bit binary 2s complement numbers are used, what is the decimal and binary equivalent of FFFF16? Octal is base 8. Why might octal be of use for digital systems?

Version 6.3/26/11 For Academic Use Only. All Rights Reserved

Notes:

Top

Logic Elements
B NOT B = A AB 01 10 X Y OR Z = A+B Z XY 00 01 10 11 Z 0 1 1 1

2.14

E F AND G = EF
Distributed by: http://www.xilinx.com/univ/

EF 00 01 10 11

G 0 0 0 1

P Q EOR R = P+Q

PQ 00 01 10 11
Developed by:

R 0 1 1 0

The Universal Gate


The Not-AND (NAND) gate can be used to create all other gates:

Top

2.15

The OR gate is produced as: X Y Z X Y Z

Algebraically: Z = AB = A + B Question: Is a NOR (NOT-OR) a universal gate?

Version 6.3/26/11 For Academic Use Only. All Rights Reserved

Notes:

Top

Boolean Algebra

2.16

The representation of logical circuits can be done with Boolean expressions as above, and the manipulation of Boolean expressions performed using the laws of Boolean algebra. Boolean variables can have one of two values: 0 or 1. Laws: Complementation: A + A = 1 Involution: Indempotency Absorption Association Distribution De-Morgans
Distributed by: http://www.xilinx.com/univ/

AA = 0 A+1 = 1 AA = A A + AB = A

A = A A+A = A

Union/Intersection A + 0 = A

A(A + B) = A

A + (B + C) = (A + B) + C A + BC = ( A + B ) ( A + C ) ( A + B ) = AB ( AB ) = A + B
Developed by:

Boolean Circuit Representation

Top

2.17

Any combinational circuit using digital logic components can be written in Boolean algebra. A B C X

X = AB Y = ( AB + C )D = ABCD = ( A + B )CD = ACD + BCD A combinational circuit does not include feedback or memory.

Version 6.3/26/11 For Academic Use Only. All Rights Reserved

Notes:

Top

Standard Boolean Forms

2.18

Sum of Products (SOP) or an OR of ANDs e.g. Y ( A, B, C ) = ABC + ABC + AB


AND AND OR AND

Product of Sums (POS) or an AND of ORs e.g. P ( X, Y, Z ) = ( X + Y + Z ) ( X + Y )


OR AND OR

Distributed by: http://www.xilinx.com/univ/

Developed by:

Two Level Gate Implementations


Y ( A, B, C ) = ABC + ABC + AB
A B C A B C A B

Top

2.19

Standard form SOP can be implemented in a two level AND/OR configuration (POS can be implemented in two level OR/AND):

If all product terms contain all variables then this is often referred to as sum of minterms or canonical sum of products. Y ( A, B, C ) = ABC + ABC + AB ( C + C ) = ABC + ABC + ABC + ABC

Version 6.3/26/11 For Academic Use Only. All Rights Reserved

Notes:

Top

Boolean Expressions and Truth Tables

2.20

Boolean expressions can be easily converted into truth tables using binary values for each term in the expression when written in the standard form. For example

ABC 000 001 010 011 100 101 110 111

F 1 0 0 0 0 1 1 1

minterm

F ( A, B, C ) = ABC + ABC + ABC + ABC


000 101 110 111

= ( 0, 5, 6, 7 )
shorthand form

truth table
Developed by:

Distributed by: http://www.xilinx.com/univ/

Review Examples

Top

2.21

1. Implement the following Boolean functions using simple AND, OR and NOT logic gates (do not simplify the functions): (b) F = A BC + ABC + A B (a) F = AB + ABC + CD (c) F = A + ABC + ABC (d) F = X Y Z(W + YZ) + ZW + X Y 2. Reduce the following expressions, using Boolean algebraic methods. State the relevant law or postulate used at each step. (a) X.X.Y (b) X + X + Y (c) (X + X).B (d) B+ B.A (e) Y.(Y+X) (f) (A+B).(A+C) 3. Using only the theory of Boolean algebra and algebraic manipulation, simplify the following Boolean expressions to a minimum number of literals: (a) A + BC + (B + C)(B + A) (b) A + ABC + B (c) AB D(A + BD) + DA + B C(d) (XY) + X Y + Z(X + YZ) + X Y 4. Using only the theory of Boolean algebra and algebraic manipulation, simplify the following Boolean expressions to a minimum number of literals: (a) X + XYZ + (Y + Z)(Y + X) (b) A + ABC + BC (c) XY Z(W + Y Z) + ZW + X Y (d) (XY) + XY + Z(X + YZ) + X Y (e) WXYZ + WXYZ + WX YZ + WXY Z 5. A particular applications requires a 6 input NAND gate. You only have available an unlimited number of 2 input NAND gates. Using these gates find a design for the 6 input NAND.

Version 6.3/26/11 For Academic Use Only. All Rights Reserved

Notes:

Top

Karnaugh Maps

2.22

Karnaugh or K-maps are a form of truth table where (for small numbers of variables!) the minimisation of a standard SOP Boolean expression is easy to see.
CD AB 00 01 00 01 11 10

1 1

1 1 1 1

ABCD + ABCD = ACD ( B + B ) = ACD ACD + ACD = AC

ABCD + ABCD = ABC ( D + D ) = ABC

11 10

Adjacent squares only differ by one variable. Hence we can group vertically or horizontally neighbouring squares (or pairs of squares,.....) and eliminate one variable.
Distributed by: http://www.xilinx.com/univ/ Developed by:

K-Map Example
Y ( A, B, C, D ) = ( 0, 2, 6, 9, 11, 13, 15 ) Y = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD + ABCD
CD AB 00 00 01 11 10 01 11 10

Top

2.23

ABD

1 0 0 0

0 0 1 1

0 0 1 1 AD

1 1 0 0 ACD

Y = AD + ABD + ACD

Version 6.3/26/11 For Academic Use Only. All Rights Reserved

Notes:

Top

5 Variable K-Map
ABCD ( E + E ) = ABCD CD CD
01 11 10

2.24

AB
00 01 11 10

00

AB
00 01 11 10

00

01

11

10

1 -

1 -

E = 0

E = 0

Above 5 variable K-map is difficult to use and we should revert to formal methods.
Distributed by: http://www.xilinx.com/univ/ Developed by:

Combinational Logic
A B C A B C A B A B C A B C A B

Top

2.25

The NAND gate can be conveniently used to represent SOP Boolean expressions.

Y = ABC + ABC + AB

Y = ( ABC ) ( ABC ) ( AB )

Transformation achieved by using De-Morgans law: X + Y = XY

Version 6.3/26/11 For Academic Use Only. All Rights Reserved

Notes:

Top

NAND Only Implementation

2.26

Arbitrary logic circuits can be converted to NAND only using Boolean algebraic manipulation, or the somewhat easier graphical manipulation where pairs of inverters are added appropriately. We convert the following circuit to NAND only:
A B C D E A B C D E
Distributed by: http://www.xilinx.com/univ/

Developed by:

Examples

Top

2.27

6. For each of the following functions give (i) the Karnaugh map representation, (ii) the truth table representation, and (iii) the circuit diagram representation: (a)H(W,X,Y,Z) = (1,3,5,7,9,11) (b)F(X,Y,Z) = X Y + Y Z + XYZ (c) G(R,S,T) = (R + S)(S + T) + R(ST + T) 7. Convert the following circuit to (a) a NAND gate only implementation, and (b) a NOR gate only implementation. (Simply add pairs of inverters where appropriate.) Confirm your answers by an algebraic analysis of the circuit.

A B C D E Z

Version 6.3/26/11 For Academic Use Only. All Rights Reserved

Notes:

Top

MSI Components - The Full Adder (FA)

2.28

Arithmetic is workhorse of most digital systems. The simple Full Adder (FA): Adds two bits + one carry in bit, to produce sum and carry out A B Cin Cout Sout S out = ABC + ABC + ABC + ABC 0 0 0 0 0 = ABC 1 0 0 1 0 C out = ABC + ABC + ABC + ABC 1 0 1 0 0 0 = AB + AC + BC 0 1 1 1 1 1 0 0 0 A B 0 1 0 1 1 0 1 1 0 1 Cin Cout 1 1 1 1 1 Sout

Distributed by: http://www.xilinx.com/univ/

Developed by:

Parallel Adder
A3 B3 A2 B2 A1 B1 A0 B0

Top

2.29

C3 S4 MSB

S3

C2

S2

C1

S1

C0

S0 LSB

A3 A2 A1 A0 + B3 B2 B1 B0
C3 C2 C1 C0

S4 S3 S2 S1 S0
Gate Count: 4 x 6 two input gates per FA cell.

0 carry in

Two four bit numbers (range 0-15) give up to five bit result (0-30).

Version 6.3/26/11 For Academic Use Only. All Rights Reserved

Notes:

Top

Parallel Adder Latency

2.30

The parallel adder is also known as a carry-ripple (through) adder. In the worst case where a carry ripples from the LSB to the MSB (consider 0001 + 1111 = 10000) then the digit S4 is only valid after 4 FA delays, i.e. 4 FA 1 1 1 0 1 1 0 1 1 0 1 1 1 0

0 FA

0 FA

0 FA

0 FA

A carry lookahead adder can be used to speed up the carry ripply by designing few gate delays is the carry propagation line. However this requires more hardware/gates.
Distributed by: http://www.xilinx.com/univ/ Developed by:

Parallel Subtractor I
Invert all bits then add 1 E.g. for 8 bit 2complement: and 3 = 0000 0011 -3 = 1111 1100 +1 = 1111 1101

Top

2.31

Using 2s complement a number can be negated by the process of:

Performing this process with the parallel adder input circuitry produces a subtractor D = A B = A + ( B ) 4 bit 2s comp A3 B3 A2 B2 A1 B1 A0 B0 Invert add 1 1

Discard

C4

D3

D2

D1

D0

Version 6.3/26/11 For Academic Use Only. All Rights Reserved

Notes:

Top

Parallel Subtractor II

2.32

For an N bit subtractor, constrained to N bit 2s complement results. Overflow can be easily checked by noting the sign bits A3 and B3, and checking that the result is consistent. e.g. if adding two +ve values gives -ve result - overflow. Can combine adder and subtractor to give controllable circuit K = 1 Subtract, & K = 0 Add. (K - Kontrol bit) A3
0 MUX

B3
1

A2

B2
0 1 MUX

A1

B1
0 1 MUX

A0

B0
0 1 MUX

Distributed by: http://www.xilinx.com/univ/

Developed by:

Serial Adder
A0 A1 A2 B0 B1 B2
0 1 MUX

Top

2.33

We can save on hardware, but increase latency time by using a synchronous serial adder:
.... ....

AN-1 BN-1

K= 0 or 1 (add or subtract)

Latency = N x tclk

S0 S1 S2
Delay ....

SN-1
time

Prime with K= 0 or 1

tclk

clk
time

Version 6.3/26/11 For Academic Use Only. All Rights Reserved

Notes:

Top

Binary Multiplication
1011 1001 1011 0000 0000 +1 0 1 1 1100011 11 x9 a3 a2 a1 a0 b3 b2 b1 b0 c3 c2 c1 c0 d3 d2 d1 d0 e3 e2 e1 e0 f3 f2 f1 f0 p7 p6 p5 p4 p3 p2 p1 p0

2.34

Consider the 4 bit multiply operations:

99

This can be mapped to produce a full parallel adder where the partial products, C, D, E, and F are each produced and added to the previous partial product sum i.e. C+D, then (C+D) + E, then (C+D+E) + F
Developed by:

Distributed by: http://www.xilinx.com/univ/

Parallel Multiplier Circuit


s bout cout aout
FA is full adder

Top

2.35

FA

b c

Binary Multiplier: P = A x B
0

a3

a2

a1

a0
0

sout b1
0

b0

cout = z.c + s.z + s.c sout = (s z) c aout = a bout = b z = a.b b3


0

b2
0

p7

p6

p5

p4

p3

p2

p1

p0

The dotted path shows the maximum latency.

Version 6.3/26/11 For Academic Use Only. All Rights Reserved

Notes:

Top

Serial Multiplier Circuit


0

2.36
0

a3

a2

a1

a0 b0
0

timing cuts b1
0

b2
0

b3
0

Projection direction

a3

a2

a1

a0 b0 b1 b2 b3
0

One clock Delay

pi
Distributed by: http://www.xilinx.com/univ/ Developed by:

Flip Flops

Top

2.37

Introducing feedback into a circuit, introduces the possibility that current output/state (at time, t) can influence the next output/state (at time t+). This produces a sequential system. Feedback at the device level is integrated via standard flip-flops. Simple form of memory element in the SR (Set/Reset) latch: S R Q(t) Q(t+) R Q 0 0 0 0 1 0 0 1 Q 0 0 1 0 S 0 0 1 1 1 1 0 0 Q ( t + ) = S + RQ ( t ) SR 1 1 1 0 1 1 1 0 Not allowed by Characteristic Equation definition of S and R 1 1 1
Version 6.3/26/11 For Academic Use Only. All Rights Reserved

Notes:

Top

Gated SR Latch

2.38

Can set up an Enable (EN) line that only allows the inputs to be latched when EN = 1: R EN S Q

S EN R

Q Q

Symbol
Distributed by: http://www.xilinx.com/univ/ Developed by:

Gated D Latch

Top

2.39

Connecting together S and R as shown, we can produced a data or Dtype latch: D EN Q

D Q(t) Q(t+) 0 0 1 1 0 1 0 1 0 0 1 1
EN

Q Q

Symbol

Version 6.3/26/11 For Academic Use Only. All Rights Reserved

Notes:

Top

Edge Triggered Flip Flops

2.40

Enabled latches/FFs are transparent when EN = 1. It is desirable to make the FFs more edge triggered, with a specific (but small) set up time and hold time. A simple model of an edge detector that could be used at the EN (enable) input of a latch is:
Propagation delay of inverter, inv

time Edge Detect clk


F

clk 0
Distributed by: http://www.xilinx.com/univ/

time

0
Developed by:

time

Positive Edge Triggered D-type

Top

2.41

Using an edge detector circuit we can produce a positive edge (+ve) triggered D type FF: D
clk Edge Detect

Q Q

D Q(t) Q(t+) 0 0 1 1 0 1 0 1 0 0 1 1
clk

Q Q

Symbol

Version 6.3/26/11 For Academic Use Only. All Rights Reserved

Notes:

Top

Negative Edge Triggered D-type

2.42

Using an edge detector circuit we can also produce a positive edge (+ve) triggered D-type FF: D
clk Edge Detect

Q Q

D Q(t) Q(t+) 0 0 1 1 0 1 0 1 0 0 1 1
clk

Q Q

Symbol
Developed by:

Distributed by: http://www.xilinx.com/univ/

JK Flip Flop

Top

2.43

The JK flip flop (J - SET, K - Klear) is similar to the SR, expect that the condition of J = K = 1 has a defined operation. J = K = 1 then FF output will toggle (from state 0 to 1 or 1 to 0). The J and K inputs are synchronous (controlled by the clock): J K Q(t) Q(t+) J Q 0 0 0 0 clk 1 0 0 1 K Q 0 0 1 0 0 0 1 1 Symbol 1 1 0 0 1 1 0 1 Q ( t + ) = JQ ( t ) + KQ ( t ) 1 1 1 0 Characteristic Equation 0 1 1 1

Version 6.3/26/11 For Academic Use Only. All Rights Reserved

Notes:

Top

JK Asynchronous Inputs

2.44

The JK often has two asynchronous inputs (i.e. not controlled or affected by the clock input):

Preset J PQ clk K CQ (Pre)Clear


Asserted LO inputs, e.g. P = 0 forces Q = 1, C = 0 forces Q = 0 regardless of clk input.
Distributed by: http://www.xilinx.com/univ/ Developed by:

Flip Flop Key Operating Characteristics


t plh LO to HI propagation delay t phl HI to LO propagation delay Minimum pulse width for clock, preset, preclear

Top

2.45

Setup and hold times are defined for edge triggered FFs. Inputs must be held fixed during t setup and t hold or output is likely to be unpredictable. clk J
0 OK 0 Setup Violation time

t setup

Q
0

t hold
??????

time

t plh

time

Version 6.3/26/11 For Academic Use Only. All Rights Reserved

Notes:

Top

Metastability

2.46

A flip-flop enters a metastable state when its timing requirements (setup and hold times) are violated
Setup Time Active Clock Edge Hold Time

Clock No violations Setup violation Hold violation 0 0 M 0 M 1 0 ? ?

Clock
Data must not change during setup and hold times. A period of metastability follows a setup or hold violation. The output then settles to a random value.

The period of metastability lasts for a short time and then a 0 or 1 output is settled upon... however... The value of this output is non deterministic - which can potentially destroy the functionality of the entire design!
Distributed by: http://www.xilinx.com/univ/ Developed by:

Metastability Details

Top

2.47

While in the metastable state, the voltage may be somewhere between those required for the two valid states. Another possibility is for the output to oscillate between the two states for some period of time. In both cases, the period of metastability ends with one of the two valid states... however the eventual output value may be incorrect. The time taken to resolve the eventual output (correctly or otherwise!) also constitutes an extra and undesirable delay in the output. Metastability is encountered when dealing with signals which are asynchronous to the clock. Some areas which are potentially vulnerable to metastability effects are: External inputs Crossing clock domains Resets

Version 6.3/26/11 For Academic Use Only. All Rights Reserved

Notes:

Top

Metastability Solutions

2.48

Prior to applying an asynchronous input to a synchronous system, one or more synchronising flip-flops may be used. A common approach is to use two cascaded flip-flops to reduce the chance of metastability. In this case Y, a potentially metastable output from Flip-flop A, should have settled down before Flip-flop B samples it.
Synchroniser Asynchronous Input

Z
Synchronous Design

Clock

There is still some small chance of failure, which is calculable.


Distributed by: http://www.xilinx.com/univ/ Developed by:

JK for Frequency Division


The JK can be used for simple frequency division Setting J = K = 1 (toggle mode): 1 clk 1 K Q
Q 0 0

Top

2.49

clk 0 0 1 0 1 time 1 0 1 0 1 0 time

Input clock frequency is divided by 2.

Version 6.3/26/11 For Academic Use Only. All Rights Reserved

Notes:

Top

Ripple or Asynchronous Counter


D 1 J K C 1 1 J K B 1 1 J K

2.50

Cascade JKs in toggle mode to produce a 0-15 ripple counter:


A 1 1 J K

Q Q

Q Q

Q Q

Q Q

clk 1

Fill in the timing diagram: clk LSB D C B MSB A


Distributed by: http://www.xilinx.com/univ/ Developed by:

time

State Diagram
The state diagram for the above 0-15 counter is (state = ABCD)
1111 1110 1101 0100 1100 0101 1011 1010 1001 1000 0111 0110 0000 0001 0010 0011

Top

2.51

Version 6.3/26/11 For Academic Use Only. All Rights Reserved

Notes:

Top

Count Direction
D 1 J K C 1 1 J K B 1 1 J K

2.52

Using +ve edge triggers gives a downcounter for ABCD:


A 1 1 J K

Q Q

Q Q

Q Q

Q Q

clk 1

Fill in the timing diagram: clk D C B A


Distributed by: http://www.xilinx.com/univ/ Developed by:

time

Transition States
A B C

Top

2.53

Because this type of counter is asynchronous (i.e. no sync clock for all FFs) then due to propagation delay there will be transition states: Q Q
Duration of transition states function of propagation delay

J K

1 1
110

Q Q
100

J K

1 1

Q Q

J K

1 clk 1

000 001
000

111

110 101 100


000

010

100

011
010

Version 6.3/26/11 For Academic Use Only. All Rights Reserved

Notes:

Top

Resettable Decade Counter


D 1 J K C 1 1 J K B 1 1 J K

2.54

On reaching state ABCD = 1010 (ten) then the counter resets to zero.
A 1 1 J K

Q Q

Q Q

Q Q

Q Q

clk 1

A C

Problems? Transitions states, and reset state (1010 exists for a very short time).
Distributed by: http://www.xilinx.com/univ/ Developed by:

You might also like