Lecture Notes

UNIT-1
Microprocessor notes
Prepared by- Girraj Sharma
UNIT-1
Central processing unit (CPU)
The central processing unit (CPU) is the portion of a computer system that carries out the instructions of a computer program, to perform the basic arithmetical, logical, and input/output operations of the system. The CPU plays a role somewhat analogous to the brain in the computer. The term has been in use in the computer industry at least since the early 1960s.[1] The form, design and implementation of CPUs have changed dramatically since the earliest examples, but their fundamental operation remains much the same. On large machines, CPUs require one or more printed circuit boards. On personal computers and small workstations, the CPU is housed in a single silicon chip called a microprocessor. Since the 1970s the microprocessor class of CPUs has almost completely overtaken all other CPU implementations. Modern CPUs are large scale integrated circuits in packages typically less than four centimeters square, with hundreds of connecting pins. Two typical components of a CPU are the arithmetic logic unit (ALU), which performs arithmetic and logical operations, and the control unit (CU), which extracts instructions from memory and decodes and executes them, calling on the ALU when necessary. Not all computational systems rely on a central processing unit. An array processor or vector processor has multiple parallel computing elements, with no one unit considered the "center". In the distributed computing model, problems are solved by a distributed interconnected set of processors.
Control unit
The control unit of the CPU contains circuitry that uses electrical signals to direct the entire computer system to carry out stored program instructions. The control unit does not execute program instructions; rather, it directs other parts of the system to do so. The control unit must communicate with both the arithmetic/logic unit and memory.
Buses
All of the basic components of the computer are tied together by communications paths called buses. A computer bus is simply a parallel collection of conductors that carry data and control signals from one unit to another.
Types of Buses Any computer has three major system buses identified by the type of information they carry. The three major system buses are: Address bus, Data bus, Control bus. These buses are actually extensions of the microprocessor's internal communications structures. Address Bus The address bus is a unidirectional pathway that carries addresses generated by the microprocessor to the memory and I/O elements of the computer. The size of the address bus, determined by the number of conductors in the bus, determines the number of memory locations and/or I/O elements the microprocessor can address. Address Bus Size If the address bus is composed of 16 lines (or bits), the microprocessor can generate 65,536 (2 to the power of 16) distinct address codes. If the address bus size is increased to a 20-bit word size, the microprocessor's capability to address memory and I/O elements is increased to 1,048,576 (2 to the power of 20) possible addresses. Addressing Capacity When discussing addressing capacity, it is common to use the letter "K" (for kilo) to represent 1024 (2 to the power of 10) addresses. Using this terminology, the 16-bit bus example is capable of
addressing up to 64 KB of memory, while the 20-bit bus is capable of directly addressing up to 1,000 KB of memory. 1,000 KB of memory is referred to as a megabyte of memory and is denoted by the letter "M" (MB for megabytes). Address Codes When the microprocessor wishes to access a memory location (to perform a Read or Write operation), it does so by placing the appropriate address code on its address pins and generating the proper control signals to perform the operation. The microprocessor uses the same process to access an input or outputelement.
Decoding Circuitry
Because the memory unit is normally composed of several memory chips (RAM and ROM), special decoding circuitry is required to select the proper IC and then single out the proper memory location, the input or output device that the microprocessor is trying to address.
Data Bus
In contrast to the address bus, the data bus is bi-directional in nature. Data flows along the data bus from the microprocessor to memory during a Write operation. Conversely, data moves from memory to the microprocessor during a Read operation. The direction for data movement is the same for Read and Write operations between the microprocessor and Input/Output devices. Sharing the Data Bus Because all the computer elements must share the data bus, any device connected to the bus must have the capability to put its outputs in a high impedance state (floating) when not involved in an operation with the microprocessor. This prevents data from having more than one source placed on the bus at one time. Data Bus Size If two devices attempt to place data on the bus at the same time, confusion and damage to the devices results. The size of the data bus usually corresponds to the word size of the computer. In general, the larger the data bus, the more powerful the system.8-16-32 bits.
Control Bus
The control bus carries the timing and control signals necessary to coordinate the activities of the entire system. Unlike the other two buses, the control bus signals are not necessarily related to each other. Some are output signals from the microprocessor, others are input signals to the microprocessor from Input and Output elements. Each different microprocessor type has its own unique set of control signals, which it can generate or respond to. Types of Control Signals Many control bus signals are common to most microprocessors (or similar to those used by most processors). The following are the more common control signals in use today: System Clock (SYSCLK) Read/Write Line (R/W Line)
Microprocessor notes Prepared by- Girraj Sharma
Memory Read (MEMR) Memory Write (MEMW) I/O Read (IOR), I/O Write (IOW) Clock Control Signal One of the most important control signals in any microprocessor-based system is the system clock. This signal provides the timing information for all the system's activities. Clock signals may be generated on the microprocessor chip, or by special IC signal generators. Microprocessors with internal clock generators usually require that an external crystal be connected to their clock input pins. Read and Write Signals The control bus also carries the signals that enable selected memory or I/O elements for Read and Write operations. These signals may range from a simple Read/Write line (R/W) to a collection of signals such as Memory Read (MEMR), Memory Write (MEMW), I/O Read (IOR), and I/O Write (IOW). These signals are used by the microprocessor in conjunction with addresses on the address bus to perform Read and Write operations at selected memory or I/O locations. The Intel 8085 is an 8-bit microprocessor introduced by Intel in 1977. It was binary-compatible with the more-famous Intel 8080 but required less supporting hardware, thus allowing simpler and less expensive microcomputer systems to be built. The "5" in the model number came from the fact that the 8085 requires only a +5-volt (V) power supply rather than the +5V, 5V and +12V supplies the 8080 needed. Both processors were sometimes used in computers running the CP/M operating system, and the 8085 also saw use as a microcontroller, by virtue of its low component count. Both designs were eclipsed for desktop computers by the compatible Zilog Z80, which took over most of the CP/M computer market as well as taking a share of the booming home computer market in the early-to-mid-1980s. The 8085 had a long life as a controller. Once designed into such products as the DECtape controller and the VT100 video terminal in the late 1970s, it continued to serve for new production throughout the life span of those products (generally longer than the product life of desktop computers)
8085 architecture.
The 8085 is a conventional von Neumann design based on the Intel 8080. Unlike the 8080 it does not multiplex state signals onto the data bus, but the 8-bit data bus was instead multiplexed with the lower part of the 16-bit address bus to limit the number of pins to 40. Pin No. 40 is used for the power supply (+5v) and pin No. 20 for ground. Pin No. 39 is used as the hold pin. Pins No. 15 to No. 8 are generally used for address buses. The processor was designed using nMOS circuitry and the later "H" versions were implemented in Intel's enhanced nMOS process called HMOS, originally developed for fast static RAM products. Only a 5 Volt supply is needed, like competing processors and unlike the 8080. The 8085 uses approximately 6,500 transistors. The 8085 incorporates the functions of the 8224 (clock generator) and the 8228 (system controller), increasing the level of integration. A downside compared to similar contemporary designs (such as the Z80) was the fact that the buses required demultiplexing; however, address latches in the Intel 8155, 8355, and 8755 memory chips allowed a direct interface, so an 8085 along with these chips was almost a complete system. The 8085 has extensions to support new interrupts, with three maskable interrupts (RST 7.5, RST 6.5 and RST 5.5), one non-maskable interrupt (TRAP), and one externally serviced interrupt (INTR). The RST n.5 interrupts refer to actual pins on the processor, a feature which permitted simple systems to avoid the cost of a separate interrupt controller. Like the 8080, the 8085 can accommodate slower memories through externally generated wait states (pin 35, READY), and has provisions for Direct Memory Access (DMA) using HOLD and HLDA signals (pins 39 and 38). An improvement over the 8080 was that the 8085 can itself drive a piezoelectric crystal directly connected to it, and a built in clock generator generates the internal high amplitude two-phase clock signals at half the crystal frequency (a 6.14 MHz crystal would yield a 3.07 MHz clock, for instance). The 8085 is a binary compatible follow up on the 8080, using the same basic instruction set as the 8080. Only a few minor instructions were new to the 8085 above the 8080 set.
Programming model
The processor has seven 8-bit registers accessible to the programmer, named A, B, C, D, E, H, and L, where A is the 8-bit accumulator and the other six can be used as independent byte-registers or as three 16-bit register pairs, BC, DE, and HL, depending on the particular instruction. Some instructions use HL as a (limited) 16-bit accumulator. As in the 8080, the contents of the memory address pointed to by HL could be accessed as pseudoregister M. It also has a 16-bit stack pointer to memory (replacing the 8008's internal stack), and a 16-bit program counter. HL pair is called the primary data pointers.
Commands/instructions
As in many other 8-bit processors, all instructions are encoded in a single byte (including registernumbers, but excluding immediate data), for simplicity. Some of them are followed by one or two bytes of data, which could be an immediate operand, a memory address, or a port number. Like larger processors, it has CALL and RET instructions for multi-level procedure calls and returns (which can be conditionally executed, like jumps) and instructions to save and restore any 16-bit register-pair on the machine stack. There are also eight one-byte call instructions (RST) for subroutines located at the fixed addresses 00h, 08h, 10h,...,38h. These were intended to be supplied by external hardware in order to invoke a corresponding interrupt-service routine, but are also often employed as fast system calls. The most sophisticated command was XTHL, which is used for exchanging the register pair HL with the value stored at the address indicated by the stack pointer.
8-bit instructions
Most 8-bit operations work on the 8-bit accumulator (the A register). For two operand 8-bit operations, the other operand can be either an immediate value, another 8-bit register, or a memory cell addressed by the 16-bit register pair HL. Direct copying is supported between any two 8-bit registers and between any 8-bit register and a HL-addressed memory cell. Due to the regular encoding of the MOV-instruction (using a quarter of available opcode space) there are redundant codes to copy a register into itself (MOV B,B, for instance), which are of little use, except for delays. However, what would have been a copy from the HL-addressed cell into itself (i.e., MOV M,M) instead encodes the HLT instruction, halting execution until an external reset or interrupt occurred.
16-bit operations
Although the 8085 is an 8-bit processor, it also has some 16-bit operations. Any of the three 16-bit register pairs (BC, DE, HL) or SP could be loaded with an immediate 16-bit value (using LXI), incremented or decremented (using INX and DCX), or added to HL (using DAD). LHLD loaded HL from directly-addressed memory and SHLD stored HL likewise. The XCHG operation exchanges the values of HL and DE. Adding HL to itself performs a 16-bit arithmetical left shift with one instruction. The only 16 bit instruction that affects any flag was DAD (adding HL to BC, DE, HL or SP), which updates the carry flag to facilitate 24-bit or larger additions and left shifts (for a floating point mantissa for instance). Adding the stack pointer to HL is useful for indexing variables in (recursive) stack frames. A stack frame can be allocated using DAD SP and SPHL, and a branch to a computed pointer can be done with PCHL. These abilities make it feasible to compile languages such as PL/M, Pascal, or C with 16-bit variables and produce 8085 machine code. Subtraction and bitwise logical operations on 16 bits is done in 8-bit steps. Operations that have to be implemented by program code (subroutine libraries) included comparisons of signed integers as well as multiply and divide.
Input/output scheme
The 8085 supported up to 256 input/output (I/O) ports, accessed via dedicated Input/Output instructionstaking port addresses as operands. This Input/Output mapping scheme was regarded as an advantage, as it freed up the processor's limited address space.
Development system
Intel produced a series of development systems for the 8080 and 8085, known as the MDS-80 Microprocessor System. The original development system had an 8080 processor. Later 8085 and 8086 support was added including ICE (in-circuit emulators). It was a large and heavy desktop box, about a 20" cube (in the Intel corporate blue colour) which included a CPU, monitor, and a single 8 inch floppy disk drive. Later an external box was available with two more floppy drives. It ran the ISIS operating system and could also operate an emulator pod and an external EPROM programmer. This unit used the Multibus card cage which was intended just for the development system. A surprising number of spare card cages and processors were being sold, leading to the development of the Multibus as a separate product.
The later iPDS was a portable unit, about 8" x 16" x 20", with a handle. It had a small green screen, a keyboard built into the top, a 5 inch floppy disk drive, and ran the ISIS-II operating system. It could also accept a second 8085 processor, allowing a limited form of multi-processor operation where both processors ran simultaneously and independently. The screen and keyboard could be switched between them, allowing programs to be assembled on one processor (large programs took awhile) while files were edited in the other. It had a bubble memory option and various programming modules, including EPROM and Intel 8048 and 8051 programming modules which were plugged into the side, replacing stand-alone device programmers. In addition to an 8080/8085 assembler, Intel produced a number of compilers including PL/M-80 and Pascal languages, and a set of tools for linking and statically locating programs to enable them to be burnt into EPROMs and used in embedded systems.
Volatile memory
Volatile memory is computer memory that requires power to maintain the stored information. Most modern semiconductor volatile memory is either Static RAM (see SRAM) or dynamic RAM (see DRAM). SRAM retains its contents as long as the power is connected and is easy to interface to but uses six transistors per bit. Dynamic RAM is more complicated to interface to and control and needs regular refresh cycles to prevent its contents being lost. However, DRAM uses only one transistor and a capacitor per bit, allowing it to reach much higher densities and, with more bits on a memory chip, be much cheaper per bit. SRAM is not worthwhile for desktop system memory, where DRAM dominates, but is used for their cache memories. SRAM is commonplace in small embedded systems, which might only need tens of kilobytes or less. Forthcoming volatile memory technologies that hope to replace or compete with SRAM and DRAM include Z-RAM, TTRAM, A-RAM and ETA RAM.
Non-volatile memory
Non-volatile memory is computer memory that can retain the stored information even when not powered. Examples of non-volatile memory include read-only memory (see ROM), flash memory, most types of magnetic computer storage devices (e.g. hard disks, floppy discs and magnetic tape), optical discs, and early computer storage methods such as paper tape and punched cards. Forthcoming non-volatile memory technologies include FeRAM, CBRAM, PRAM, SONOS, RRAM, Racetrack memory, NRAM and Millipede.
Read-only memory (ROM) is a class of storage medium used in computers and other electronic devices. Data stored in ROM cannot be modified, or can be modified only slowly or with difficulty, so it is mainly used to distribute firmware (software that is very closely tied to specific hardware, and unlikely to need frequent updates). In its strictest sense, ROM refers only to mask ROM (the oldest type of solid state ROM), which is fabricated with the desired data permanently stored in it, and thus can never be modified. Despite the simplicity, speed and economies of scale of mask ROM, field-programmability often make reprogrammable memories more flexible and inexpensive. As of 2007, actual ROM circuitry is therefore mainly used for applications such as microcode, and similar structures, on various kinds of digital processors (i.e. not only CPUs). Other types of non-volatile memory such as erasable programmable read only memory (EPROM) and electrically erasable programmable read-only memory (EEPROM or Flash ROM) are sometimes referred to, in an abbreviated way, as "read-only memory" (ROM), but this is actually a misnomer because these types of memory can be erased and re-programmed multiple times[1]. When used in this less precise way, "ROM" indicates a non-volatile memory which serves functions typically provided by mask ROM, such as storage of program code and nonvolatile data. Classic mask-programmed ROM chips are integrated circuits that physically encode the data to be stored, and thus it is impossible to change their contents after fabrication. Other types of non-volatile solid-state memory permit some degree of modification: Programmable read-only memory (PROM), or one-time programmable ROM (OTP), can be written to or programmed via a special device called a PROM programmer. Typically, this device uses high voltages to permanently destroy or create internal links (fuses or antifuses) within the chip. Consequently, a PROM can only be programmed once. Erasable programmable read-only memory (EPROM) can be erased by exposure to strong ultraviolet light (typically for 10 minutes or longer), then rewritten with a process that again needs higher than usual voltage applied. Repeated exposure to UV light will eventually wear out an EPROM, but the endurance of most EPROM chips exceeds 1000 cycles of erasing and reprogramming. EPROM chip packages can often be identified by the prominent quartz "window" which allows UV light to enter. After programming, the window is typically covered with a label to prevent accidental erasure. Some EPROM chips are factory-erased before they are packaged, and include no window; these are effectively PROM.
Electrically erasable programmable read-only memory (EEPROM) is based on a similar semiconductor structure to EPROM, but allows its entire contents (or selected banks) to be electrically erased, then rewritten electrically, so that they need not be removed from the computer (or camera, MP3 player, etc.). Writing or flashing an EEPROM is much slower (milliseconds per bit) than reading from a ROM or writing to a RAM (nanoseconds in both cases). Electrically alterable read-only memory (EAROM) is a type of EEPROM that can be modified one bit at a time. Writing is a very slow process and again needs higher voltage (usually around 12 V) than is used for read access. EAROMs are intended for applications that require infrequent and only partial rewriting. EAROM may be used as non-volatile storage for critical system setup information; in many applications, EAROM has been supplanted by CMOS RAM supplied by mains power and backed-up with a lithium battery.
Flash memory (or simply flash) is a modern type of EEPROM invented in 1984. Flash memory can be erased and rewritten faster than ordinary EEPROM, and newer designs feature very high endurance (exceeding 1,000,000 cycles). Modern NAND flash makes efficient use of silicon chip area, resulting in individual ICs with a capacity as high as 32 GB as of 2007; this feature, along with its endurance and physical durability, has allowed NAND flash to replace magnetic in some applications (such as USB flash drives). Flash memory is sometimes called flash ROM or flash EEPROM when used as a replacement for older ROM types, but not in applications that take advantage of its ability to be modified quickly and frequently
Decoders
A decoder is a multiple-input, multiple-output logic circuit that converts coded inputs into coded outputs, where the input and output codes are different; e.g. n-to-2n, BCD decoders.
Enable inputs must be on for the decoder to function, otherwise its outputs assume a single "disabled" output code word.
Decoding is necessary in applications such as data multiplexing, 7 segment display and memory address decoding. Figure below shows the pseudo block of a decoder.
Basic Binary Decoder
And AND gate can be used as the basic decoding element, because its output is HIGH only when all its inputs are HIGH. For example, if the input binary number is 0110, then, to make all the inputs to the AND gate HIGH, the two outer bits must be inverted using two inverters as shown in figure below.
Binary n-to-2n Decoders
A binary decoder has n inputs and 2n outputs. Only one output is active at any one time, corresponding to the input value. Figure below shows a representation of Binary n-to-2n decoder
Example - 2-to-4 Binary Decoder
A 2 to 4 decoder consists of two inputs and four outputs, truth table and symbols of which is shown below.
Truth Table X 0 0 1 1 Y 0 1 0 1 F0 1 0 0 0 F1 0 1 0 0 F2 0 0 1 0 F3 0 0 0 1
Symbol
To minimize the above truth table we may use kmap, but doing that you will realize that it is a waste of time. One can directly write down the function for each of the outputs. Thus we can draw the circuit as shown in figure below.
Note: Each output is a 2-variable minterm (X'Y', X'Y, XY', XY)
Circuit
Example - 3-to-8 Binary Decoder
A 3 to 8 decoder consists of three inputs and eight outputs, truth table and symbols of which is shown below.
Truth Table X 0 0 0 0 1 1 1 1 Y 0 0 1 1 0 0 1 1 Z 0 1 0 1 0 1 0 1 F0 1 0 0 0 0 0 0 0 F1 0 1 0 0 0 0 0 0 F2 0 0 1 0 0 0 0 0 F3 0 0 0 1 0 0 0 0 F4 0 0 0 0 1 0 0 0 F5 0 0 0 0 0 1 0 0 F6 0 0 0 0 0 0 1 0 F7 0 0 0 0 0 0 0 1
Symbol
From the truth table we can draw the circuit diagram as shown in figure below.
Implementing Functions Using Decoders

Any n-variable logic function, in canonical sum-of-minterms form can be implemented using a single n-to-2n decoder to generate the minterms, and an OR gate to form the sum.
The output lines of the decoder corresponding to the minterms of the function are used as inputs to the or gate.
Any combinational circuit with n inputs and m outputs can be implemented with an n-to-2n decoder with m OR gates.
Suitable when a circuit has many outputs, and each output function is expressed with few minterms. Encoders
An encoder is a combinational circuit that performs the inverse operation of a decoder. If device output code has fewer bits than the input code has, the device is usually called an encoder. e.g. 2n-to-n, priority encoders.
The simplest encoder is a 2n-to-n binary encoder, where it has only one of 2n inputs = 1 and the output is the n-bit binary number corresponding to the active input.
Example - Octal-to-Binary Encoder
Octal-to-Binary take 8 inputs and provides 3 outputs, thus doing the opposite of what the 3
to-8 decoder does. At any one time, only one input line has a value of 1. The figure below shows the truth table of an Octal-to-binary encoder.
Truth Table
I0 1 0 0 0 0 0 0 0
I1 0 1 0 0 0 0 0 0
I2 0 0 1 0 0 0 0 0
I3 0 0 0 1 0 0 0 0
I4 0 0 0 0 1 0 0 0
I5 0 0 0 0 0 1 0 0
I6 0 0 0 0 0 0 1 0
I7 0 0 0 0 0 0 0 1
Y2 0 0 0 0 1 1 1 1
Y1 0 0 1 1 0 0 1 1
Y0 0 1 0 1 0 1 0 1
For an 8-to-3 binary encoder with inputs I0-I7 the logic expressions of the outputs Y0-Y2 are:
Y0 = I1 + I3 + I5 + I7 Y1= I2 + I3 + I6 + I7 Y2 = I4 + I5 + I6 +I7
Based on the above equations, we can draw the circuit as shown below
Circuit
Example - Decimal-to-Binary Encoder
Decimal-to-Binary take 10 inputs and provides 4 outputs, thus doing the opposite of what the 4-to-10 decoder does. At any one time, only one input line has a value of 1. The figure below shows the truth table of a Decimal-to-binary encoder.
Truth Table
I0 1 0 0 0 0 0 0 0 0
I1 0 1 0 0 0 0 0 0 0
I2 0 0 1 0 0 0 0 0 0
I3 0 0 0 1 0 0 0 0 0
I4 0 0 0 0 1 0 0 0 0
I5 0 0 0 0 0 1 0 0 0
I6 0 0 0 0 0 0 1 0 0
I7 0 0 0 0 0 0 0 1 0
I8 0 0 0 0 0 0 0 0 1
I9 0 0 0 0 0 0 0 0 0
Y3 0 0 0 0 0 0 0 0 1
Y2 0 0 0 0 1 1 1 1 0
Y1 0 0 1 1 0 0 1 1 0
Y0 0 1 0 1 0 1 0 1 0
From the above truth table , we can derive the functions Y3, Y2, Y1 and Y0 as given below.
Y3 = I8 + I9 Y2 = I4 + I5 + I6 + I7 Y1 = I2 + I3 + I6 + I7 Y0 = I1 + I3 + I5 + I7 + I9
Latches and Flip-Flops
There are two types types of sequential circuits.

Asynchronous Circuits. Synchronous Circuits.
As seen in last section, Latches and Flip-flops are one and the same with a slight variation: Latches have level sensitive control signal input and Flip-flops have edge sensitive control signal input. Flip-flops and latches which use this control signals are called synchronous circuits. So if they don't use clock inputs, then they are called asynchronous circuits.
D Latch
The RS latch seen earlier contains ambiguous state; to eliminate this condition we can ensure that S and R are never equal. This is done by connecting S and R together with an
inverter. Thus we have D Latch: the same as the RS latch, with the only difference that there is only one input, instead of two (R and S). This input is called D or Data input. D latch is called D transparent latch for the reasons explained earlier. Delay flip-flop or delay latch is another name used. Below is the truth table and circuit of D latch.
In real world designs (ASIC/FPGA Designs) only D latches/Flip-Flops are used.
D 1 0
Q X X
Q+ 1 0
Below is the D latch waveform, which is similar to the RS latch one, but with R removed.
JK Latch
The ambiguous state output in the RS latch was eliminated in the D latch by joining the inputs with an inverter. But the D latch has a single input. JK latch is similar to RS latch in that it has 2 inputs J and K as shown figure below. The ambiguous state has been eliminated here: when both inputs are high, output toggles. The only difference we see here is output feedback to inputs, which is not there in the RS latch.
J 1 1 1 0
K 1 1 0 1
Q 0 1 1 0
T Latch
When the two inputs of JK latch are shorted, a T Latch is formed. It is called T latch as, when
input is held HIGH, output toggles.
T 1 1 0 0
Q 0 1 1 0
Q+ 1 0 1 0
The following table helps you to understand the differences between the different processors that Intel has introduced over the year
Name
Date
Transistors
Microns
Clock Speed 2 MHz 5 MHz 6 MHz 16 MHz
Data width
MIPS
8080 8088 80286 80386
1974 1979 1982 1985
6,000 29,000 134,000 275,000
6 3 1.5 1.5
8 bits 16 bits, 8-bit bus 16 bits 32 bits
0.64 0.33 1 5
80486
1989
1,200,000 3,100,000
1 0.8
25 MHz 60 MHz
32 bits 32 bits, 64-bit bus
20 100
Pentium 1993 Pentium II Pentium III Pentium IV
1997
7,500,000
0.35
233 MHz 32 bits, 64-bit bus
~300
1999
9,500,000
0.25
450 MHz 32 bits, 64-bit bus
~510
2000
42,000,000
0.18
1.5 GHz
32 bits, 64-bit bus
~1,700
Brief introduction to comparison of different features in 8085and 8086 microprocessors.

There are some of the difference mentioned below:
1.Size:8085 is 8 bit microprocessor whereas 8086 is 16 bit microprocessor.
2.Address Bus:8085 has 16 bit address bus and 8086 has 20 bit addres bus.
3.Memory:8085 can access up to 2^16 = 64 Kb of memory whereas 8086 can access up to 2^20 = 1 MB of memory.
4.Instruction Queue:Microprocessor notes Prepared by- Girraj Sharma
8085 doesn't have an instruction queue whereas 8086 has instruction queue.
5.Pipelining:8085 does not support pipelined architecture whereas 8086 supports pipelined architecture.
6.Multiprocessing Support:8085 does not support multiprocessing support whereas 8086 supports.
7.I/O:8085 can address 2^8 = 256 I/O's and 8086 can access 2^16 = 65,536 I/O's
8.Airthmetic Support:8085 only supports integer and decimal whereas 8086 supports integer, decimal and ASCII arithmetic.
9.Multiplication and Division:8085 doesn't support whereas 8086 supports.
10. Operating Modes:8085 supports only single operating mode whereas 8086 operates in two modes.
11.External Hardware:8085 requires less external hardware whereas 8086 requires more external hardware.
12.Cost:The cost of 8085 is low and 8086 is high.
13.Memory Segmentation:In 8085, memory space is not segmented but in 8086, memory space is segmented.
UNIT-2
UNIT-2 INTRODUCTION TO MICROPROCESSOR BASEDSYSTEM

The microprocessor is a semiconductor device (Integrated Circuit) manufactured by the VLSI (Very Large Scale Integration) technique. It includes the ALU, register arrays and control circuit on a single chip. To perform a function or useful task we have to form a system by using microprocessor as a CPU and interfacing memory, input and output devices to it. A system designed using a microprocessor as its CPU is called a microcomputer. The Microprocessor based system (single board microcomputer) consists of microprocessor as CPU, semiconductor memories like EPROM and RAM, input device, output device and interfacing devices. The memories, input device, output device and interfacing devices are called peripherals. The popular input devices are keyboard and floppy disk and the output devices are printer, LED/LCD displays, CRT monitor, etc.
The above block diagram shows the organization of a microprocessor based system. In this system, the microprocessor is the master and all other peripherals are slaves. The master controls all the peripherals and initiates all operations. The work done by the processor can be classified into the following three groups. 1. Work done internal to the processor 2. Work done external to the processor 3. Operations initiated by the slaves or peripherals. The work done internal to the processors are addition, subtraction, logical operations, data transfer operations, etc. The work done external to the processor are reading/writing the memory and reading/writing the J/O devices or the peripherals. If the peripheral requires the attention of the master then it can interrupt the master and initial state. The microprocessor is the master, which controls all the activities of the system. To perform a specific job or task, the microprocessor has to execute a program stored in memory. The program consists of a set of instructions. It issues address and control signals and fetches the instruction and data from memory. The instruction is executed one by one internal to the processor and based on the result it takes appropriate action. BUSES: The buses are group of lines that carries data, address or control signals. The CPU Bus has multiplexed lines, i.e., same line is used to carry different signals. The CPU interface is provided to demultiplex the multiplexed lines, to generate chip select signals and additional control signals. The system bus has separate lines for each signal. All the slaves in the system are connected to the same system bus. At any time instant
communication takes place between the master and one of the slaves. All the slaves have tristate logic and hence normally remain in high impedance state. Only when the slave is selected it comes to the normal logic. PERIPHERAL DEVICES The EPROM memory is used to store permanent programs and data. The RAM memory is used to store temporary programs and data. The input device is used to enter the program, data and to operate the system. The output device is used for examining the results. Since the speed of I/O devices does not match with the speed of microprocessor, an interface device is provided between system bus and I/O devices. Generally I/O devices are slow devices. Advantages of Microprocessor based system 1. Computational/processing speed is high. 2. Intelligence has been brought to systems. 3. Automation of industrial processes and office administration. 4. Since the devices are programmable, there is flexibility to alter the system by changing the software alone. 5. Less number of components, compact in size and cost less. Also it is more reliable. 6. Operation and maintenance are easier.
Disadvantages of Microprocessor based System

1. It has limitations on the size of data. 2. The applications are limited by the physical address space. 3. The analog signals cannot be processed directly and digitizing the analog signals introduces errors. 4. The speed of execution is slow and so real time applications are not possible. 5. Most of the
microprocessors does not support floating point operation
INTEL 8085 - Pin Diagram & Description

The INTEL 8085 is a 8-bit microprocessor. It operates on 8-bit data and uses 16-bit address to access the memory. With the help of 16-bit address, 8085 can access 216 = 65536 = 64K memory locations. It is a 40-pin DIP chip designed using NMOS. It operates with a power supply of +5 volts and GND. 8085 generates the clock signal internally by dividing the external supplied clock signal by two.
INTEL 8085 ARCHITECTURE The architecture of.8085 is shown in figure given below. The internal architecture of 8085 includes the ALU, timing and control unit, instruction register and decoder, register array, interrupt control and serial I/O control.
OPERATIONS PERFORMED BY 8085 The ALU performs the arithmetic and logical operations. The operations performed by ALU of 8085 are addition, subtraction, increment, decrement, logical AND, OR, EXCL U8IVE -OR, compare, complement and left / right shift. The accumulator and temporary register are used to hold the data during an arithmetic / logical operation. After an operation the result is stored in the accumulator and the flags are set or reset according to the result of the operation.
Memory Program, data and stack memories occupy the same memory space. The total addressable memory size is 64 KB. Program memory - program can be located anywhere in memory. Jump, branch and call instructions use 16-bit addresses, i.e. they can be used to jump/branch anywhere within 64 KB. All jump/branch instructions use absolute addressing. Data memory - the data can be placed anywhere as the 8085 processor always uses 16-bit addresses. Stack memory is limited only by the size of memory. Stack grows downward. First 64 bytes in a zero memory page should be reserved for vectors used by RST instructions.
I/O ports 256 256 Output ports Input ports
Registers
Accumulator or A register is an 8-bit register used for arithmetic, logic, I/O and load/store operations. Flag is an 8-bit register containing 5 1-bit flags:

Sign - set if the most significant bit of the result is set. Zero - set if the result is zero. Auxiliary carry - set if there was a carry out from bit 3 to bit 4 of the result. Parity - set if the parity (the number of set bits in the result) is even. Carry - set if there was a carry during addition, or borrow during subtraction/comparison.
General registers:
8-bit B and 8-bit C registers can be used as one 16-bit BC register pair. When used as a pair the C register contains low-order byte. Some instructions may use BC register as a data pointer.
8-bit D and 8-bit E registers can be used as one 16-bit DE register pair. When used as a pair the E register contains low-order byte. Some instructions may use DE register as a data pointer.
8-bit H and 8-bit L registers can be used as one 16-bit HL register pair. When used as a pair the L register contains low-order byte. HL register usually contains a data pointer used to reference memory addresses.
Stack pointer is a 16 bit register. This register is always incremented/decremented by 2. Program counter is a 16-bit register.
Instruction Set Instruction set of Intel 8085 microprocessor consists of the following instructions:

Data moving instructions. Arithmetic - add, subtract, increment and decrement. Logic - AND, OR, XOR and rotate.
Control transfer - conditional, unconditional, call subroutine, return from subroutine and restarts.
Input/Output instructions. Other - setting/clearing flag bits, enabling/disabling interrupts, stack operations, etc.
Functioning of ALU in 8085 The arithmetic and logical unit will be performing *8 bit addition with /with out carry *8bit substraction with /with out borrow *2 bit BCD(Binary coded decimal) addition *16 bit binary addition*16 bit logical operations-OR,AND,EX-OR,COMPLEMENT and BIT SHIFT
address/data buffer the address bus will be having 16 address lines[A15-A0] .In which A7-A0 are called as lower addressing lines and these are multiplexed with data lines[D7-D0] to form multiplexed address /data buffer .The address/data buffer is the bidirectional bus.
address buffer the remaining higher order address lines form the address buffer ranging from[A15-18].This is having the unidirectional buffer
Instruction register there are 74 instructions in 8085 .these instructions are classified in to 5 addressing modes they are 1)immediate addressing mode 2)register addressing mode 3)direct addressing mode 4)indirect addressing mode 5)implied addressing mode
serial i/o control these these are are control signals subdivided used into for controlling 2
8085 types
1)SID(serial input data):this is used for transferring of data into the memory serially 2)SOD(serial output data):this is used for transferring of data from memory to external devices
After an ALU operation, if the most significant bit of the result is 1, then sign flag is set. The zero flag is set, if the ALU operation results in zero and it is reset if the result is non-zero. In an arithmetic operation, when a carry is generated by the lower nibble, the auxiliary carry flag is set. After an arithmetic or logical operation, if the result has an even number of 1 's the parity flag is set, other wise it is reset. If an arithmetic operation results in a carry, the carry flag is set other wise it is reset. Among the five flags, the AC flag is used internally for BCD arithmetic and other four flags can be used by the programmer to check the conditions of the result of an operation.
TIMING & CONTROL UNIT: The timing and control unit synchronizes all the microprocessor operations with the clock and generates the control signals necessary for communication between the microprocessor and peripherals.
INSTRUCTION REGISTER & DECODER: When an instruction is fetched from memory it is placed in instruction register. Then it is decoded and encoded into various machine cycles.
REGISTER ARRAY: Apart from Accumulator (A-register), there are six general-purpose programmable registers B, C, D, E, H and L. They can be used as 8-bit registers or paired to store l6-bit data. The allowed pairs are B-C, D-E and H-L. The temporary registers W and Z are intended for internal use of the processor and it cannot be used by the programmer.
STACK POINTER (SP): The stack pointer SP, holds the address of the stack top. The stack is a sequence of RAM memory locations defined by the programmer. The stack is used to save the content of registers during the execution of a program.
PROGRAM COUNTER (PC):

The program counter (PC) keeps track of program execution. To execute a program the starting address of the program is loaded in program counter. The PC sends out an address to fetch a byte of instruction from memory and increment its content automatically. Hence, when a byte of instruction is fetched, the PC holds the address of the next byte of the instruction or next instruction.
Interrupts
Hardware interrupts:
An external device initiates the hardware interrupts and placing an appropriate signal at the interrupt pin of the processor.
If the interrupt is accepted then the processor executes an interrupt service routine.
The 8085 has five hardware interrupts
(1) TRAP
(2) RST 7.5
(3) RST 6.5
(4) RST 5.5
(5) INTR
TRAP:

This interrupt is a non-maskable interrupt. It is unaffected by any mask or interrupt enable. TRAP bas the highest priority and vectored interrupt. TRAP interrupt is edge and level triggered. This means hat the TRAP must go high and remain high until it is acknowledged.
In sudden power failure, it executes a ISR and send the data from main memory to backup memory.
The signal, which overrides the TRAP, is HOLD signal. (i.e., If the processor receives HOLD and TRAP at the same time then HOLD is recognized first and then TRAP is recognized).
There are two ways to clear TRAP interrupt. 1.By resetting microprocessor (External signal) 2.By giving a high TRAP ACKNOWLEDGE (Internal signal)
INTR INTR is maskable 8080A compatible interrupt. When the interrupt occurs the processor fetches from the bus one instruction, usually one of these instructions:
One of the 8 RST instructions (RST0 - RST7). The processor saves current program counter into stack and branches to memory location N * 8 (where N is a 3-bit number from 0 to 7 supplied with the RST instruction).
CALL instruction (3 byte instruction). The processor calls the subroutine, address of which is specified in the second and third bytes of the instruction.
RST5.5 is a maskable interrupt. When this interrupt is received the processor saves the contents of the PC register into stack and branches to 2Ch (hexadecimal) address.
RST6.5 is a maskable interrupt. When this interrupt is received the processor saves the contents of the PC register into stack and branches to 34h (hexadecimal) address.
RST7.5 is a maskable interrupt. When this interrupt is received the processor saves the contents of the PC register into stack and branches to 3Ch (hexadecimal) address. All maskable interrupts can be enabled or disabled using EI and DI instructions. RST 5.5, RST6.5 and RST7.5 interrupts can be enabled or disabled individually using SIM instruction.
UNIT- 3
UNIT - 3
INSTRUCTION EXECUTION AND DATA FLOW in 8085
The program instructions are stored in memory, which is an external device. To execute a program in 8085, the starting address of the program should be loaded in program counter. The 8085 output the content of program counter in address bus and asserts read control signal low. Also, the program counter is incremented. The address and the read control signal enable the memory to output the content of memory location on the data bus. Now the content of data bus is the opcode of an instruction. The read control signal is made high by timing and control unit after a specified time. At the rising edge of read control signals, the opcode is latched into microprocessor internal bus and placed in instruction register. The instruction-decoding unit, decodes the instructions and provides information to timing and control unit to take further actions. INSTRUCTION FORMAT OF 8085 The 8085 have 74 basic instructions and 246 total instructions. The instruction set of 8085 is defined by the manufacturer Intel Corporation. Each instruction of 8085 has 1 byte opcode. With 8 bit binary code, we can generate 256 different binary codes. In this, 246 codes have been used for opcodes. The size of 8085 instructions can be 1 byte, 2 bytes or 3 bytes. The 1-byte instruction has an opcode alone. The 2 bytes instruction has an opcode followed by an eight-bit address or data. The 3 bytes instruction has an opcode followed by 16 bit address or data. While storing the 3
bytes instruction in memory, the sequence of storage is, opcode first followed by low byte of address or data and then high byte of address or data.
ADDRESSING MODES Every instruction of a program has to operate on a data. The method of specifying the data to be operated by the instruction is called Addressing. The 8085 has the following 5 different types of addressing. 1. Immediate Addressing 2. Direct Addressing 3. Register Addressing 4. Register Indirect Addressing 5. Implied Addressing
Immediate Addressing In immediate addressing mode, the data is specified in the instruction itself. The data will be apart of the program instruction. All instructions that have 'I' in their mnemonics are of Immediate addressing type. Eg. MVI B, 3EH - Move the data 3EH given in the instruction to B register. Direct Addressing In direct addressing mode, the address of the data is specified in the instruction. The data will be in memory. In this addressing mode, the program instructions and data can be stored in different memory blocks. This type of addressing can be identified by 16-bit address present in the instruction. Eg. LDA 1050H - Load the data available in memory location 1050H in accumulator. Register Addressing In register addressing mode, the instruction specifies the name of the register in which the data is available. This type of addressing can be identified by register names (such as 'A', 'B', ) in the instruction. Eg. MOV A, B -Move the content of B register to A register.
Register Indirect Addressing In register indirect addressing mode, the instruction specifies the name of the register in which the address of the data is available. Here the data will be in memory and the address will be in the register pair. This type of addressing can be identified by letter 'M' present in the instruction. Eg. MOV A, M - The memory data addressed by HL pair is moved to A register. Implied Addressing In implied addressing mode, the instruction itself specifies the type of operation and location of data to be operated. This type of instruction does not have any address, register name, immediate data specified along with it.Ex- CMA
INSTRUCTION SET The 8085 instruction set can be classified into the following five functional headings. Group I - DATA TRANSFER INSTRUCTIONS: Includes the instructions that moves ( copies) data between registers or between memory locations and registers. In all data transfer operations the content of source register is not altered. Hence the data transfer is copying operation. Ex: i) MOV A,B ii) LDA 4600 iii) LHLD 4200
Group II - ARITHMETIC INSTRUCTIONS: Includes the instructions which performs the addition, subtraction, increment or decrement operations. The flag conditions are altered after execution of an instruction in this group. Ex: i) ADD B ii) SUB C iii) INR D iv) INX H
Group III - LOGICAL INSTRUCTIONS: The instructions which performs the logical operations like AND, OR, Exclusive-OR, complement, compare and rotate instructions are grouped under this heading. The flag conditions are altered after execution of an instruction in this group. Ex: i) ORA B ii) XRA A iii) RAR
Group IV - BRANCHING INSTRUCTIONS: The instructions that are used to transfer the program control from one memory location to another memory location are grouped under this heading. Ex: i) JZ 4200 ii) RST 7 iii) CALL 4300
Group V - MACHINE CONTROL INSTRUCTIONS: Includes the instructions related to interrupts and the instruction used to halt program execution. Ex: i) SIM ii) RIM iii) HLT
The 74 basic instructions of8085 are listed inTable-2.1. The opcode of each instruction, size, machine cycles, number of T -state and the total number of instructions in each type are also shown in table in next page. The instructions affecting the status flag are listed in table followed.
INSTRUCTION SET OF INTEL 8085
An Instruction is a command given to the computer to perform a specified operation on given data. The instruction set of a microprocessor is the collection of the instructions that the microprocessor is designed to execute. The instructions described here are of Intel 8085. These instructions are of Intel Corporation. They cannot be used by other microprocessor manufactures. The programmer can write a program in assembly language using these instructions. These instructions have been classified into the following groups: 1. Data Transfer Group 2. Arithmetic Group 3. Logical Group 4. Branch Control Group 5. I/O and Machine Control Group
Data Transfer Group: Instructions, which are used to transfer data from one register to another register, from memory to register or register to memory, come under this group. Examples are: MOV, MVI, LXI, LDA, STA etc. When an instruction of data transfer group is executed, data is
transferred from the source to the destination without altering the contents of the source. For example, when MOV A, B is executed the content of the register B is copied into the register A, and the content of register B remains unaltered. Similarly, when LDA 2500 is executed the content of
the memory location 2500 is loaded into the accumulator. But the content of the memory location 2500 remains unaltered.
Arithmetic Group: The instructions of this group perform arithmetic operations such as addition, subtraction; increment or decrement of the content of a register or memory. Examples are: ADD, SUB, INR, DAD etc. Logical Group: The Instructions under this group perform logical operation such as AND, OR, compare, rotate etc. Examples are: ANA, XRA, ORA, CMP, and RAL etc. Branch Control Group: This group includes the instructions for conditional and unconditional jump, subroutine call and return, and restart. Examples are: JMP, JC, JZ, CALL, CZ, RST etc. I/O and Machine Control Group: This group includes the instructions for input/output ports, stack and machine control. Examples are: IN, OUT, PUSH, POP, and HLT etc.
Intel 8085 Instructions

1. Data Transfer Group
a. MOV r1, r2 (Move Data; Move the content of the one register to another). [r1] [r2]. b. MOV r, m (Move the content of memory register). r [M] c. MOV M, r. (Move the content of register to memory). M [r] d. MVI r, data. (Move immediate data to register). [r] data. e. MVI M, data. (Move immediate data to memory). M data. f. LXI rp, data 16. (Load register pair immediate). [rp] data 16 bits, [rh] 8 LSBs of data.
g. LDA addr. (Load Accumulator direct). [A] [addr].

h. STA addr. (Store accumulator direct). [addr] [A]. i.LHLD addr. (Load H-L pair direct). [L] [addr], [H] [addr+1]. j. SHLD addr. (Store H-L pair direct) [addr] [L], [addr+1] [H]. k. LDAX rp. (OAD accumulator indirect) [A] [[rp]] l. STAX rp. (Store accumulator indirect) [[rp]] [A]. m. XCHG. (Exchange the contents of H-L with D-E pair) [H-L] <-->[D-E].
2. Arithmetic Group
i. ii. iii. iv. v. vi. vii. viii. ix. x. xi. xii. xiii.
ADD r. (Add register to accumulator) [A] [A] + [r]. ADD M. (Add memory to accumulator) [A] [A] + [[H-L]]. ADC r. (Add register with carry to accumulator). [A] [A] + [r] + [CS]. ADC M. (Add memory with carry to accumulator) [A] [A] + [[H-L]] [CS]. ADI data (Add immediate data to accumulator) [A] [A] + data. ACI data (Add with carry immediate data to accumulator). [A] [A] + data + [CS]. DAD rp. (Add register paid to H-L pair). [H-L] [H-L] + [rp]. SUB r. (Subtract register from accumulator). [A] [A] [r]. SUB M. (Subtract memory from accumulator). [A] [A] [[H-L]]. SBB r. (Subtract register from accumulator with borrow). [A] [A] [r] [CS]. SBB M. (Subtract memory from accumulator with borrow). [A] [A] [[H-L]] [CS]. SUI data. (Subtract immediate data from accumulator) [A] [A] data. SBI data. (Subtract immediate data from accumulator with borrow). [A] [A] data [CS].
xiv. xv. xvi. xvii.
INR r (Increment register content) [r] [r] +1. INR M. (Increment memory content) [[H-L]] [[H-L]] + 1. DCR r. (Decrement register content). [r] [r] 1. DCR M. (Decrement memory content) [[H-L]] [[H-L]] 1.
xviii. INX rp. (Increment register pair) [rp] [rp] 1.

xix. xx.
DCX rp (Decrement register pair) [rp] [rp] -1. DAA (Decimal adjust accumulator) .
The instruction DAA is used in the program after ADD, ADI, ACI, ADC, etc instructions. After the execution of ADD, ADC, etc instructions the result is in hexadecimal and it is placed in the accumulator. The DAA instruction operates on this result and gives the final result in the decimal system. It uses carry and auxiliary carry for decimal adjustment. 6 is added to 4 LSBs of the content of the accumulator if their value lies in between A and F or the AC flag is set to 1. Similarly, 6 is also added to 4 MSBs of the content of the accumulator if their value lies in between A and F or the CS flag is set to 1. All status flags are affected. When DAA is used data should be in decimal numbers.
3. Logical Group
i. ii. iii. iv. v. vi. vii. viii. ix.
ANA r. (AND register with accumulator) [A] [A] ^ [r]. ANA M. (AND memory with accumulator). [A] [A] ^ [[H-L]]. ANI data. (AND immediate data with accumulator) [A] [A] ^ data. ORA r. (OR register with accumulator) [A] [A] v [r]. ORA M. (OR memory with accumulator) [A] [A] v [[H-L]] ORI data. (OR immediate data with accumulator) [A] [A] v data. XRA r. (EXCLUSIVE OR register with accumulator) [A] [A] v [r] XRA M. (EXCLUSIVE-OR memory with accumulator) [A] [A] v [[H-L]] XRI data. (EXCLUSIVE-OR immediate data with accumulator) [A] [A] v data.
x. x. xi. xii. xiii. xiv.
CMA. (Complement the accumulator) [A] [A] CMC. (Complement the carry status) [CS] [CS] STC. (Set carry status) [CS] 1. CMP r. (Compare register with accumulator) [A] [r] CMP M. (Compare memory with accumulator) [A] [[H-L]] CPI data. (Compare immediate data with accumulator) [A] data.
The 2nd byte of the instruction is data, and it is subtracted from the content of the accumulator. The status flags are set according to the result of subtraction. But the result is discarded. The content of the accumulator remains unchanged.
xv.
RLC (Rotate accumulator left) [An+1] [An], [A0] [A7], [CS] [A7]. The content of the accumulator is rotated left by one bit. The seventh bit of the accumulator is moved to carry bit as well as to the zero bit of the accumulator. Only CS flag is affected.
Carry
CS
A7
A0
xvi.
RRC. (Rotate accumulator right) [A7] [A0], [CS] [A0], [An] [An+1]. The content of the accumulator is rotated right by one bit. The zero bit of the accumulator is moved to the seventh bit as well as to carry bit. Only CS flag is affected.
CS
A7
A0
Carry Status Schematic Diagram for RRC xvii.
Accumulator
RAL. (Rotate accumulator left through carry) [An+1] [An], [CS] [A7], [A0] [CS].
xviii. RAR. (Rotate accumulator right through carry) [An] [An+1], [CS] [A0], [A7] [CS]
4. Branch Group
i.
JMP addr (label). (Unconditional jump: jump to the instruction specified by the address). [PC] Label.
ii.
Conditional Jump addr (label): After the execution of the conditional jump instruction the program jumps to the instruction specified by the address (label) if the specified condition is fulfilled. The program proceeds further in the normal sequence if the specified condition is not fulfilled. If the condition is true and program jumps to the specified label, the execution of a conditional jump takes 3 machine cycles: 10 states. If condition is not true, only 2 machine cycles; 7 states are required for the execution of the instruction. a. JZ addr (label). (Jump if the result is zero) b. JNZ addr (label) (Jump if the result is not zero) c. JC addr (label). (Jump if there is a carry) d. JNC addr (label). (Jump if there is no carry) e. JP addr (label). (Jump if the result is plus) f. JM addr (label). (Jump if the result is minus) g. JPE addr (label) (Jump if even parity) h. JPO addr (label) (Jump if odd parity)
iii.
CALL addr (label) (Unconditional CALL: call the subroutine identified by the operand) CALL instruction is used to call a subroutine. Before the control is transferred to the subroutine, the address of the next instruction of the main program is saved in the stack. The content of the stack pointer is decremented by two to indicate the new stack top. Then the program jumps to subroutine starting at address specified by the label.
iv. v.
RET (Return from subroutine) RST n (Restart) Restart is a one-word CALL instruction. The content of the program counter is saved in the stack. The program jumps to the instruction starting at restart location.
5. Stack, I/O and Machine Control Group i. ii. IN port-address. (Input to accumulator from I/O port) [A] [Port] OUT port-address (Output from accumulator to I/O port) [Port] [A]
iii. iv. v. vi. vii. viii. ix. x. xi. xii. xiii. xiv.
PUSH rp (Push the content of register pair to stack) PUSH PSW (PUSH Processor Status Word) POP rp (Pop the content of register pair, which was saved, from the stack) POP PSW (Pop Processor Status Word) HLT (Halt) XTHL (Exchange stack-top with H-L) SPHL (Move the contents of H-L pair to stack pointer) EI (Enable Interrupts) DI (Disable Interrupts) SIM (Set Interrupt Masks) RIM (Read Interrupt Masks) NOP (No Operation)
INTERRUPTS NEED FOR INTERRUPTS Interrupt is a signal send by an external device to the processor, to the processor to perform a particular task or work. Mainly in the microprocessor based system the interrupts are used for data transfer between the peripheral and the microprocessor. When a peripheral is ready for data transfer, it interrupts the processor by sending an appropriate signal to the interrupt pin of the processor. If the processor accepts the interrupt then the processor suspends its current activity and executes an interrupt service subroutine to complete the data transfer between the peripheral and processor. After executing the interrupt service routine the processor resumes its current activity. This type of data transfer scheme is called interrupt driven data transfer scheme.
TYPES OF INTERRUPTS The interrupts are classified into software interrupts and hardware interrupts. The software interrupts are program instructions. These instructions are inserted at desired
locations in a program. While running a program, lf a software interrupt instruction is encountered, then the processor executes an interrupt service routine (ISR). The hardware interrupts are initiated by an external device by placing an appropriate signal at the interrupt pin of the processor. If the interrupt is accepted, then the processor executes an interrupt service routine (ISR).
SOFTWARE INTERRUPTS OF 8085 The software interrupts are program instructions. When the instruction is executed, the processor executes an interrupt service routine stored in the vector address of the software interrupt instruction. The software interrupts of 8085 are RST 0, RST 1, RST 2, RST 3, RST 4, RST 5, RST 6 RST 7. The vector addresses software interrupts of and are given in table below.
The software interrupt instructions are included at the appropriate (or required) place in the main program. When the processor encounters the software instruction, it pushes the content of PC (Program Counter) to stack. Then loads the Vector address in PC and starts executing the Interrupt Service Routine (ISR) stored in this vector address. At the end of ISR, a return instruction - RET will be placed. When the RET instruction is executed, the processor POP the content of stack to PC. Hence the processor control returns to the main program after servicing the interrupt. Execution of ISR is referred to as servicing of interrupt. All software interrupts of 8085 are vectored interrupts. The software interrupts cannot be masked and they cannot be disabled. The software interrupts are RST0, RST1, RST7 . HARDWARE INTERRUPTS OF 8085 An external device, initiates the hardware interrupts of 8O85 by placing an appropriate signal at the interrupt pin of the processor. The processor keeps on checking the interrupt pins at the second T state of last machine cycle of every instruction. If the processor finds a valid interrupt signal and if the interrupt is unmasked and enabled, then the processor accepts the interrupt. The acceptance of the interrupt is acknowledged by sending an INTA signal to the interrupted device. The processor saves the content of PC (program Counter) in stack and then loads the vector address of the interrupt in PC. (If the interrupt is non-vectored, then the interrupting device has to supply the address of ISR when it receives INTA signal). It starts executing ISR in this address. At the end of ISR, a return instruction, RET will be placed. When the processor executes the RET instruction, it POP the content of top of stack to PC. Thus the processor control returns to main program after servicing interrupt. The hardware interrupts of 8085 are TRAP, RST 7.5, RST 6.5, RST 5.5 and INTR. Further the interrupts may be classified into VECTORED and NON-VECTORED INTERRUPTS.
VECTORED INTERRUPT In vectored interrupts, the processor automatically branches to the specific address in response to an interrupt.
NON-VECTORED INTERRUPT But in non-vectored interrupts the interrupted device should give the address of the interrupt service routine (ISR). In vectored interrupts, the manufacturer fixes the address of the ISR to which the program control is to be transferred. The TRAP, RST 7.5, RST 6.5 and RST 5.5 are vectored interrupts. The INTR is a non-vectored interrupt. Hence when a device interrupts through INTR, it has to supply the address of ISR after receiving interrupt acknowledge signal. The type of signal that has to be placed on the interrupt pin of hardware interrupts of 8085 are defined by INTEL. The TRAP interrupt is edge and level sensitive. Hence, to initiate TRAP, the interrupt signal has to make a low to high transition and then it has to remain high until the interrupt is recognized. The RST 7.5 interrupt is edge sensitive (positive edge). To initiate the RST 7.5, the interrupt signal has to make a low to high transition an it need not remain high until it is recognized. The RST 6.5, RST 5.5 and INTR are level sensitive interrupts. Hence for these interrupts the interrupting signal should remain high, until it is recognized. MASKABLE & NON-MASKABLE INETRRUPTS: The hardware vectored interrupts are classified into maskable and non-maskable interrupts. TRAP is non-maskable interrupt RST 7.5, RST 6.5 and RST 5.5 are maskable interrupt.
Masking is preventing the interrupt from disturbing the main program. When an interrupt is masked the processor will not accept the interrupt signal. The interrupts can be masked by moving an appropriate data (or code) to accumulator and then executing SIM instruction. (SIM - Set Interrupt Mask). The status of maskable interrupts can be read into accumulator by executing RIM instruction (RIM - Read Interrupt Mask).
The TRAP, RST 7.5, RST 6.5 and RST 5.5 are vectored interrupts. The INTR is a non-vectored interrupt. Hence when a device interrupts through INTR, it has to supply the address of ISR after receiving interrupt acknowledge signal. The type of signal that has to be placed on the interrupt pin of hardware interrupts of 8085 are defined by INTEL. The TRAP interrupt is edge and level sensitive. Hence, to initiate TRAP, the interrupt signal has to make a low to high transition and then it has to remain high until the interrupt is recognized. The RST 7.5 interrupt is edge sensitive (positive edge). To initiate the RST 7.5, the interrupt signal has to make a low to high transition an it need not remain high until it is recognized. The RST 6.5, RST 5.5 and INTR are level sensitive interrupts. Hence for these interrupts the interrupting signal should remain high, until it is recognized. MASKABLE & NON-MASKABLE INETRRUPTS: The hardware vectored interrupts are classified into maskable and non-maskable interrupts. TRAP is non-maskable interrupt RST 7.5, RST 6.5 and RST 5.5 are maskable interrupt.
Masking is preventing the interrupt from disturbing the main program. When an interrupt is masked the processor will not accept the interrupt signal. The interrupts can be masked by moving an appropriate data (or code) to accumulator and then executing SIM instruction. (SIM - Set Interrupt Mask). The status of maskable interrupts can be read into accumulator by executing RIM instruction (RIM - Read Interrupt Mask). All the hardware interrupts, except TRAP are disabled, when the processor is resetted. They can also be disabled by executing Dl instruction. (Dl-Disable Interrupt). When an interrupt is disabled, it will not be accepted by the processor. (i.e., INTR, RST 5.5, RST 6.5 and RST 7.5 are disabled by DI instruction and upon hardware reset). To enable (to allow) the disabled interrupt, the processor has to execute El instruction (El-
Enable Interrupt).
INTERRUPT DRIVEN DATA TRANSFER SCHEME The interrupt driven data transfer scheme is the best method of data transfer for effectively utilizing the processor time. In this scheme, the processor first initiates the I/O device for data transfer. After initiating the device, the processor will continue the execution of instructions in the program. Also at the end of an instruction the processor will check for a valid interrupt signal. If there is no interrupt then the processor will continue the execution. When the I/O device is ready, it will interrupt the processor. On receiving an interrupt signal, the processor will complete the current instruction execution and saves the processor status in stack. Then the processor calls an interrupt service routine (ISR) to service the interrupted device. At the end of ISR the processor status is retrieved from stack and the processor starts executing its main program. The sequence of operations for an interrupt driven data transfer scheme is shown in figure below.
Timing diagram
Timing diagram is the display of initiation of read/write and transfer of data operations underthe control of 3-status signals IO / M , S1, and S0. As the heartbeat is required for the survival of the human being, the CLK is required for the proper operation of different sections of the microprocessors. All actions in the microprocessor is controlled by either leading or trailing edge of the clock. If I ask a man to bring 6-bags of wheat, each weighing 100 kg, he may take 6-times to perform this task in going and bringing it. A stronger man might perform the same task in 3times only. Thus, it depends on the strength of the man to finish the job quickly or slowly. Here, we can assume both weaker and strong men as machine. The weaker man has taken 6-machine cycle (6-times going and coming with one bag each time) to execute the job where as the stronger man has taken only 3-machine cycle for the same job. Similarly, a machine may execute one instruction in as many as 3-machine cycles while the other machine can take only one machine cycle to execute the same instruction. Thus, the machine that has taken only one machine cycle is efficient than the one taking 3-machine cycle. Each machine cycle is composed of many clock cycle. Since, the data and instructions, both are stored in the memory, the P performs fetch operation to read the instruction or data and then execute the instruction. The P in doing so may take several cycles to perform fetch and execute operation. The 3-status signals : IO / M, S1, and S0 are generated at the beginning of each machine cycle. The unique combination of these 3-status signals identify read or write operation and remain valid for the duration of the cycle. Table-5.1(a) shows details of the unique combination of these status signals to identify different machine cycles. Thus, time taken by any P to execute one instruction is calculated in terms of the clock period. The execution of instruction always requires read and writes operations to transfer data to or from the P and memory or I/O devices. Each read/ write operation constitutes one machine cycle (MC1) as indicated in Fig. 5.1 (a). Each machine cycle consists of many clock periods/ cycles, called T-states. The heartbeat of the microprocessor is the clock period. Each and every operation inside the microprocessor is under the control of the clock cycle. The clock signal determines the time taken by the microprocessor to execute any instruction. The clock cycle shown in Fig. 5.1 (a) has two edges (leading and trailing or lagging). State is defined as the time.
interval between 2-trailing or leading edges of the clock. Machine cycle is the time required to transfer data to or from memory or I/O devices.
PROCESSOR CYCLE
The function of the microprocessor is divided into fetch and execute cycle of any instruction of a program. The program is nothing but number of instructions stored in the memory in sequence. In the normal process of operation, the microprocessor fetches (receives or reads) and executes one instruction at a time in the sequence until it executes the halt (HLT) instruction. Thus, an instruction cycle is defined as the time required to fetch and execute an instruction. For executing any program, basically 2-steps are followed sequentially with the help of clocks Fetch, and Execute. The time taken by the P in performing the fetch and execute operations are called fetch and execute cycle. Thus, sum of the fetch and execute cycle is called the instruction cycle as indicated in Fig. 5.2 (a).
Instruction Cycle (IC) = Fetch cycle (FC) + Execute Cycle (EC)
TIMING DIAGRAM for various machine cycles
The machine cycles are the basic operations performed by the processor, while instructions are executed. The time taken for performing each machine cycle is expressed in terms of T- states. One T-state is the time period of one clock cycle of the microprocessor. The various machine cycles are 1. Opcode fetch .. 2. Memory Read . 3. Memory Write . - 4/6T - 3T - 3T
4. I/O Read .. 5. I/O Write . Interrupt Acknowledge 7. Bus Idle
- 3T - 3T 6.
- 6 / 12 T - 2/3T
UNIT-4
UNIT-4 MEMORY INTERFACING

KEYBOARD AND DISPLAY INTERFACE USING 8279 The four major sections of 8279 are keyboard, scan, display and CPU interface. Keyboard section:
The keyboard section consists of eight return lines RL0 - RL7 that can be used to form the columns of a keyboard matrix.
It has two additional input : shift and control/strobe. The keys are automatically debounced.
The two operating modes of keyboard section are 2-key lockout and N-key rollover. In the 2-key lockout mode, if two keys are pressed simultaneously, only the first key is recognized.
In the N-key rollover mode simultaneous keys are recognized and their codes are stored in FIFO.
The keyboard section also have an 8 x 8 FIFO (First In First Out) RAM. The FIFO can store eight key codes in the scan keyboard mode. The status of the shift key and control key are also stored along with key code. The 8279 generate an interrupt signal when there is an entry in FIFO. The format of key code entry in FIFO for scan keyboard mode is,
The functional block diagram of 8279 is shown.
In sensor matrix mode the condition (i.e., open/close status) of 64 switches is stored in FIFO RAM. If the condition of any of the switches changes then the 8279 asserts IRQ as high to interrupt the processor.
Display section:

The display section has eight output lines divided into two groups A0-A3 and B0-B3. The output lines can be used either as a single group of eight lines or as two groups of four lines, in conjunction with the scan lines for a multiplexed display.
The output lines are connected to the anodes through driver transistor in case of common cathode 7-segment LEDs.
The cathodes are connected to scan lines through driver transistors. The display can be blanked by BD (low) line. The display section consists of 16 x 8 display RAM. The CPU can read from or write into any location of the display RAM.
Scan section:

The scan section has a scan counter and four scan lines, SL0 to SL3. In decoded scan mode, the output of scan lines will be similar to a 2-to-4 decoder. In encoded scan mode, the output of scan lines will be binary count, and so an external decoder should be used to convert the binary count to decoded output.
The scan lines are common for keyboard and display. The scan lines are used to form the rows of a matrix keyboard and also connected to digit drivers of a multiplexed display, to turn ON/OFF.
CPU interface section:

The CPU interface section takes care of data transfer between 8279 and the processor. This section has eight bidirectional data lines DB0 to DB7 for data transfer between 8279 and CPU.
It requires two internal address A =0 for selecting data buffer and A = 1 for selecting control register of8279.
The control signals WR (low), RD (low), CS (low) and A0 are used for read/write to 8279.
It has an interrupt request line IRQ, for interrupt driven data transfer with processor. The 8279 require an internal clock frequency of 100 kHz. This can be obtained by dividing the input clock by an internal prescaler.
The RESET signal sets the 8279 in 16-character display with two -key lockout keyboard modes.
Features:

3 8-bit IO ports PA, PB, PC PA can be set for Modes 0, 1, 2. PB for 0,1 and PC for mode 0 and for BSR. Modes 1 and 2 are interrupt driven.
PC has 2 4-bit parts: PC upper (PCU) and PC lower (PCL), each can be set independently for I or O. Each PC bit can be set/reset individually in BSR mode.
PA and PCU are Group A (GA) and PB and PCL are Group B (GB) Address/data bus must be externally demux'd. TTL compatible.
Pinout
A1 A0 Select 0 0 PA 0 1 PB 1 0 PC 1 1 Control reg.
Block diagram
BSR mode Bit set/reset, applicable to PC only. One bit is S/R at a time. Control word: D7 0 (0=BSR) D6 X D5 X D4 X D3 B2 D2 B1 D1 B0 D0 S/R (1=S,0=R)
Bit select: (Taking Don't care's as 0) B2 B1 B0 PC bit Control word (Set) Control word (reset) 0 0 0 0 0 1 0 1 0000 0001 = 01h 0000 0011 = 03h 0000 0000 = 00h 0000 0010 = 02h
0 0 1 1 1 1
1 1 0 0 1 1
0 1 0 1 0 1
2 3 4 5 6 7
0000 0101 = 05h 0000 0111 = 07h 0000 1001 = 09h
0000 0100 = 04h 0000 0110 = 06h 0000 1000 = 08h
0000 1011 = 0Bh 0000 1010 = 0Ah 0000 1101 = 0Dh 0000 1100 = 0Ch 0000 1111 = 0Fh 0000 1110 = 0Eh
I/O mode D7 1 (1=I/O) D6 D5 D4 PA D3 PCU D2 GB mode select D1 PB D0 PCL
GA mode select
D6, D5: GA mode select:

o o o
00 = mode0 01 = mode1 1X = mode2
D4(PA), D3(PCU): 1=input 0=output D2: GB mode select: 0=mode0, 1=mode1 D1(PB), D0(PCL): 1=input 0=output
Mode 0: No interrupts. Plain I/O. Two 8 bit ports PA, PB. Two 4 bit ports PCU and PCL. Outputs latched, inputs buffered.
Mode 1
(Input and output data are latched) PC bits in input mode: D7 D6 D5 D4 D3 D2 D1 D0 INTRB
PC7
PC6
IBF- INTE-A / STB- INTR- INTE-B / STBA A-bar A B-bar
IBF-B
PC bits in output mode: D7 D6 D5 D4 D3 D2 D1 D0
OBF-A- INTE-A / ACKbar A-bar
PC5 PC4
INTR- INTE-B / ACK- OBF-B- INTRA B-bar bar B
Input mode:
D4, D2: Set/Reset INTE using BSR. STB-bar input is connected to external peripheral's strobe output (i.e. PC2, PC4 pin to external strobe).
INTE is internal connection. STB-bar is external connection.
Output mode:
D6, D2: Set/Reset INTE using BSR. ACK-bar input is connected to external peripheral's acknowledge output (i.e. PC2, PC6 pin to external ack).
INTE is internal connection. ACK-bar is external connection.
Mode 2 Only for PA Status: D7 D6 D5 D4 D3 D2 D1 D0
OBF-A-bar
INTE1(O/P) ACK-A-BAR
IBF-A
INTE2(I/P) STB-A-bAR
INTR-A
The 8255 is widely used not only in many microcomputer/microcontroller systems especially Z80 based, home computers such as SV-328 and all MSX, but also in the system board of the best known original IBM-PC, PC/XT, PC/jr, etc. and clones, along with numerous homebuilt computer computers such as the N8VEM.
Functional block of 8255

The 8255 has 24 input/output pins in all. These are divided into three 8-bit ports. Port A and port B can be used as 8-bit input/output ports. Port C can be used as an 8-bit input/output port or as two 4-bit input/output ports or to produce handshake signals for ports A and B. The three ports are further grouped as follows: 1. Group A consisting of port A and upper part of port C. 2. Group B consisting of port B and lower part of port C. Eight data lines (D0 - D7) are available (with an 8-bit data buffer) to read/write data into the ports or control register under the status of the " RD" (pin 5) and WR" (pin 36), which are
active low signals for read and write operations respectively. The address lines A1 and A0 allow to successively access any one of the ports or the control register as listed below: A1 A0 Function
0 0 1 1
0 1 0 1
port A port B port C control register
The control signal "' CS" (pin 6) is used to enable the 8255 chip. It is an active low signal, i.e., when CS = '0' , the 8255 is enabled. The RESET input (pin 35) is connected to a system (like
8085, 8086, etc. ) reset line so that when the system is reset, all the ports are initialised as input lines. This is done to prevent 8255 and/or any peripheral connected to it, from being destroyed due to mismatch of ports. This is explained as follows. Suppose an input device is connected to 8255 at port A. If from the previous operation, port A is initialised as an output port and if 8255 is not reset before using the current configuration, then there is a possibility of damage of either the input device connected or 8255 or both since both 8255 and the device connected will be sending out data. The control register or the control logic or the command word register is an 8-bit register used to select the modes of operation and input/output designation of the ports
Operational modes of 8255

There are two main operational modes of 8255: 1. Input/output mode 2. Bit set/reset mode Input/output mode There are three types of the input/output mode which are as follows:
Mode 0 In this mode, the ports can be used for simple input/output operations without handshaking. If both port A and B are initialized in mode 0, the two halves of port C can be either used together as an additional 8-bit port, or they can be used as individual 4-bit ports. Since the two halves of port C are independent, they may be used such that one-half is initialized as an input port while the other half is initialized as an output port. The input/output features in mode 0 are as follows: 1. O/p are latched. 2. I/p are buffered not latched. 3. Port do not have handshake or interrupt capability. Mode 1 When we wish to use port A or port B for handshake (strobed) input or output operation, we initialise that port in mode 1 (port A and port B can be initilalised to operate in different modes, i.e., for e.g., port A can operate in mode 0 and port B in mode 1). Some of the pins of port C function as handshake lines. For port B in this mode (irrespective of whether is acting as an input port or output port), PC0, PC1 and PC2 pins function as handshake lines. If port A is initialised as mode 1 input port, then, PC3, PC4 and PC5 function as handshake signals. Pins PC6 and PC7 are available for use as input/output lines. The mode 1 which supports handshaking has following features: 1. Two ports i.e. port A and B can be use as 8-bit i/o port. 2. Each port uses three lines of port c as handshake signal and remaining two signals can be function as i/o port. 3. Interrupt logic is supported. 4. Input and Output data are latched. Mode 2
Only group A can be initialised in this mode. Port A can be used for bidirectional handshake data transfer. This means that data can be input or output on the same eight lines (PA0 - PA7). Pins PC3 - PC7 are used as handshake lines for port A. The remaining pins of port C (PC0 PC2) can be used as input/output lines if group B is initialised in mode 0. In this mode, the 8255 may be used to extend the system bus to a slave microprocessor or to transfer data bytes to and from a floppy disk controller. Bit set/reset (BSR) mode In this mode only port B can be used (as an output port). Each line of port C (PC0 - PC7) can be set/reset by suitably loading the command word register.no effect occurs in input-output mode. The individual bits of port c can be set or reset by sending the signal OUT instruction to the control register. Control word format ] Input/output mode format
The figure shows the control word format in the input/output mode. This mode is selected by making D7 = '1' .
D0, D1, D3, D4 are for lower port C, port B, upper port C and port A respectively. When D0 or D1 or D3 or D4 are "SET", the corresponding ports act as input ports. For e.g., if D0 = D4 = '1', then lower port C and port A act as input ports. If these bits are "RESET", then the corresponding ports act as output ports. For e.g., if D1 = D3 = '0', then port B and upper port C act as output ports.
D2 is used for mode selection for group B (Port B and Lower Port C). When D2 = '0', mode 0 is selected and when D2 = '1', mode 1 is selected.
D5, D6 are used for mode selection for group A (Upper Port C and Port A). The format is as follows:
D6 D5 mode 0 0 1 0 1 x 0 1 2
Example: If the 5th bit (PC5) of port C has to be "SET", then what is the control word? 1. Since it is BSR mode, D7 = '0'. 2. Since D4, D5, D6 are not used, assume them to be '0'. 3. PC5 has to be selected, hence, D3 = '1', D2 = '0', D1 = '1'. 4. PC5 has to be set, hence, D0 = '1'.

A simple schematic for interfacing the 8257 with 8085 processor is shown. The 8257 can be either memory mapped or I/O mapped in the system. In the schematic shown in figure is I/O mapped in the system. Using a 3-to-8 decoder generates the chip select signals for I/O mapped devices. The address lines A4, A5 and A6 are decoded to generate eight chip select signals (IOCS0 to IOCS-7) and in this the chip select signal IOCS-6 is used to select 8257.
The address line A7 and the control signal IO/M (low) are used as enable for decoder. The cascade pins (CAS0, CAS1 and CAS2) from the master are connected to the corresponding pins of the slave.
For the slave 8259, the SP (low) / EN (low) pin is tied low to let the device know that it is a slave.
The SP (low) / EN (low) pin can be used as input or output signal. In non-buffered mode it is used as input signal and tied to logic-I in master 8259 and logic-0 in slave 8259.
In buffered mode it is used as output signal to disable the data buffers while data is transferred from 8259A to the CPU.
It requires two internal address and they are A =0 or A = 1. It can be either memory mapped or I/O mapped in the system. The interfacing of 8259 to 8085 is shown in figure is I/O mapped in the system.
The low order data bus lines D0-D7 are connected to D0-D7 of 8259.
The address line A0 of the 8085 processor is connected to A0 of 8259 to provide the internal address.
The 8259 require one chip select signal. Using 3-to-8 decoder generates the chip select signal for 8259.
The address lines A4, A5 and A6 are used as input to decoder.
The control signal IO/M (low) is used as logic high enables for decoder and the address line A7 is used as logic low enable for decoder.
The I/O addresses of 8259 are shown in table.
Fig - Cascade Connection of 8259 INTERFACING 8259 WITH 8085 MICROPROCESSOR CASCADING 8259:
Working of 8259 with 8085 processor:
First the 8259 should be programmed by sending Initialization Command Word (ICW) and Operational Command Word (OCW). These command words will inform 8259 about the following,
1. Type of interrupt signal (Level triggered / Edge triggered). 2. Type of processor (8085/8086). 3. Call address and its interval (4 or 8) 4. Masking of interrupts. 5. Priority of interrupts. 6. Type of end of interrupts.
Once 8259 is programmed it is ready for accepting interrupt signal. When it receives an interrupt through any one of the interrupt lines IR0-IR7 it checks for its priority and also checks whether it is masked or not.
If the previous interrupt is completed and if the current request has highest priority and unmasked, then it is serviced.
For servicing this interrupt the 8259 will send INT signal to INTR pin of 8085. In response it expects an acknowledge INTA (low) from the processor. When the processor accepts the interrupt, it sends three INTA (low) one by one. In response to first, second and third INTA (low) signals, the 8259 will supply CALL opcode, low byte of call address and high byte of call address respectively. Once the processor receives the call opcode and its address, it saves the content of program counter (PC) in stack and load the CALL address in PC and start executing the interrupt service routine stored in this call address.
INTERFACING 8253 (TIMER IC) WITH 8085 PROCESSOR AIM: To interface 8253 Programmable Interval Timer to 8085 and verify the operationof 8253 in six different modes.
APPARATUS REQUIRED: 8085 Microprocessor toolkit.2)
8253 Interface board.3) VXT parallel bus.4) Regulated D.C power supply.5) CRO. MODE 0-Interrupt On Terminal Count:The output will be initially low after mode set operation. After loading the counter, theoutput will remain low while counting and on terminal count, the output will become highuntil reloaded again.Let us see the channel in mode0. Connect the CLK 0 to the debounce circuit andexecute the following program. PROGRAM: MVI A, 30H ;Channel 0 in mode 0.OUT CEHMVI A, 05H ;LSB of count.OUT C8HMVI A, 00H ;MSB of count.OUT C8HHLTIt is observed in CRO that the output of channel 0 is initially low. After giving x clock pulses, we may notice that the output goes high. MODE 1-Programmable One Shot:After loading the count, the output will remain low following the rising edge of thegate input. The output will go high on the terminal count. It is retriggerable; hence theoutput will remain low for the full count after any rising edge of the gate input.
The following program initializes channel 0 of 8253 in Mode 1 and also initializes triggering of gate. OUT 0 goes low as clock pulses and after triggering It goes back to high level afterfive clock pulses. Execute the program and give clock pulses through the debounce logic and verify using CRO. PROGRAM:
MVI A, 32H ;Channel 0 in mode 1.OUT CEH ;MVI A, 05H ;LSB of count.OUT C8HMVI A, 00H ;MSB of count.OUT C8HOUT DOH ;Trigger Gate 0.HLT MODE 2-Rate Generator: It is a simple divide by N counter. The output will be low for one period of the inputclock. The period from one output pulse to next equals the number of input count in thecount register. If the count register is reloaded between output pulses, the present period willnot be affected, but the subsequent period will reflect a new value. MODE 3-Square Generator: It is similar to mode 2 except that the output will remain high until one half of thecount and goes low for the other half provided the count is an even number. If the count isodd the output will be high for (count +1)/2 counts. This mode is used for generating baudrate of 8251. PROGRAM: MVI A, 36H ;Channel 0 in mode 3.OUT CEH ;MVI A, 0AH ;LSB of count.OUT C8HMVI A, 00H ;MSB of count.OUT C8HHLT We utilize mode 3 to generate a square wave of frequency 150 kHz at Channel 0.Set thejumper so that the clock of 8253 is given a square wave of Frequency 1.5 MHz. Thisprogram divides the program clock by 10 and thus the Output at channel 0 is 150 KHz. s v i e t k a n u r u .t k MODE 4-Software Triggered Strobe: The output is high after the mode is set and also during counting. On Terminalcount, the output will go low for one clock period and becomes high again. This mode canbe used for interrupt generation.
MODE 5-Hardware Triggered Strobe: Counter starts counting after rising edge of trigger input and the output goes low forone clock period. When the terminal count is reached, the counter is retrigerrable. Onterminal count, the output will go low for one clock period and becomes high again. Thismode can be used for interrupt generation. RESULT: Thus the 8253 PIT was interfaced to 8085 and the operations for mode 0, Mode 1and mode 3 was verified. ISPLAY CONTROLLER ESSORLXI H,4130H;Initialize counter.Mode and Display.;Clear display.;Write Display MOV
UNIT-5
UNIT-5 Basic Computer Architecture
Fig: - Computer Architecture
The main components in a typical computer system are the processor, memory, input/output devices, and the communication channels that connect them.
CENTRAL PROCESSING UNIT. The main unit inside the computer is the CPU. This unit is responsible for all events inside the computer. It controls all internal and external devices, performs arithmetic and logic operations. The operations a microprocessor performs are called the instruction set of this processor. The instruction set is "hard wired" in the CPU and determines the machine language for the CPU. The more complicated the instruction set is, the slower the CPU works. Processors differ from one another by the instruction set. If the same program can run on two different computer brands they are said to be compatible. Programs written for IBM compatible computers will not run on Apple computers because these two architectures are not compatible. There is an exception to this rule. Apple Macintosh with a program SoftPC loaded can run programs written for IBM PC. Programs like SoftPC make one CPU "pretend" to be another.
These programs are called software emulators. Although software emulators allow the CPU to run incompatible programs they severely slow down the performance.
The CPU is composed of several units...
Diagram 1. A simplified diagram of the CPU The control unit directs and controls the activities of the internal and external devices. It interprets the instructions fetched into the computer, determines what data, if any, are needed, where it is stored, where to store the results of the operation, and sends the control signals to the devices involved in the execution of the instructions. The arithmetic and logic unit (ALU) is the part where actual computations take place. It consists of circuits which perform arithmetic operations (e.g. addition, subtraction, multiplication, division) over data received from memory and capable to compare numbers.While performing these operations the ALU takes data from the temporary storage area inside the CPU named registers. Registers are a group of cells used for memory addressing, data manipulation and processing. Some of the registers are general purpose and some are reserved for certain functions. It is a high-speed memory which holds only data for immediate processing and results of this processing. If these results are not needed for the next instruction, they are sent back to the main memory and registers are occupied by the new data used in the next instruction. The microprocessor -- also known as a CPU or central processing unit -- is a complete computation engine that is fabricated on a single chip. The first microprocessor was the Intel 4004, introduced in 1971. The 4004 was not very powerful, all it could do was add and subtract,
and it could only do that 4 bits at a time. But it was amazing that everything was on one chip. Prior to the 4004, engineers built computers either from collections of chips or from discrete components (transistors wired one at a time). The 4004 powered one of the first portable electronic calculators. The first microprocessor to make it into a home computer was the Intel 8080, a complete 8-bit computer on one chip, introduced in 1974. The first microprocessor to make a real splash in the market was the Intel 8088, introduced in 1979 and incorporated into the IBM PC (which first appeared around 1982). If you are familiar with the PC market and its history, you know that the PC market moved from the 8088 to the 80286 to the 80386 to the 80486 to the Pentium to the Pentium II to the Pentium III to the Pentium 4. All of these microprocessors are made by Intel and all of them are improvements on the basic design of the 8088. The Pentium 4 can execute any piece of code that ran on the original 8088, but it does it about 5,000 times faster Memory Memory is the main component of a computer system. It stores instructions and data in binary form that is used by the central processing unit. Memories are divided into 2 types such as 1) Primary memory 2) Secondary memory
1) Primary memory: It is directly accessible by the CPU. The primary memory is of two types such as a) ROM memory b) Read /Write memory
a) Read Only Memory (ROM) this is a non-volatile memory and the data can only be read from this type of memory. ROM are three types such as
PROM (Programmable Read only Memory): it uses fusible links that can be burned by using special PROM burning circuit. It can be programmed by the user using a PROM programmer. EPROM (Erasable Programmable Read only Memory): the information stored in an EPROM can be erased by exposing the memory to ultraviolet light. EEPROM (Electrically Erasable Programmable Read only Memory): it is also same as EPROM but the erasing is done by electrical signals.
b) Read /Write memory It is a memory area where information can be written into or read whenever required by the CPU. It is required during calculation. It is also called Random access memory (RAM). RAM is of two types such as SRAM (Static RAM): It uses flip flops for storage elements. In SRAM once data is written into memory location, the data stays unchanged unless some new data is entered into that location. DRAM (Dynamic RAM): It uses capacitors as storage element. The dynamic RAM contents may change with time due to leakage of charge. So it is required to refresh the storage elements periodically. It consumes less power compare to SRAM. 2) Secondary memory: The maximum capacity of primary memory is limited. So to handle more data than allowed by primary memory, secondary memory is used. And it is non-volatile i.e. data is not lost due to current failure. Magnetic tape, Floppy disk and Hard disk are some examples of secondary memory.
Volatile memory
Volatile memory is computer memory that requires power to maintain the stored information. Most modern semiconductor volatile memory is either Static RAM or dynamic RAM . SRAM retains its contents as long as the power is connected and is easy to interface to but uses six transistors per bit. Dynamic RAM is more complicated to interface to and control and needs regular refresh cycles to prevent its contents being lost. However, DRAM uses only one transistor and a capacitor per bit, allowing it to reach much higher densities and, with more bits
on a memory chip, be much cheaper per bit. SRAM is not worthwhile for desktop system memory, where DRAM dominates, but is used for their cache memories. SRAM is commonplace in small embedded systems, which might only need tens of kilobytes or less. Forthcoming volatile memory technologies that hope to replace or compete with SRAM and DRAM include Z-RAM, TTRAM, A-RAM and ETA RAM.
Non-volatile memory
Non-volatile memory is computer memory that can retain the stored information even when not powered. Examples of non-volatile memory include read-only memory (see ROM), flash memory, most types of magnetic computer storage devices (e.g. hard disks, floppy discs and magnetic tape), optical discs, and early computer storage methods such as paper tape and punched cards. Forthcoming non-volatile memory technologies include FeRAM, CBRAM, PRAM, SONOS, RRAM, Racetrack memory, NRAM and Millipede. Virtual Memory Memory is hardware that your computer uses to load the operating system and run programs. It consists of one or more RAM chips that each have several memory modules. The amount of real memory in a computer is limited to the amount of RAM installed. Common memory sizes are 256MB, 512MB, and 1GB. Because your computer has a finite amount of RAM, it is possible to run out of memory when too many programs are running at one time. This is where virtual memory comes in. Virtual memory increases the available memory your computer has by enlarging the "address space," or places in memory where data can be stored. It does this by using hard disk space for additional memory allocation. However, since the hard drive is much slower than the RAM, data stored in virtual memory must be mapped back to real memory in order to be used. The process of mapping data back and forth between the hard drive and the RAM takes longer than accessing it directly from the memory. This means that the more virtual memory is used, the more it will slow your computer down. While virtual memory enables your computer to run more programs than it could otherwise, it is best to have as much physical memory as possible. This allows your computer to run most programs directly from the RAM, avoiding the need to
use virtual memory. Having more RAM means your computer works less, making it a faster, happier machine. Virtual memory is a part of the hard disk which is used as a memory. It has a set of memory addresses and stores the instructions or the data. When the processor executes the instructions, it converts the virtual memory addresses into real memory addresses. The main use of the virtual memory is to increase the address space. Suppose, an instruction uses the whole virtual memory area then the processor copies the essential data from the virtual memory to the main memory. Rest of the data remains in virtual memory only. The operating system divides the virtual memory into pages. This help copy virtual memory into real memory. Each page contains a fixed number of memory addresses. The hard disk stores these pages.
Logical Memory Logical memory enables the user to use large amount of memory to store data. It defines way to organize the physical memory such as RAM and cache. This enables the Operating System to arrange memory into a logical manner such as assigning a logical address. Logical address is a memory location and it is accessed by an application program. The system maps the logical address to real physical storage address. During the execution of the program, same logical address can be mapped to many different physical addresses.
Physical memory Also referred to as the physical storage or the real storage, physical memory is a term used to describe the total amount of memory installed in the computer. For example, if the computer has two 64MB memory modules installed, it has a total of 128MB of physical memory.
Dynamic RAM Dynamic RAM is the most common type of memory in use today. Inside a dynamic RAM chip, each memory cell holds one bit Of information and is made up of two parts: a transistor And a
capacitor. These are, of course, extremely small Transistors and capacitors so that millions of them can fit On a single memory chip. The capacitor holds the bit of Information -- a 0 or a 1 (see How Bits and Bytes Work for information on bits). The transistor acts as a switch that lets the control circuitry on the memory chip read the capacitor or change its state.
Static RAM Static RAM uses a completely different technology. In static RAM, a form of flip-flop holds each bit of memory (see How Boolean Gates Work for detail on flip-flops). A flip-flop for a memory cell takes 4 or 6 transistors along with some wiring, but never has to be refreshed. This makes static RAM significantly faster than dynamic RAM. However, because it has more parts, a static memory cell takes a lot more space on a chip than a dynamic memory cell. Therefore You get less memory per chip, and that makes static RAM alot more expensive.
So static RAM is fast and expensive, and dynamic RAM is less expensive and slower. Therefore static RAM is used to create the CPU's speed-sensitive cache, while dynamic RAM forms the larger system RAM space.
Magnetic core memory

Ever thought of the origin of the phrase "Core Dump"? Even today, programmers know that it means a dump (to disk or hard copy) of the contents of part of memory. And no, the phrase does not mean that it's a "central" part of memory; it means Cores, literally. Like these The "Donuts" are made of Ferrite, a material that can hold a magnetic field in either of two directions, thus representing "1" or "0". The wires through the cores allow the computer to set or read the magnetic direction.
The very first computers used bizarre memory devices such as mercury filled tubes carrying acoustic waves, or complex vacuum tube circuits. The ENIAC, the first large electronic computer, had a memory capacity of only 20 decimal numbers, and that required more than half its 18,000 vacuum tubes (unbelievable? it used flip-flops in a highly inefficient decimal notation; do the math). The breakthrough in memory technology came in 1952, when Jay W. Forrester of MIT invented Magnetic Core Memory. This technology allowed construction of core stacks of
hundreds of thousands of bytes - for a hefty but practical price. Only the arrival of Intel's Solid State DRAM technology in 1970 ousted Magnetic Core as the memory technology of choice. The cores in this exhibit are unique because they are truly HUGE. They can easily be seen as little rings by the unaided eye. This makes them an early version; later core memory, especially in the 60's, had cores that appear as tiny black dots unless you use a magnifier. The capacity of the board is also unusual - merely 400 bits, or 50 bytes, in a board 11 by 11 centimeters square.These boards, or "planes", were manufactured in "stacks", like the one on the right. Alas, I only managed to get one plane; it comes from a stack like the one in the photo, which has 10 planes, or 500 bytes.
Binary cell memory A solid state, directly overwritable, electronic, non-volatile, high density, low cost, low energy, high speed, readily manufacturable, multibit single cell memory based upon phenomenologically novel electrical switching characteristics provided by a unique class of semiconductor materials in unique configurations, which memory exhibits orders of magnitude higher switching speeds at remarkably reduced energy levels. The novel memory of the instant invention is characterized, inter alia, by numerous stable and truly non-volatile detectable configurations of local atomic and/or electronic order, which can be selectively and repeatably accessed by electrical input signals of varying pulse voltage and duration.
Flash Memory Flash Memory A memory chip that is non-volatile, re-writable that functions like a combination random access memory and a hard disk drive. In the case of power being lost, data is retained in memory. Advantages of flash memory include low voltage, durability and high speed; for this reason, flash memory is used in printers, pagers, digital cameras, audio recorders and cell phones. Cache Memory:
Cache Memory is used in-between the CPU and the RAM and holds the most frequently used data or instructions to be processed. There are three different grades of Cache. Some systems will only have level 1 and level 2. More advanced systems will include the level3. 1. Level 1 (L1) - Is the primary and is on or very close to the processor. This is used for the most frequently used data and instructions. 2. Level 2 (L2) - Is second closest to the CPU and is more common to be on the motherboard. Depending on your motherboard it might be able to be updated. This is used for the most frequently used data and instructions. 3. Level 3 (L3) - This is the most advanced cache and will speed up the memory even further. This is used for the most frequently used data and instructions. Memory bandwidth Memory bandwidth is the rate at which data can be read from or stored into a semiconductor memory by a processor. Memory bandwidth is usually expressed in units of bytes/second, though this can vary for systems with natural data sizes that are not a multiple of the commonly used 8-bit bytes. Memory bandwidth that is advertised for a given memory or system is usually the maximum theoretical bandwidth. In practice the observed memory bandwidth will be less than (and is guaranteed not to exceed) the advertised bandwidth. A variety of computer benchmarks exist to measure sustained memory bandwidth using a variety of access patterns. These are intended to provide insight into the memory bandwidth that a system should sustain on various classes of real applications. Seek Time The seek time of a hard disk measures the amount of time required for the read/write heads to move between tracks over the surfaces of the platters. Seek time is one of the most commonly discussed metrics for hard disks, and it is one of the most important positioning performance specifications. However, using this number to compare drives can be somewhat fraught with danger.
Seek time is normally expressed in milliseconds (commonly abbreviated "msec" or "ms"), with average seek times for most modern drives today in a rather tight range of 8 to 10 ms. Of course, in the modern PC, a millisecond is an enormous amount of time: your system memory has speed measured in nanoseconds, for example (one million times smaller). A 1 GHz processor can (theoretically) execute over one million instructions in a millisecond! Obviously, even small reductions in seek times can result in improvements in overall system performance, because the rest of the system is often sitting and waiting for the hard disk during this time. It is for this reason that seek time is usually considered one of the most important hard disk performance specifications. Some consider it the most important. At one point many years ago seek times were difficult to use because manufacturers wouldn't agree on a standardized way of reporting them. Today, this has largely been corrected. While seek time is usually given as a single number, in fact there are three different seek time specifications you should examine for a drive, as they represent the drive's performance when doing different types of seeks:
Average: As discussed, this is meant to represent an average seek time from one random track (cylinder) to any other. This is the most common seek time metric, and is usually 8 to 10 ms, though older drives had much higher numbers, and top-of-the-line SCSI drives are now down to as low as 4 ms!
Track-to-Track: This is the amount of time that is required to seek between adjacent tracks. This is similar in concept (but not exactly the same as) the track switch time and is usually around 1 ms. (Incidentally, getting this figure without at least two significant digits is pretty meaningless; don't accept "1 ms" for an answer, get the number after the decimal point! Otherwise every drive will probably round off to "1 ms".)
Full Stroke: This number is the amount of time to seek the entire width of the disk, from the innermost track to the outermost. This is of course the largest number, typically being in the 15 to 20 ms range. In some ways, combining this number with the average seek time represents the way the drive will behave when it is close to being full.
Memory Latency
"Latency" in computer terms is how long it takes to get a request back. It's the flip side of the coin from "bandwidth", which is how fast the data flows.
If you want to buy a movie, you can either download it or buy the DVD from Amazon. The download has good latency: you get a response to your request immediately, but the bandwidth sucks. (Or at least, it did before everybody got broadband.) Buying the DVD has great bandwidth (several gigabytes in just a few days, way faster than a modem) but the latency sucks. Good for downloading movies. Bad for surfing the web, despite the awesome bandwidth.
The same thing applies up and down the computer scale. Making a request to RAM isn't instantaneous. The electronic signal has to travel up to a few inches to get to the RAM chips, through the chips, and then back before you can use the memory. It may not seem like much, but compared to the onboard cache, it's forever. Several nanoseconds during which your computer is just twiddling its thumbs.
Memory bandwidth and memory latency are tradeoffs. The more bandwidth, the longer it takes to assemble all of the memory you need to send. That just slows you down when you really only want one byte. Computer programs optimize memory access to try to get all of the bytes they need in one request, and that's really tricky, because it can be hard to know what bytes you're going to need next.
Many different factors will go into how fast your program runs, and different programs will take advantage of different factors depending on how the memory is laid out and how the algorithms operate. It's so complicated that it's essentially impossible to know which one is best, but you'll always know that lower latency is better than higher latency all other things being equal (which they never are). ROM: A regular ROM is constructed from hard-wired logic, encoded in the silicon itself, much the way that a processor is. It is designed to perform a specific function and cannot be changed. This is inflexible and so regular ROMs are only used generally for programs that are static (not
changing often) and mass-produced. This product is analagous to a commercial software CDROM that you purchase in a store.
Programmable ROM (PROM): This is a type of ROM that can be programmed using special equipment; it can be written to, but only once. This is useful for companies that make their own ROMs from software they write, because when they change their code they can create new PROMs without requiring expensive equipment. This is similar to the way a CD-ROM recorder works by letting you "burn" programs onto blanks once and then letting you read from them many times. In fact, programming a PROM is also called burning, just like burning a CD-R, and it is comparable in terms of its flexibility.
Erasable Programmable ROM (EPROM): An EPROM is a ROM that can be erased and reprogrammed. A little glass window is installed in the top of the ROM package, through which you can actually see the chip that holds the memory. Ultraviolet light of a specific frequency can be shined through this window for a specified period of time, which will erase the EPROM and allow it to be reprogrammed again. Obviously this is much more useful than a regular PROM, but it does require the erasing light. Continuing the "CD" analogy, this technology is analogous to a reusable CD-RW.
Electrically Erasable Programmable ROM (EEPROM): The next level of erasability is the EEPROM, which can be erased under software control. This is the most flexible type of ROM, and is now commonly used for holding BIOS programs. When you hear reference to a "flash BIOS" or doing a BIOS upgrade by "flashing", this refers to reprogramming the BIOS EEPROM with a special software program. Here we are blurring the line a bit between what "read-only" really means, but remember that this rewriting is done maybe once a year or so, compared to real read-write memory (RAM) where rewriting is done often many times per second!
Random Access Memory (RAM) The kind of memory used for holding programs and data being executed is called random access memory or RAM. RAM differs from read-only memory (ROM) in that it can be both read and written. It is considered volatile storage because unlike ROM, the contents of RAM are lost when the power is turned off. RAM is also sometimes called read-write memory or RWM. This is actually a much more precise name, so of course it is hardly ever used. :^) It's a better name because calling RAM "random access" implies to some people that ROM isn't random access, which is not true. RAM is called "random access" because earlier read-write memories were sequential and did not allow random access. Sometimes old acronyms persist even when they don't make much sense any more (e.g., the "AT" in the old IBM AT stands for "advanced technology" :^) ). Obviously, RAM needs to be writeable in order for it to do its job of holding programs and data that you are working on. The volatility of RAM also means that you risk losing what you are working on unless you save it frequently. RAM is much faster than ROM is, due to the nature of how it stores information. This is why RAM is often used to shadow the BIOS ROM to improve performance when executing BIOS code. There are many different types of RAMs, including static RAM (SRAM) and many flavors of dynamic RAM (DRAM).
SDRAM: Synchronous dynamic random access memory (SDRAM) is dynamic random access memory (DRAM) that is synchronized with the system bus. Classic DRAM has an asynchronous interface, which means that it responds as quickly as possible to changes in control inputs. SDRAM has a synchronous interface, meaning that it waits for a clock signal before responding to control inputs and is therefore synchronized with the computer's system bus. The clock is used to drive an internal finite state machine that pipelines incoming instructions. This allows the chip to have a more complex pattern of operation than an asynchronous DRAM, enabling higher speeds. Pipelining means that the chip can accept a new instruction before it has finished processing the previous one. In a pipelined write, the write command can be immediately followed by another instruction without waiting for the data to be written to the memory array. In a pipelined read,
the requested data appears after a fixed number of clock pulses after the read instruction, cycles during which additional instructions can be sent. (This delay is called the latency and is an important parameter to consider when purchasing SDRAM for a computer.) SDRAM is widely used in computers; from the original SDRAM, further generations of DDR (or DDR1) and then DDR2 and DDR3 have entered the mass market, with DDR4 currently being designed and anticipated to be available in 2015.
RDRAM: Direct Rambus DRAM or DRDRAM (sometimes just called Rambus DRAM or RDRAM) is a type of synchronous dynamic RAM. RDRAM was developed by Rambus inc., in the mid-1990s as a replacement for then-prevalent DIMM SDRAM memory architecture. RDRAM was initially expected to become the standard in PC memory, especially after Intel agreed to license the Rambus technology for use with its future chipsets. Further, RDRAM was expected to become a standard for VRAM. However, RDRAM got embroiled in a standards war with an alternative technology - DDR SDRAM, quickly losing out on grounds of price, and, later on, performance. By the early 2000s, RDRAM was no longer supported by any mainstream computing architecture.
DDRAM: Double data rate synchronous dynamic random-access memory (DDR SDRAM) is a class of memory integrated circuits used in computers. DDR SDRAM (sometimes referred to as DDR1 SDRAM) has been superseded by DDR2 SDRAM and DDR3 SDRAM, neither of which are either forward or backward compatible with DDR SDRAM, meaning that DDR2 or DDR3 memory modules will not work in DDR equipped motherboards, and vice versa. Compared to single data rate (SDR) SDRAM, the DDR SDRAM interface makes higher transfer rates possible by more strict control of the timing of the electrical data and clock signals. Implementations often have to use schemes such as phase-locked loops and self-calibration to reach the required timing accuracy.[1][2] The interface uses double pumping (transferring data on both the rising and falling edges of the clock signal) to lower the clock frequency. One advantage of keeping the clock frequency down is that it reduces the signal integrity requirements on the circuit board connecting the memory to the controller. The name "double data rate" refers to the
fact that a DDR SDRAM with a certain clock frequency achieves nearly twice the bandwidth of a single data rate (SDR) SDRAM running at the same clock frequency, due to this double pumping.With data being transferred 64 bits at a time, DDR SDRAM gives a transfer rate of (memory bus clock rate) 2 (for dual rate) 64 (number of bits transferred) / 8 (number of bits/byte). Thus, with a bus frequency of 100 MHz, DDR SDRAM gives a maximum transfer rate of 1600 MB/s."Beginning in 1996 and concluding in June 2000, JEDEC developed the DDR (Double Data Rate) SDRAM specification (JESD79)."[3] JEDEC has set standards for data rates of DDR SDRAM, divided into two parts. The first specification is for memory chips, and the second is for memory modules.
PAL (Programmable Array Logic) The term Programmable Array Logic (PAL) is used to describe a family of programmable logic device semiconductors used to implement logic functions in digital circuits introduced by Monolithic Memories, Inc. (MMI) in March 1978.[1] MMI obtained a registered trademark on the term PAL for use in "Programmable Semiconductor Logic Circuits". The trademark is currently held by Lattice Semiconductor.[2] PAL devices consisted of a small PROM (programmable read-only memory) core and additional output logic used to implement particular desired logic functions with few components.Using specialized machines, PAL devices were "field-programmable". Each PAL device was "one-time programmable" (OTP), meaning that it could not be updated and reused after its initial programming. (MMI also offered a similar family called HAL, or "hard array logic", which were like PAL devices except that they were mask-programmed at the factory.)
PLA( Programmable Logic Array) The C-64 uses the PLA to implement bank switching. This lets the CPU access both 64 Kbytes RAM as well as 20 Kbytes internal ROM, various I/O hardware and any extra ROM, I/O etc. added through the use of a cartridge: By setting three of the I/O pins in the on-chip port of the 6510 CPU, and through a pair of control lines in the expansion port, access to various "zones" of ROM, RAM etc. can be enabled and disabled as needed. For example, the memory area 53248 57343/$D000$DFFF is where the VIC, SID, and CIA I/O devices are mapped into the address
space. Through bank switching via the CPU on-chip port, this I/O area can be replaced by character ROM (to make the character patterns readable by the CPU, e.g. to copy them to RAM), or provide access to the four Kbytes of underlying RAM. Caution should be taken when setting the system up in non-standard configurations: Since the standard interrupt handling routines in ROM access the I/O hardware (in order to scan the keyboard), normal interrupt operations should be disabled as long as the I/O hardware is banked out of the address space (i.e. when it's not accessible by the CPU). Likewise care should be taken to avoid the CPU trying to execute code expected from ROM, when The following table helps you to understand the differences between the different processors that Intel has introduced over the years.

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UNIT-1

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Basic Binary Decoder

Binary n-to-2n Decoders

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Example - 2-to-4 Binary Decoder

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Note: Each output is a 2-variable minterm (X'Y', X'Y, XY', XY)

Example - 3-to-8 Binary Decoder

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Implementing Functions Using Decoders

Example - Octal-to-Binary Encoder

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Example - Decimal-to-Binary Encoder

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Latches and Flip-Flops

There are two types types of sequential circuits.

Asynchronous Circuits. Synchronous Circuits.

In real world designs (ASIC/FPGA Designs) only D latches/Flip-Flops are used.

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input is held HIGH, output toggles.

Clock Speed 2 MHz 5 MHz 6 MHz 16 MHz

8080 8088 80286 80386

1974 1979 1982 1985

6,000 29,000 134,000 275,000

8 bits 16 bits, 8-bit bus 16 bits 32 bits

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32 bits 32 bits, 64-bit bus

Pentium 1993 Pentium II Pentium III Pentium IV

233 MHz 32 bits, 64-bit bus

450 MHz 32 bits, 64-bit bus

32 bits, 64-bit bus

Brief introduction to comparison of different features in 8085and 8086 microprocessors.

1.Size:8085 is 8 bit microprocessor whereas 8086 is 16 bit microprocessor.

4.Instruction Queue:Microprocessor notes Prepared by- Girraj Sharma

9.Multiplication and Division:8085 doesn't support whereas 8086 supports.

12.Cost:The cost of 8085 is low and 8086 is high.

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UNIT-2 INTRODUCTION TO MICROPROCESSOR BASEDSYSTEM

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Disadvantages of Microprocessor based System

microprocessors does not support floating point operation

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INTEL 8085 - Pin Diagram & Description

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I/O ports 256 256 Output ports Input ports

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PROGRAM COUNTER (PC):

The 8085 has five hardware interrupts

(2) RST 7.5

(3) RST 6.5

(4) RST 5.5

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