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Electric Power Systems Research 77 (2007) 721729

Control system design for VSC transmission

Dragan Jovcic a, , Lisa Lamont b,1 , Keith Abbott c,2
a b

Received 22 June 2005; received in revised form 6 April 2006; accepted 19 June 2006 Available online 4 August 2006

Abstract This paper investigates a suitable control system for a DC transmission system based on voltage source converters (VSC). Each of the two VSC converters has two control inputs and the four control channels on a VSC transmission system offer potential for a versatile control. However, the main challenge is the dynamic interaction among the control loops. It is proposed in this study that the overall system stability and good robustness should be achieved with two high-gain feedback loops, one at each converter. Eigenvalue and robustness analysis with MATLAB software shows that the best fast feedback signals are inverter DC voltage and rectier AC voltage q component. The slow controller consists of three PI controllers that regulate: rectier AC voltage, inverter AC voltage and the DC power. The VSC transmission control under fault conditions is achieved with a separate controller that takes over system control for fault-level currents. The fault controller regulates the local DC currents at each converter. The proposed controller is tested using PSCAD/EMTDC for a wide range of small-signal step inputs and the design performance is conrmed. The design is also tested for typical fault scenarios on AC and DC side to verify the fault controller operation. 2006 Elsevier B.V. All rights reserved.

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Keywords: VSC transmission; State-space methods; Thyristor converters; Root loci; Eigenvalues

1. Introduction

Corresponding author. Tel.: +44 1224 272 336. E-mail addresses: d.jovcic@abdn.ac.uk (D. Jovcic), la.lamont@ulster.ac.uk (L. Lamont), keith.abbott@areva-td.com (K. Abbott). 1 Tel.: +44 2890 368565. 2 Tel.: +44 1785 257111. 0378-7796/$ see front matter 2006 Elsevier B.V. All rights reserved. doi:10.1016/j.epsr.2006.06.011

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A voltage source converters (VSC) transmission system is generally similar to its predecessor HVDC transmission system where the main difference is the use of voltage source converters instead of line commutated converters (LCC). Because of the semiconductor technology constraints, VCS transmission is at present limited to lower power (around 300 MW), but it has already been implemented in a number of projects and it is likely to be further employed with higher voltage levels and in wider application areas [1]. The main advantage of VSC power transmission is the high controllability, the ability to control independently active and reactive power at each terminal and the possibility for linking with dead networks. These characteristics make VSC transmission attractive in many applications like the emerging interconnection with renewable energy sources. The

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disadvantages are known as higher power losses and higher capital cost compared with conventional HVDC [1,2]. The converter topologies and their ring controls are in the development stage at many research centers, but it is widely believed that some form of pulse width modulation (PWM) control with two control inputs will normally be used. From a control system standpoint, a complete VSC transmission system has four control inputs, namely modulation signal magnitude and angle at each of the two converter stations. Because of the strong interactions among the control channels, it is a truly non-linear multiple-input multiple-output (MIMO) system. Refs. [3,4] propose a method for controlling VSC transmission based on a decoupling controller at each converter station. These methods use fast-feedback to linearise, decouple and simplify the feedback dynamics for d and q axis currents. The dq current control reference inputs are further used for implementing PV (or PQ, or VDC Q) control strategies at higher control level. Ref. [5] discusses the shortcomings of current measurement lag and further improves decoupling controller using an inner predictive control loop (for a UPFC test system). The possible issues with controllers [35] in VSC transmission are identied:

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Engineering Department, University of Aberdeen, Aberdeen, Scotland AB23 3UE, UK Electrical and Mechanical Engineering, University of Ulster, Newtownabbey BT37 OQB, UK c Simulation and Studies, AREVA T & D, P.O. Box 27, Stafford ST17 4LN, UK

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Fig. 1. VSC test system schematic.

Table 1 Control system input and output pairing Input

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The aim of this study is to develop a fast VSC transmission controller with good DC voltage transient behavior at both converters, which also guarantees good stability and robustness properties. The controller should further enable current and voltage control during faults and fast fault recoveries. The design is based on a small-signal linearised VSC transmission model developed earlier on MATLAB platform [6]. It is

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Feedback linearisation/decoupling assumes that dq axis currents and DC voltage signals are available at the bandwidth higher than the main control loops. In practice, these measurements are dependent on phase locked loop (PLL) output and they are noise contaminated which reduces the frequency range for accurate measurements. Consequently, this slows the main control loops. In ref. [5] predictive current controller improves speed but only for the reference inputs, the disturbance inputs rely on the current measurements. The control system in ref. [4] operates at three levels: at the fastest level is the feedback linearisation, then the main AC current loops and the DC voltage is the slowest outer control loop. Since the DC voltage is controlled in the outer control loop, during disturbances it can have poor responses in terms of overshooting and rise/settling times. On the other hand, DC voltage control is very important with VSC converters because of balancing issues since they are currently built of large number of small semiconductor units in series connection. The same current controller is used for system protection under faults. The current controller can regulate fault currents very well, but the control gains for fault conditions are detuned to enable equally satisfactory small-signal dynamics. Such controller design considers only the local converter dynamics. The dynamics of the DC line or the interactions between the two converters, which are important with VSC transmission, are not considered. This implies larger overshooting and slower responses as shown in ref. [3].

also desired to fully test the design for wide range of step inputs (reference and disturbance) and also for a range of typical fault scenarios, on a more accurate non-linear simulator. The paper rstly reviews the analytical model for VSC transmission. The small signal design is presented in details in Sections 35, and the fault controller in Section 6. The controller is tested in Section 7. 2. The test system and modeling

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Rectier modulation signal magnitude Mmr Rectier modulation signal angle Mr Inverter modulation signal magnitude Mmi Inverter modulation signal angle Mi

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Output

The test system and the analytical MATLAB model are described in ref. [6] and only the summary is given here. The test system is a 300 MW bi-pole VSC HVDC where only one pole (150 MW) is studied for simplicity. The system consists of a rectier and inverter equivalent AC systems, the DC circuit and the controller as shown in Fig. 1, where the parameters are given in Appendix A. Each AC system has a typical short circuit level MVA of SCL = Vs2 /zth = 10, corresponding to short circuit ratio SCR = SCL/PDC = 6.6 in the nominal conguration, and R/X = 0.26. The DC system corresponds to a 100 km cable and includes the DC side capacitors, which are optimized with respect to the allowed DC voltage ripple. The controller model also includes a linearised PLL model at each converter station. The converters are two-level with bipolar PWM ring signal generation. The PWM frequency ratio is 21. The MATLAB model is a small-signal dynamic model linearised around the steady state. The model consists of three individual units: AC rectier system, AC inverter system and the DC circuit that includes all control systems. Each of these subsystems is an independent state-space model and they are linked through the state-space inputoutput matrices. This model enables eigenvalue and frequency domain studies for the overall system in a wide frequency domain. In ref. [6], the model accuracy is conrmed against non-linear simulation on PSCAD/EMTDC [7] platform, for a range of input steps.

Rectier AC voltage magnitude VACR Rectier DC power PDCR Inverter AC voltage magnitude VACI Inverter DC voltage VDCI

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Fig. 2. VSC transmission controller structure.

3. VSC transmission controller structure

The VSC transmission system is viewed as a multivariable four-input four-output plant. The control inputs and the system outputs are paired as it is shown in Table 1. If a PI control is used with each of these control loops it is possible to achieve decoupled steady-state control and output regulation as it is shown in ref. [6]. The dynamic performance of such control system is however very poor, because of the strong interactions among the control loops. Only one of the control loops in such controller can have high gains and fast performance, whereas the other variables have large overshootings and long settling times. Because of the interactions, even modest gains lead to instabilities. While the designs in refs. [35] concentrate on decoupling the two controllers at each converter, from HVDC system viewpoint this is a local approach since it neglects the DC line dynamics and the interactions between the two converters. An HVDC system with the two connecting AC systems can be viewed as a dynamic system consisting of two coupled subsystems, i.e. the rectier and the inverter system. The dynamic interactions between these two systems have important effect on VSC transmission dynamics and should be studied in controller design. To enable good robustness and disturbance rejection at each AC system, it is necessary to have a high-gain feedback controller at each converter station, as shown in the study for conventional HVDC in ref. [8]. The design in this research is directed primarily on resolving interactions between the two converters by considering dominant dynamics of the overall ACDCAC system.

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The proposed controller structure is presented in Fig. 2. There is a high-gain fast controller at rectier converter that rejects rectier side disturbances, and a fast inverter controller that improves inverter side stability. The main design effort is therefore focused on developing structure and parameters of these two loops in such way that they do not negatively interact. 4. Fast controller design The fast controller has crucial inuence on the stability, and the primary design goals are: good stability margins, good robustness for AC parameter changes at each AC system, and high performance regulation of the DC voltage. This design approach considers dynamics of the overall ACDCAC system, in developing the controller. We note that the considered ACDCAC system is complex, multivariable, higher order system (model is of 34th order), and also it is difcult to transmit on-line signals between rectier and inverter considering that the length of DC line can be very large. These considerations together with high converter harmonics make the application of conventional advanced control theories, like LQG or Hinf , very difcult. Because of importance of accurate DC voltage control, the DC voltage controller at inverter side is designed rstly. The PI controller design rules are used (assuming all other loops are disconnected). The best achievable location of eigenvalues with a single PI controller is shown in Fig. 3 as diamonds. In this gure, only several most dominant eigenvalues are shown for simplicity. We can observe that the eigenvalues (diamonds) on branches A and B have poor damping and this will lead to low quality dynamic properties.

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Fig. 3. Root locus with stabilizing VACRq feedback. Diamonds represent open loop eigenvalues (VDCI control only).

Fig. 4. Root locus with stabilizing VACRq feedback, and with the lead lter.

At the next step, a rectier fast controller is added, which is important for eliminating rectier side disturbances. An additional fast feedback loop at rectier side is designed using root locus rules and the robustness indicators. We rstly create the list of candidate rectier feedback signals and examine the system performance for each candidate signal assuming a low order feedback controller. A particular attention is paid to the feedback signal selection at rectier side in order to avoid complex highorder controllers. The candidate feedback signals are all locally available variables at the rectier converter, namely: the two components of AC voltage and AC current, active and reactive power, and DC side voltages and currents. All combinations of the ten outputs with each of the two rectier control inputs are evaluated and compared. Considering the primary design goals, the analysis is centered on eigenvalue positioning and system robustness criteria, but the input and disturbance time domain responses are also monitored. The goal is to move the two dominant eigenvalue pairs in Fig. 3 lying on the branches A and B, which are denoted by diamonds, to the left region with better damping. A systematic analysis with all candidate signals is carried and the results show that none of the 20 inputoutput combinations gives satisfactory improvement. However, the best feedback signal is the rectier AC voltage q component (VACRq ) with rectier modulation magnitude (Mmr ), which gives root locus as shown in Fig. 3. This signal is selected for feedback since it improves the position of the dominant eigenvalues (branch A), however, the improvement is modest and the eigenvalues on the branch B deteriorate. To stabilize the high frequency root locus and improve transient performance a zero is added in the rectier fast controller, represented by the lead compensator in Fig. 2. A zero in the feedback transfer function increases the angles for asymptotes in the root locus [9], thus moving roots to stable region. As the result, the nal root locus is shown in Fig. 4. We can see that the dominant oscillatory mode (branch A ) has much better damping and also other modes have improved dynamics. Most importantly however because of the good direction of root locus branches it is possible to use high-gain rectier feedback, which improves robustness.

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Fig. 5. Robust stability condition for the range of rectier AC system strength (3 < SCL < 10): (a) systems with only VDCI feedback and (b) system with VDCI feedback and an additional VACRq fast stabilizing feedback.

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The robustness is tested during the design by changing parameters of the two AC systems. Note that the AC parameters can be expected to vary during the operation because of different topologies and loading [3,8], whereas the DC system parameters are typically constant. We change the rectier and inverter

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AC system strength in a wide range 3 < SCL < 10 (corresponding to 2 < SCR < 6.6) by changing RACSR,I and LACSR,I in Fig. 1 and by keeping the impedance angle (R/X) unchanged. The system robustness is then tested using the small-gain theorem [10]. The system stability is guaranteed in the presence of multiplicative uncertainty M(s) if: M(s) < 1 T (s) (1)

where T(s) is the complementary sensitivity function. The plant transfer function with varying parameters is G(s) and it is represented using multiplicative uncertainty as: G(s) = Gn (s)(1 + M(s)) (2)

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5. Slow regulating controller design

The two fast control loops are primarily responsible for the system stability and the disturbance rejection/robustness properties. Since we are also interested in regulating the system outputs to the reference values we design PI controllers for the three loops: VACR , VACI and PDCR . These three loops do not require fast responses, they are not critical for stability, and their performance requirement is a zero-error output regulation with some reasonable settling time Ts < 400 ms. The root locus method is used assuming the system with the fast controller as the open loop plant. It is found that the inuence of slow feedback loops on the fast controller performance, and on the stability margins, is in general negative, but they must be incorporated to enable steady-state regulation of the output variables. With each loop there are three design parameters: the feedback lter constant, the PI controller zero (z = ki /kp ) and the controller gain kp . The feedback lter parameters and the location of zero will change the shape of the root locus at higher and lower frequencies, respectively, and they are rstly determined. By observing the root locus and the VDCI responses, the gains of the feedback controllers are increased to the point where they start interfering with the fast control loops (the gains are relatively low and root locus branches are short). Fig. 6 shows the root locus for the rectier AC voltage feedback controller where the open loop system is the system with fast controller (the system designed in Section 4). We observe that branch C has negative inuence and very fast approaching the Imaginary

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where Gn (s) is the nominal plant model. Fig. 5 shows the robustness testing for the rectier AC system. It is seen in Fig. 5(a) that if we do not use high-gain feedback at rectier side (only fast inverter VDC feedback control is used) the system is sensitive to the changes in the rectier AC structure and the small-gain condition is not satised. On the other hand, the system with fast feedback at rectier is able to tolerate wide changes in the AC system strength as shown in Fig. 5(b). These results show that with HVDC transmission it is very important to have two high-gain, and coordinated control loops, one at rectier and the other at inverter terminals. Similar tests demonstrate that the additional feedback loop at rectier side also improves inverter side robustness. The nal controller gains are given in Fig. 2, noted as fast controller.

Fig. 6. Slow controller design. Root locus with rectier AC voltage feedback. Diamonds represent open loop eigenvalues (fast controller).

axis implying the use of very low gains. The branch D also has negative inuence after some initial improvements for low gains. Using a similar method as in Fig. 6 and with some iterative root-locus design it is possible to design the remaining two slow loops to enable good tracking of individual reference signals and only minimal deterioration of the fast controller performance. The nally selected controller parameters are shown in Fig. 2. 6. VSC transmission control under faults

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The small signal controller in Sections 4 and 5 is designed for the operation only around the steady state. Since this controller is based on fast DC voltage control, it would act as a rm voltage source and this would cause high over-currents during faults. The controller for fault conditions has primary task of overcurrent reduction. The VSC transmission fault controller is inactive during the normal operation and it is designed to take over the system control during the fault conditions, in order to enable satisfactory fault ride-through. This is the control method that resembles the parallel current control, which is sometimes used with power electronic drives [11]. The transition between steady state and fault control is achieved using the minimum elements, as seen in Fig. 2. In general, the fault controllers can reduce fault current by either acting on the modulation magnitude or on the modulation angle control input. By reducing modulation magnitude, the AC voltage directly reduces and by keeping the AC voltage angle to zero the power transfer is reduced. However, simulation shows that the best transient (fault recovery) performance is achieved if we use modulation magnitude at inverter side and modulation angle at rectier side, as shown in Fig. 2. In this case, the fault control disables (through the minimum elements) only the slow controllers, whereas the fast small-signal control loops are still active during the faults. Therefore during the faults, at each converter we have a high-gain voltage and current controller.

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Fig. 7. Protection zone for rectier and inverter controllers. Simulated fault location is also shown.

Fig. 10. System response following a 10% DC voltage reference step. Top: DC voltage; bottom: AC terminal voltages.

Fig. 8. Current limiting controller: (a) at rectier side; (b) at inverter side.

7. Simulation results

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Fig. 7 shows the protection zone for each of the converter controllers, and also location for the simulated faults. The rectier converter controls the current in the positive direction (normal transfer direction) and it reduces overcurrents in case of faults anywhere to the right of the converter. Since it regulates the fault current in the same direction as the nominal current the rectier current limiter has current reference value at 30% above the nominal current. The current controller structure is shown in Fig. 8. The inverter converter regulates the fault currents in the negative direction, i.e. it prevents high currents in case of faults on the rectier AC system or on the DC system. It has the current reference value of 0 and the current feedback sign is positive in order to activate the controller only in the case of negative currents, as shown in Fig. 8. The current controllers are connected to the control inputs as shown in Fig. 2. In order to further reduce the fault stresses, the reference signals for steady-state controllers are reduced during faults, as represented by the reference calculation blocks in Fig. 2. The references for the rectier controllers (AC voltage and DC power) are made dependent on the low-bandwidth ltered rectier AC voltage, and similarly references on the inverter side are dependent on the inverter AC voltage, as shown in Fig. 9. This strategy reduces power transfer during faults and enables gradual fault recovery.

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Fig. 9. DC voltage reference calculation.

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7.1. Steady-state controller

The designed system is simulated in PSCAD/EMTDC and a range of tests is performed. At the simulation stage the controller gains are tuned to nal values, which are shown in Fig. 2. The new controller is compared against the decoupling predictive VSC converter as presented in ref. [5]. The predictive controller uses the same outer feedback loops as in Table 1, to enable comparison. It is labeled as predictive in gures in this section. To simplify presentation the following curve labeling is used: thick traces correspond to the new controller, and rectier side traces are dotted lines. Fig. 10 shows the system response after a 10% step on the VDCI reference. In the top graph we see that DC voltage with

Fig. 11. System response following a 10% voltage drop (negative step 130 kV117 kV) on the inverter AC source (Vsi ). Top: DC voltage; bottom: AC terminal voltages.

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Fig. 14. System response following a 10% DC voltage reference step with reduced strength at inverter side (SCL = 3).

Fig. 13. System response following a 10% DC power reference step. Top: DC power; middle: AC terminal voltages; bottom: DC voltage.

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Fig. 15. System response following a 0.1 s low resistance DC line fault. Top: DC voltage; middle: AC terminal voltages; bottom: DC current.

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the new controller responds very fast and with minimal overshooting, signicantly outperforming the predictive controller. The lower graph shows that the rectier and inverter AC voltage controllers are able to maintain the control variables at the references, but the predictive controller demonstrates lower AC disturbances as the result of internal local decoupling at each converter.

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Fig. 12. System response following a 10% voltage drop (negative step 130 kV117 kV) on the rectier AC source (Vsr ). Top: DC voltage; bottom: AC terminal voltages.

In Fig. 11, we test system for a common AC disturbance, simulated as 10% voltage drop on the (remote source Vsi in Fig. 1) inverter side. It is evident that stability and disturbance rejection with the new controller are excellent, and much better than with the predictive controller. The decoupling predictive controller cannot perform very fast in face of AC voltage disturbances. We also observe that the AC voltage controllers are able to maintain reference output values. Fig. 12 shows similar disturbance simulation on rectier side and equally good response are observed. We further observe similar magnitude of transient deviations in Figs. 11 and 12 implying that the system with the new controller is well balanced against rectier or inverter disturbances. Fig. 13 shows a 10% reference step on the DC power, conrming that slow controllers are able to regulate outputs within desired settling time. Fig. 14 is a further practical robustness testing result. The inverter AC system strength is reduced over three times, to

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D. Jovcic et al. / Electric Power Systems Research 77 (2007) 721729 Table A.1 System parameter values Notation LACSR,I LACTSR,I RACSR,I CACSR,I LDCR,I CDC n Value 0.052 H 0.033 H 4.36 1e 09 F 0.0135 H 34e 06 F 130/90 Notation CDCR,I RDCR,I PREFDCR VREFDCI VREFACR VREFACI Value 40e 06 F 1.85 150 MW 150 kV 130 kV 130 kV

SCL = 3, and a step is applied at the reference DC voltage. We note good dynamic properties and by comparing with the response in Fig. 10, only little deviation in the performance is evident. 7.2. Control under faults

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Fig. 16. System response following a ve-cycle low resistance three-phase fault at the inverter AC bus. Top: DC voltage; middle: AC terminal voltages; bottom: DC current.

model, enabling coordinated study of the overall ACDCAC system. It is postulated that system stability and good robustness can be achieved with two high-gain feedback loops: one at inverter side and another at rectier side. The two control loops can be designed using a suitable MATLAB model, following the root locus rules and robustness indicators. The best fast stabilizing feedback at rectier side is found to be AC voltage q component, which complements the high-gain DC voltage feedback at inverter side. The slow controller consists of three PI regulating control loops using as feedback signals: AC voltage at rectier side, AC voltage at inverter side, and DC power at rectier side. Under the fault conditions, VSC transmission is controlled using dedicated current controllers. The fault controllers take over system control under fault conditions by overriding two slow control loops. The simulation tests on PSCAD/EMTDC conrm that for a range of step inputs the system has high stability margins, good robustness and notably better performance than a controller based on two decoupling-predictive converter controllers. The testing for AC and DC system faults also conrm low overvoltage and low over-current responses. Acknowledgments This project is supported by Department of Employment and Learning (DEL), Northern Ireland. The authors gratefully acknowledge the resources provided by AREVA T&D UK Ltd.Power Electronic Systems. Appendix A. Parameters See Table A.1. for system parameter values. References
[1] K. Ericsson, Operational experience of HVDC light, in: Seventh International Conference on ACDC Power Transmission IEE, London, UK, 2001, pp. 119124. [2] B.R. Andersen, L. Xu, K.T.G. Wong, Topologies for VSC transmission, in: Seventh International Conference on ACDC Power Transmission IEE, London, UK, 2001, pp. 119124. [3] M. Durrant, H. Werner, K. Abbott, A comparison of current controller designs for VSC-HVDC, in: Tenth European Conference on Power Electronics and Applications, September 2003. [4] J.L. Thomas, S. Poullain, A. Benchaib, Analysis of a robust DC-bus voltage control system for a VSC transmission scheme, in: Seventh International

This section presents the system testing with fault scenarios. The following typical HVDC faults are applied: a low impedance three-phase to ground AC faults at each converter terminal, and a low impedance DC cable to ground fault. Fig. 15 shows a 0.1 s DC line fault. If not controlled, this fault would lead to very high (over 4 kA) positive rectier currents and negative inverter currents. The bottom graph demonstrates that the fault controllers are able to reduce the fault current to reference values (1.3 and 0 kA) for the fault duration, and we see that after the fault clearing transition to the steady control is fast. Note also larger transient over-voltages and over-currents with the decoupling-predictive control. Fig. 16 conrms that overvoltages and over-currents are kept low during an inverter fault. The tests with rectier faults have shown similar results. 8. Conclusions This paper presents a novel controller design for a VSC transmission system. The design is based on an accurate analytical

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D. Jovcic et al. / Electric Power Systems Research 77 (2007) 721729 Conference on ACDC Power Transmission IEE, London, UK, 2001, pp. 119124. I. Papic, P. Zunko, D. Povh, M. Weinhold, Basic control of unied power ow controller, IEEE Trans. Power Syst. 12 (November 4) (1997) 17341739. D. Jovcic, L.A. Lamont, L. Xu, VSC Transmission model for analytical studies, Power Eng. Soc. Gen. Meet. IEEE 3 (July 1317) (2003) 17371742. Manitoba HVDC research Center PSCAD/EMTDC users manual, Winnipeg, 2003. D. Jovcic, N. Pahalawaththa, M. Zavahir, Inverter controller for very weak receiving AC systems, IEE Proc. Gen. Transm. Distrib. 146 (May 3) (1999) 235240. K. Ogata, Modern Control Engineering, Prentice Hall International, 1997. S. Skogestad, I. Postlethwaite, Multivariable Feedback Control, John Wiley and Sons, 1996. N. Mohan, T.M. Undeland, W.P. Robbins, Power Electronics Converters, in: Applications and Design, John Wiley & Sons, 1995.

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with the University of Aberdeen, Scotland, where he has been since 2004. He also worked for the University of Ulster in period 20002004 and as a design engineer in the New Zealand power industry from 19992000. His research interests lie in the areas of control systems, HVDC systems and FACTS. He is a member of IEEE. Lisa Lamont obtained B.E. (Hons.) degree from University of Ulster, UK in 2001 and is currently studying for Ph.D. degree from the University of Ulster, UK. Her research areas of interest are FACTS and control systems. She is a student member of IEEE. Keith Abbott obtained his B.Sc. (Hons.) in Electrical Engineering in 1966 and M.Sc. by research at the University of Newcastle-upon-Tyne, England.He lectured from 1966 to 1981 at Sunderland Polytechnic in the Department of Electrical, Electronic & Control Engineering. From 1981 to 1997, he was head of department of Electrical & Electronic Engineering and associate dean of Engineering at Staffordshire University. Keith joined ALSTOM T&D Power Electronic Systems in 1997 and is currently manager of the Simulation and Studies Department, responsible for all ALSTOMs HVDC, SVC and STATCOM analysis. Keith has published 20 technical papers and is a Chartered Engineer, member of the IEE, Member of the IEEE and Member of CIGRE Working Group 38-14 Simulation of HVDC and FACTS.

[6]

[7] [8]

[11]

Dragan Jovcic obtained a B.Sc. in Control Engineering from the University of Belgrade, Yugoslavia in 1993 and Ph.D. degree in Electrical Engineering from the University of Auckland, New Zealand in 1999. He is currently a lecturer

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[9] [10]

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