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Dual Edge Clocking

Programmable or Variable Burst Length
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United States Patent 6,715,020

Farmwald , et al. March 30, 2004

Synchronous integrated circuit device

Abstract
A controller device for controlling a synchronous dynamic random access memory device. The
controller device includes output driver circuitry to output block size information to the memory
device. The block size information defines an amount of data to be output by the memory device.
In addition, the controller device includes input receiver circuitry to receive the amount of data
output by the memory device.

What is claimed is:

1. A controller device for controlling a synchronous dynamic random access memory device, the
controller device comprises: first output driver circuitry to output block size information to the
memory device, wherein the block size information defines an amount of data to be output by the
memory device; and input receiver circuitry to receive the amount of data output by the memory
device.

3. The controller device of claim 2 wherein the operation code is included in a packet.

4. The controller device of claim 3 wherein the block size information and the operation code are
included in the packet.

6. The controller device of claim 2 wherein the first output driver circuitry and the second output
driver circuitry output address information to the memory device.

7. The controller device of claim 6 wherein the block size information, the address information
and the operation code are output to the memory device via an external bus.

8. The controller device of claim 7 wherein the external bus includes a plurality of signal lines to
carry, in a multiplexed format, the block size information, the operation code and the address
information.

9. The controller device of claim 1 further including delay looked loop circuitry, coupled to the
input receiver circuitry, to generate an internal clock signal, wherein the input receiver circuitry
samples the amount of data in response to the internal clock signal.
10. The controller device of claim 1 further including delay locked loop circuitry, coupled to the
first output driver circuitry, to generate an internal clock signal, wherein the first output driver
circuitry outputs the block size information synchronously with respect to the internal clock signal.

11. The controller device of claim 10 wherein the delay locked loop circuitry includes at least one
variable delay line used in the generation of the internal clock signal.

12. The controller device of claim 11 wherein the delay locked loop circuitry includes more than
one variable delay line used in the generation of the internal clock signal.

13. The controller device of claim 1 wherein the block size information is a binary code.

14. The controller device of claim 1 wherein the input receiver circuitry samples: a first portion of
the amount of data during a first half of a clock cycle of an external clock signal; and a second
portion of the amount of data during a second half of the clock cycle of the external clock signal.

15. The controller device of claim 1 wherein the input receiver circuitry samples: a first portion of
the amount of data in response to a rising edge of an external clock signal; and a second portion
of the amount of data in response to a falling edge of the external clock signal.

16. The controller device of claim 1 further including a clock receiver to receive an external clock
signal, wherein, during a clock cycle of an external clock signal, the input receiver receives two
bits of data from an external signal line, wherein the two bits of data are included in the amount of
data output by the memory device.

39. The controller device of claim 38 wherein the operation code is included in a packet.

40. The controller device of claim 39 wherein the block size information and the operation code
are included in the packet.

42. The controller device of claim 38 wherein both the first plurality of output drivers and the
second plurality of output drivers output address information to the memory device.

43. The controller device of claim 42 wherein the block size information, the operation code, and
the address information are output, in a multiplexed format, to the memory device via an external
bus.

44. The controller device of claim 38 further including a clock receiver to receive an external clock
signal, wherein the first plurality of output drivers outputs the block size information synchronously
with respect to the external clock signal.

45. The controller device of claim 44 further including a delay locked loop coupled to the clock
receiver and the plurality of input receivers, wherein the delay locked loop generates an internal
clock signal, and wherein the plurality of input receivers samples the amount of data in response
to the internal clock signal.

46. The controller device of claim 44 further including a delay locked loop coupled to the first
plurality of output drivers and the clock receiver, wherein the delay locked loop generates an
internal clock signal, and wherein the first plurality of output drivers outputs the block size
information in response to the internal clock signal.

47. The controller device of claim 38 wherein the block size information is a binary code.

48. The controller device of claim 38 further including a clock receiver to receive an external clock
signal, wherein: the plurality of input receivers samples a first portion of the amount of data during
a first half of a clock cycle of the external clock signal; and the plurality of input receivers samples
a second portion of the amount of data during a second half of the clock cycle of the external
clock signal.

49. The controller device of claim 38 wherein, during a clock cycle of an external clock signal, the
plurality of input receivers samples two bits of data of the amount of data output by the memory
device via an external signal line.

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United States Patent 6,697,295

Farmwald , et al. February 24, 2004

Memory device having a programmable register

Abstract
The present invention includes a memory subsystem comprising at least two semiconductor
devices, including at least one memory device, connected to a bus, where the bus includes a
plurality of bus lines for carrying substantially all address, data and control information needed by
said memory devices, where the control information includes device-select information and the
bus has substantially fewer bus lines than the number of bits in a single address, and the bus
carries device-select information without the need for separate device-select lines connected
directly to individual devices. The present invention also includes a protocol for master and slave
devices to communicate on the bus and for registers in each device to differentiate each device
and allow bus requests to be directed to a single or to all devices. The present invention includes
modifications to prior-art devices to allow them to implement the new features of this invention. In
a preferred implementation, 8 bus data lines and an AddressValid bus line carry address, data
and control information for memory addresses up to 40 bits wide.

What is claimed is:

1. A method of operation of a synchronous memory device, wherein the memory device includes
an array of memory cells and a programmable register, the method of operation of the memory
device comprises: sampling a first operation code synchronously with respect to a transition of an
external clock signal; receiving a binary value synchronously with respect to the external clock
signal, wherein the binary value is representative of a delay time to transpire before the memory
device is to output data in response to a second operation code, wherein the second operation
code specifies a read operation to the memory device; and storing the binary value in the
programmable register in response to the first operation code.

2. The method of claim 1 wherein the first operation code is included in a control register access
request packet.

3. The method of claim 2 wherein the first operation code and the binary value are included in the
same control register access request packet.

4. The method of claim 1 wherein the delay time is representative of a number of clock cycles of
the external clock signal.
5. The method of claim 4 further including: receiving the second operation code; and outputting
the data, in response to the second operation code, after the number of clock cycles of the
external clock signal transpire.

6. The method of claim 5 further including sampling address information synchronously with
respect to the external clock signal.

7. The method of claim 6 wherein the address information and the second operation code are
included in a read request packet.

8. The method of claim 1 further including: receiving block size information, wherein the block
size information is representative of an amount of data to be output; receiving the second
operation code; and outputting the amount of data, in response to the second operation code,
after the delay time transpires.

9. The method of claim 8 wherein the block size information further defines an amount of data to
be input in response to a third operation code, wherein the third operation code specifies a write
operation to the memory device, the method further including: receiving the third operation code;
and inputting the amount of data in response to the third operation code.

10. The method of claim 9 wherein the third operation code is included in a write request packet.

11. The method of claim 10 wherein the block size information and the third operation code are
included in the same write request packet.

12. The method of claim 1 further including: receiving the second operation code; and outputting
data in response to the second operation code, wherein the data is output synchronously with
respect to consecutive rising and falling edge transitions of the external clock signal.

13. The method of claim 1 wherein the first operation code is received during an initialization
sequence after power is applied to the memory device.

14. The method of claim 1 wherein the first operation code is sampled from an external bus.

15. The method of claim 14 wherein the external bus includes a plurality of signal lines, and
wherein the binary value and the first operation code are multiplexed over the plurality of signal
lines.

16. A method of controlling a synchronous memory device by a controller, wherein the memory
device includes an array of memory cells and a programmable register, the method of controlling
the memory device comprises: issuing a first operation code to the memory device, wherein the
first operation code specifies an access of the programmable register in the memory device in
order to store a binary value, wherein the binary value is representative of control information;
and providing the binary value to the memory device, wherein the memory device stores the
binary value in the programmable register in response to the first operation code.

17. The method of claim 16 wherein the control information is representative of a number of clock
cycles of an external clock signal to transpire before the memory device outputs data in response
to a second operation code.

18. The method of claim 17 further including: issuing the second operation code to the memory
device; and receiving data output by the memory device after the number of clock cycles of the
external clock signal transpire.

19. The method of claim 18 further including providing address information to the memory device
synchronously with respect to the external clock signal.
20. The method of claim 19 wherein the address information and the second operation code are
included in a request packet.

21. The method of claim 16 further including: providing block size information to the memory
device, wherein the block size information defines an amount of data to be output by the memory
device in response to a second operation code; issuing the second operation code to the memory
device; and receiving the amount of data output by the memory device.

22. The method of claim 21 wherein the block size information further defines an amount of data
to be input by the memory device in response to a third operation code, the method further
including: issuing the third operation code to the memory device; and providing the amount of
data to the memory device.

23. The method of claim 16 wherein the first operation code and the binary value are included in
a request packet.

24. The method of claim 23 wherein the first operation code and the binary value are included in
the same request packet.

25. The method of claim 16 wherein the first operation code is issued to the memory device via
an external bus.

26. The method of claim 25 wherein the external bus includes a plurality of signal lines, and
wherein the binary value and the first operation code are multiplexed over the plurality of signal
lines.

27. The method of claim 16 wherein the control information includes a device type identifier.

28. The method of claim 16 wherein the control information identifies a location of a defective
portion of the array of memory cells.

29. The method of claim 16 wherein the control information identifies a range of addressable
locations of the array of memory cells.

30. The method of claim 16 wherein the control information includes a device identification value
to identify the memory device uniquely among a plurality of memory devices.

31. A synchronous memory device including an array of memory cells, the synchronous memory
device comprising: a clock receiver to receive an external clock signal; a plurality of input
receivers to sample a first operation code synchronously with respect to a transition of the
external clock signal; and a programmable register to store a binary value that is representative of
control information, wherein the memory device stores the binary value in the programmable
register in response to the first operation code.

32. The memory device of claim 31 wherein the control information is representative of a number
of clock cycles of the external clock signal to transpire before the memory device outputs data,
and wherein the memory device outputs the data in response to a second operation code.

33. The memory device of claim 32 further including a plurality of output drivers to output the
data, after the number of clock cycles of the external clock signal transpire, in response to the
second operation code.

34. The memory device of claim 31 further including a plurality of output drivers to output data in
response to a second operation code, wherein the second operation code specifies a read
operation, and wherein the plurality of output drivers output a first portion of the data
synchronously with respect to a rising edge transition of the external clock signal and output a
second portion of the data synchronously with respect to a falling edge transition of the external
clock signal.

35. The memory device of claim 31 wherein the first operation code is included in a request
packet.

36. The memory device of claim 31 wherein the first operation code and the binary value are
each included in a request packet.

37. The memory device of claim 36 wherein the first operation code and the binary value are
included in the same request packet.

38. The memory device of claim 31 wherein the plurality of input receivers are operative to
receive a second operation code, wherein the second operation code specifies a write operation
to the memory device, and wherein the memory device further includes additional input receivers
to input data in response to the second operation code.

39. The memory device of claim 31 wherein the array of memory cells includes dynamic random
access memory cells.

40. The memory device of claim 31 wherein the plurality of input receivers sample the first
operation code from an external bus.

41. The memory device of claim 40 wherein the external bus includes a plurality of signal lines,
and wherein the first operation code and the binary value are multiplexed over the plurality of
signal lines.

42. The memory device of claim 41 wherein data, the first operation code and the binary value
are multiplexed over the plurality of signal lines.

46. The memory device of claim 45 wherein the programmable register is included in a plurality of
programmable registers of the memory device, each register of the plurality of registers to store a
corresponding binary value.

47. The memory device of claim 31 wherein the control information includes a device identifier.

48. The memory device of claim 31 wherein the control information identifies a location of a
defective portion of the array of memory cells.

49. The memory device of claim 31 wherein the control information identifies a range of
addressable locations of the array of memory cells.

50. The memory device of claim 31 wherein the control information includes a device
identification value to identify the memory device uniquely among a plurality of memory devices.

51. The memory device of claim 31 further including a plurality of registers, wherein the
programmable register is included in the plurality of registers, and wherein the plurality of
registers further includes at least one of: a first register to store a value that identifies the memory
device uniquely among a plurality of memory devices; a second register to store a value that
identifies a range of addressable locations of the array of memory cells; and a third register to
store a value that identifies a location of a defective portion of the array of memory cells.

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United States Patent 6,324,120

Farmwald , et al. November 27, 2001

Memory device having a variable data output length

Abstract
A synchronous memory device and methods of operation and controlling such a device. The
method of controlling the memory device includes providing block size information to the memory
device, synchronously with respect to an external clock signal, wherein the block size information
defines an amount of data to be output by the memory device in response to a read request. The
method further includes issuing a first read request to the memory device, wherein the memory
device receives the first read request synchronously with respect to a transition of the external
clock signal.

What is claimed is:

12. The method of claim 1 further including:

receiving a value which is representative of a number of clock cycles of the external clock signal
to transpire before the memory device outputs the data; and

receiving a third operation code wherein the third operation code instructs the memory device to
store the value in a programmable register on the memory device.

13. The method of claim 12 wherein the memory device outputs the data on an external bus after
the number of clock cycles of the external clock signal transpire.

14. The method of claim 12 wherein the external bus includes a plurality of signal lines to
multiplex control information, address information, and the amount of data.

17. The method of claim 15 further including providing a binary value to the memory device,
wherein the binary value is representative of a number of clock cycles of the external clock signal
to transpire before the memory device outputs the amount of data in response to the first
operation code

19. The method of claim 15 wherein the first operation code is issued synchronously with respect
to a rising or falling edge transition of the external clock signal.

28. The memory device of claim 27 wherein a first portion of the amount of data is output
synchronously with respect to a rising edge transition of the external clock signal and a second
portion of the amount of data is output synchronously with respect to a falling edge transition of
the external clock signal.

33. The memory device of claim 29 wherein the first operation code includes precharge
information.

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