Signal

Flow Graphs
Roger Woods
r.woods@qub.ac.uk Programmable Systems Lab ECIT, Queens University Belfast (Slides 2-13 taken from Signal Flow Graphs and Data Flow Graphs chapter by Keshab K. Parhi and Yanni Chen)

Contents
Signal Flow Graphs (SFGs)
Masons Gain Formula

DSP characterisTcs Transfer FuncTon DerivaTon of SFG

Data Flow Graphs (DFGs)

DFG representaTons Equivalent Single-rate from MulT-rate DFG ReTming Pipelining

SFG/DFG transformaTons

Signal Flow Graph RepresentaTon

DSP characterisTcs
Data independence Input samples are processed periodically (typically a clock) Tasks are repeated innite number of Tmes => non- terminaTng programs High computaTonal requirements
Trend towards DSP micros and FPGAs

Towards SFGs (and DFGs)

powerful representaTons of signal processing algorithms as they represent the operaTons using a nite number of nodes
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Key features of SFGs

SFGs can be transformed using reTming, pipelining, unfolding and folding resulTng forms have same input-output characterisTcs but dierent constraints

Pipelining and reTming can be used to reduce clock period Folding can be used to Tme-mulTplex i.e. reduce area Unfolding leads to:
lower iteraTon periods in so`ware implementaTons (by highlighTng concurrency) Faster hardware by exploiTng parallel implementaTons

Key goal of transforming representaTon to meet performance requirements by adapTng levels of pipelining and parallelism (or both)
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Signal Flow Graph

SFG is a collecTon of nodes and directed edges

A directed edge (j,k) denotes a linear transform from the signal at node j to the signal at node k Edges are usually restricted to mulTplier or delay elements
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TransposiTon
Flow graph reversal/transposiTon can be applied to single-input single-output (SISO) systems by reversing direcTons of all edges, exchanging input/output nodes while keeping edge gain or edge delay unchanged

Mason's gain formula

A few useful terminologies in Mason's gain formula have to be dened related to an SFG
Forward path: a path that connects a source node to a sink node in which no node is traversed more than once. Loop: a closed path without crossing the same point more than once. Loop gain: the product of all the transfer funcTons in the loop. Non-touching or non-interacTng loops: two loops are non- touching or non-interacTng if they have no nodes in common.
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Mason's gain formula

M = transfer funcTon or gain of the system Y = output node X = input node N = total number of forward paths between X and Y = determinant of the graph = 1- loop gains + non-touching loop gains taken two at a Tme - non-touching loop gains taken three at a Tme + Mj = gain of the jth forward path between X and Y j = 1-loops remaining a`er eliminaTng the jth forward path i.e. eliminate the loops touching the jth forward path from the graph. If none of the loops remains, j = 1.
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SFG example

1) Find the forward paths and their corresponding gains Two forward paths exist in this SFG: M1 = G1G2G3 and M2 = G4 2) Find the loops and their corresponding gains There are four loops in this example: Loop1 = -G1H1 Loop2 = -G3H2 Loop3 = -G1G2G3H3 Loop4 = -G4H3
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SFG example (Contd)

3) Find the j If we eliminate the path M1 =G1G2G3 from the SFG, no complete loops remain, so 1 = 1. Similarly, if the path M2 =G4 is eliminated from the SFG, no complete loops remain neither, so 2 = 1 as well. 4) Find the determinant Only one pair of non-touching loops is in this SFG, i.e. Loop1 and Loop2, thus non-touching loop gains taken two at a Tme = (-G1H1)(-G3H2). Therefore,

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SFG example (Contd)

= 1- loop gains + non-touching loop gains taken 2 at a Tme = 1 - (- G1H1 - G3H2 - G1G2G3H3 - G4H3) + (-G1H1)(-G3H2) = 1 + G1H1 + G3H2 + G1G2G3H3 + G4H3 + G1G3H1H2 5) The nal step is to apply the Mason's gain formula

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Data Flow Graph

In DFGs, nodes represent computaTons/funcTons and directed edges represent data paths with non- negaTve numbers associated with them Captures data-driven property of DSP algorithms - node res when all input data is available.

yn = ayn-1 + xn Block diagram ConvenTonal DFG Synchronous DFG

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SDFGs and mulT-rate

Synchronous DFG is a DFG special case where the number of data samples produced or consumed by each node in each execuTon is specied a priori can be used for mulT-rate
A, B &C operate at frequencies fA, fB & fC A consumes fA samples & produces 3fA samples per Jme unit. B consumes 5fB samples, therefore using equality 3fA = 5fB , we have fB =3 fA /5. Similarly, fC = 2fB /3 = 2fA/5 which can be used to compute the frequencies for A, B and C for a specied required input sample rate. Equivalent SFG
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SequenTal algorithms
OperaTons are one a`er other. Throughput dictated by the Tme to perform P1, P2 and P3.

OperaTons can be carried out at the same Tme.

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Some deniTons - Latency

Latency Tme needed to generate an output from when the corresponding input is entered. Throughput rate is dened as the rate at which the outputs (and/or inputs) are produced.

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Why is latency important?

Latency can dictate performance in applicaTons with feedback loops

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MulTplexing
Technique to increase the throughput rate of sequenTal algorithms Processors (PEs) will operate in a Tme shared fashion.

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MulTplexing
SequenTal: TR = 1/(tP1+ tP2+ tP3) and output every cycle. E.g. if tP1= tP2= tP3=10, TR=1/30
tPn time taken for processor Pn

Interleaved: TR = 1/ (tP1or tP2or tP3) E.g. if tP1= tP2= tP3=10, TR=1/10

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Some deniTons - pipelining

Method to increase the throughput rate of a sequenTal (and parallel) algorithm TR = 1/ (tP1or tP2or tP3) If tP1= tP2= tP3=10, TR=1/10 Problems in feedback loops allow interleaving only.

clock rate = f clock rate = 4Xf output = 1 per cycle output = 1 per 4 cycles TR = f TR = f

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ApplicaTon of pipelining #1

2
Clock 0 1 2 3 4 Input x0 x1 x2 x3 x4 Node 1 a0x0 a0x1 a0x2 a0x3 a0x4 a0x0 a0x1 + a1x0 a0x2 + a1x1 a0x3 + a1x2 a 0 x0 a0x1 + a1x0 a0x2 + a1x1 + a2x0 a0x3 + a1x2 + a2x1 y0 y1 y2 y3 Node 2 Node 3

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Output

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ApplicaTon of pipelining #2
Why not apply pipelining to adder chain in FIR lter?

1 2 3

Clock 0 1 2 3 4

Input x0 x1 x2 x3 x4

Node 1 a0x0 a0x1 a0x2 a0x3 a0x4

Node 2 a0x0 a0x1 + a1x0 a0x2 + a1x1 a0x3 + a1x2

Node 3

Output

a0x0 a0x1 + a1x0 + a2x0 a0x2 + a1x1+ a2x1

y0 X X
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Formal method to apply pipelining

Problem was that pipelining was not applied in a systemaTc fashion providing a funcTonal change in the system specicaTon i.e. changing the actual funcTon. A systemaTc approach is thus required to apply reTming to the system in such a way that it does not corrupt the system specicaTon. ReTming equates to moving around exisTng delays
Does not alter the latency of the system Reduces (hopefully) the criTcal path of the system Can be employed to reTme the node

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FormulaTon of reTming
ReTming FormulaTon

w = w + r(V) - r(U) ProperTes of reTming

Weight of the reTmed path p = V0 --> V1 --> ..Vk is given by wr(p)= w (p) + r(Vk) - r(V0) ReTming does not change the number of delays in a cycle. ReTming does not alter the iteraTon bound (see later) in a DFG as the number of delays in a cycle does not change Adding the constant value j to the reTming value of each node does not alter number of delays in edges of the reTmed graph.
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ReTming of FIR Filter

Express as DFG wr(1 2) = w(1 2) + r(2)- r(1) 2,3,4 are mulTpliers, wr(1 3) = w(1 3) + r(3)- r(1) 5, 6 are adders, 1 is x input wr(1 4) = w(1 4) + r(4)- r(1) Can express relaTonships wr(2 5) = w(2 5) + r(5)- r(2) for all edges wr(3 5) = w(3 5) + r(5)- r(3) wr(4 6) = w(4 6) + r(6)- r(4) wr(5 6) = w(5 6) + r(6)- r(5) 24

ReTming of FIR Filter

Using the following reTming values, we get a pipeline a`er the mulTpliers
wr(1 2) = w(1 2) + r(2)- r(1) = 0 + (-1) (-1) = 0 wr(1 3) = w(1 3) + r(3)- r(1) = 1 + (-1) (-1) = 1 wr(1 4) = w(1 4) + r(4)- r(1) = 2 + (-1) (-1) = 2 wr(2 5) = w(2 5) + r(5)- r(2) = 0 + (0) (-1) = 1 wr(3 5) = w(3 5) + r(5)- r(3) = 0 + (0) (-1) = 1 wr(4 6) = w(4 6) + r(6)- r(4) = 0 + (0) (-1) = 1 wr(5 6) = w(5 6) + r(6)- r(5) = 0 + (0) (0) = 0
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r(1)=-1, r(2)=-1, r(3)=-1, r(4)=-1, r(5)=0, r(6)=0

Conclusions
RepresentaTons for DSP systems
Signal Flow Graphs (SFGs) Data Flow Graphs (DFGs)
Transfer FuncTon DerivaTon using Masons Gain Formula Various form including synchronous DFG ConstrucTng an Equivalent Single-rate DFG from MulT-rate

TransformaTons

Pipelining allows speed of resulTng implementaTons to be increased. ReTming can be used to perform delay transfer but that is only part of the issue. Can increase(unfold)/decrease(fold) parallelism to match performance covered later
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