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Core Overview:The
Common Flash MemoryInterface Controller IP Core is a hardware component that facilitates the use of flash memory devices present on the Altera Cyclone FPGA board. The document describes thefunctionality ofCFIController IP Core.
top_clk top_rst_n top_read top_write top_ cs top_address_in top_write_data top_read_data top_wt_req top_beginburst top_burst_count top_vio top_address_out top_ce_n
CFI Controller
Pin Description:
Inputs :Inputs to the CFI controller.
top_clk: clock to the controller. top_rst_n: Active low reset to the controller. top_write , read ,chipselect : The other output signals are 1-bit wide each, and control data transfer. top_address_in, top_write_data, top_read_data : Input signals to the controller from the which consists of data &adress . top_wt_req: Controller is busy when it is set to 0, controller is ready when it is set to 1.
Core Diagram:
clk
rst_n
rs_ry_by rs_wt_data rs_address rs_rd_data
write read begin_burst cs addressrs_ write_data read_data wt_req burst_count Register Set
Control Register:The Control register is 8 bit wide. The first (LSB) three bits are used in control register. The 0th bit is high it indicates, Controller will do reading operation. If 1st bit is high it indicates, controller will do writing operation. If 2nd bit is high it indicates it is busy. Data Register (Input):It is a 15 bit register, It gets the data from bus,Data in the register is fromthe controller. Data Register (Output): It is a 15 bit register, It gets the data from the controller,Data in the register is from bus for every read. Address Register: It is a 25 bit register, It indicates read address and write address. Reset Register: It is a Single bit register,which receives reset signal from the bus. The CFIController Core consists of bus interface signals on the left-hand side, and a flash memory chip signals on the right-hand side. The signals from the bus are storing in a register set. The stored signals in the register set are used to allow the flashmemory to be read, written and erased.The flash
memory controller signals shown on the right hand side connect to the flash memory device on a FPGA board.