M.tech Lab Record VHDL

MALINENI LAKSHMAIAH ENGINEERING COLLEGE
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LOGIC GATES
AIM:
a. Write a program for digital circuit using VHDL.
b. Verify the functionality of designed circuit.
c. Give the Timing simulation for critical path time calculation & also
synthesis for Digital Circuit.
d. Implement the place & route technique for major FPGA vendor i.e., XILINX
e. Implement the designed digital circuit using FPGA &CPLD devices.
APPARATUS:
1. Computer system
2. Xilinx 7.0 software tool
PROCEDURE:
Double click on XILINX ISE ICON.
Click on file and new project.
Enter the project name and location click on next.
Choose the settings & click on next & finally click on finish.
Double click on create new source.

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Choose VHDL module & enter the file name click o next.
Enter the post name & Select the direction & click on next & finish finally.
Write the program & click on program name in source window.
Click ont ICON of synthesis-xst then double click on the check syntax option.
Once check syntax is completed successfully, you can go for simulation.
Choose sources for behavioral simulation and click on the program name you will
get model sim simulator option on the process window.
Click on + icon of model sim simulator then double click on simulator

behavioral simulation.
Click on + (ZOOM) icon to maximize the window of waveform.

Right click on the signal and select the force value.
Change the value from U to either 0 or 1 and click OK and click on run icon &
similarly vary the inputs value for all possible options and observe the output.
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Close the model sim simulator and come back to implementation in the source
for options.
Click on + icon of user constraints and double click on floor plan ID preSynthesis.
Click on Yes and enter the pin numbers in the LOC column and click on save
icon and click on OK.
Double click on configure target device & click on yes.
Turn on the power for the board and click on finish.
Two devices will get identified click on bypass when devices XCF02S is selected.
Click on the .bit file & select open when device XC3S400 is selected and click
OK.
Right click on device XC3S400 and choose program option by clicking of right
click and click on OK.
Impact will start to download the bit file to board.

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Once you got the program succeeded message ,you can test the output on
board.
See the output ports by varying the input ports.
VHDL PROGRAM:
ANDGATE:
Behavioral Model:
Library IEEE;
Use IEEE. STD_LOGIC_1164.all;
Entity and_gate is
Port (
in
STD_LOGIC;
in
STD_LOGIC;
out
STD_LOGIC);
end and_gate;

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Architecture and_gate_beh of and_gate is
Begin
process(a, b)
begin
if a = '1' and b = '1' then c <= '1';
else c <= '0';
end if;
end process;
end and_gate_beh;
Dataflow Model:
Library IEEE;
Entity and_gate is
Port (
in
STD_LOGIC;
in
STD_LOGIC;
out
STD_LOGIC);
end and_gate;
Architecture and_gate_df of and_gate is
Begin
c <= a and b;
end and_gate_df;
Structural Model:
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Library IEEE;
Entity and_gate is
Port (
in
STD_LOGIC;
in
STD_LOGIC;
out
STD_LOGIC);
end and_gate;
Architecture and_str of and_gate is
component and_gate
Port (
in
STD_LOGIC;
in
STD_LOGIC;
out
STD_LOGIC);
end component;
begin
U1
and_gate port map (a,b,c);
end and_str;

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LOGIC SYMBOL AND TRUTH TABLE:

AND GATE
TRUTH TABLE

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SIMULATION RESULTS:

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OR GATE:
Behavioral Model:
Library IEEE;
Entity or_gate is
Port (
in
STD_LOGIC;
in
STD_LOGIC;
out
STD_LOGIC);
end or_gate;
Architecture or_gate_beh of or_gate is
Begin
process(a, b)
begin
if a = '0' and b = '0' then c <= '0';
else c <= '1';
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end if;
end process;
end or_gate_beh;
Dataflow Model:
Library IEEE;
Entity or_gate is
Port (
in
STD_LOGIC;
in
STD_LOGIC;
out
STD_LOGIC);
end or_gate;
Architecture or_gate_df of or_gate is
Begin
c <= a or b;
end or_gate_df;
Structural Model:
Library IEEE;
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Entity or_gate is
Port (
in
STD_LOGIC;
in
STD_LOGIC;
out
STD_LOGIC);
end or_gate;
Architecture or_str of or_gate is
component or_gate
Port (
in
STD_LOGIC;
in
STD_LOGIC;
out
STD_LOGIC);
end component;
begin
U1
or_gate port map(a,b,c);
end or_str;
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OR GATE
TRUTH TABLE
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SIMULATION RESULTS:
ORGATE:-
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NOT GATE:
Behavioral Model:
Library IEEE;
Entity not_gate is
Port (
in
STD_LOGIC;
out
STD_LOGIC);
end not_gate;
Architecture not_gate_beh of not_gate is
Begin
Process (a)
begin
if a = '0' then
c <= '1';
else
c <= '0';
end if;
end process;
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end not_gate_beh;
Dataflow Model:
Library IEEE;
Entity not_gate is
Port (
in
STD_LOGIC;
out
STD_LOGIC);
end not_gate;
Architecture not_gate_df of not_gate is
Begin
c <= not a;
end not_gate_df;
Structural Model:
Library IEEE;
Entity not_gate is
Port (
in
STD_LOGIC;
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c
out
STD_LOGIC);
end not_gate;
Architecture not_str of not_gate is

component not_gate
Port (
in
STD_LOGIC;
out
STD_LOGIC);
end component;
begin
U1
not_gate port map(a,c);
end not_str;
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NOT GATE
TRUTH TABLE
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SIMULATION RESULTS:
NOT GATE:-
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NAND GATE:
Behavioral Model:
Library IEEE;
Entity nand_gate is
Port (
b
a
:
in
c
in
STD_LOGIC;
STD_LOGIC;
:
out
STD_LOGIC);
end nand_gate;
Architecture nand_gate_beh of nand_gate is
Begin
process(a, b)
begin
if a = '1' and b = '1' then c <= '0';
else c <= '1';
end if;
end process;
end nand_gate_beh;
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Dataflow Model:
Library IEEE;
Entity nand_gate is
Port (
in
STD_LOGIC;
in
STD_LOGIC;
out
STD_LOGIC);
end nand_gate;
Architecture nand_gate_df of nand_gate is
Begin
c <= a nand b;
end nand_gate_df;
Structural Model:
Library IEEE;
Entity nand_gate is
Port (
in
STD_LOGIC;
in
STD_LOGIC;
out
STD_LOGIC);
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end nand_gate;
Architecture nand_str of nand_gate is

component nand_gate
Port (
in
STD_LOGIC;
in
STD_LOGIC;
out
STD_LOGIC);
end component;
begin
U1
nand_gate port map(a,b,c);
end nand_str;
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NAND GATE
TRUTH TABLE
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SIMULATION RESULTS:
NANDGATE:-
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NOR GATE:
Behavioral Model:
Library IEEE;
Entity nor_gate is
Port (
b
a
:
in
c
in
STD_LOGIC;
STD_LOGIC;
:
out
STD_LOGIC);
end nor_gate;
Architecture nor_gate_beh of nor_gate is
Begin
process(a, b)
begin
if a = '0' and b = '0' then c <= '1';
else c <= '0';
end if;
end process;
end nor_gate_beh;
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Dataflow Model:
Library IEEE;
Entity nor_gate is
Port (
in
STD_LOGIC;
in
STD_LOGIC;
out
STD_LOGIC);
end nor_gate;
Architecture nor_gate_df of nor_gate is
Begin
c <= a nor b;
end nor_gate_df;
Structural Model:
Library IEEE;
Entity nor_gate is
Port (
in
STD_LOGIC;
in
STD_LOGIC;
out
STD_LOGIC);
end nor_gate;
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Architecture nor_str of nor_gate is

component nor_gate
Port (
in
STD_LOGIC;
in
STD_LOGIC;
out
STD_LOGIC);
end component;
begin
U1
nor_gate port map(a,b,c);
end nor_str;

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NOR GATE
TRUTH TABLE
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SIMULATION RESULTS:
NORGATE:
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XOR GATE:
Behavioral Model:
Library IEEE;
Entity xor_gate is
Port (
b
a
:
in
c
in
STD_LOGIC;
STD_LOGIC;
:
out
STD_LOGIC);
end xor_gate;
Architecture xor_gate_beh of xor_gate is
Begin
process(a, b)
begin
if a = b then c <= '0';
else c <= '1';
end if;
end process;
end xor_gate_beh;
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Dataflow MOdel:
Library IEEE;
Entity xor_gate is
Port (
in
STD_LOGIC;
in
STD_LOGIC;
out
STD_LOGIC);
end xor_gate;
Architecture xor_gate_df of xor_gate is
Begin
c <= a xor b;
end xor_gate_df;
Structural Model:
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Library IEEE;
Entity xor_gate is
Port (
in
STD_LOGIC;
in
STD_LOGIC;
out
STD_LOGIC);
end xor_gate;
Architecture xor_str of xor_gate is
component xor_gate
Port (
in
STD_LOGIC;
in
STD_LOGIC;
out
STD_LOGIC);
end component;
begin
U1
xor_gate port map(a,b,c);
end xor_str;
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XOR GATE
TRUTH TABLE
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SIMULATION RESULTS:
Xorgate:
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XNOR GATE:
Behavioral Model:
Library IEEE;
Entity xnor_gate is
Port (
in
STD_LOGIC;
in
STD_LOGIC;
out
STD_LOGIC);
end xnor_gate;
Architecture xnor_gate_beh of xnor_gate is
Begin
process(a, b)
begin
if a = b then c <= '1';
else c <= '0';
end if;
end process;
end xnor_gate_beh;
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Dataflow Model:
Library IEEE;
Entity xnor_gate is
Port (
in
STD_LOGIC;
in
STD_LOGIC;
out
STD_LOGIC);
end xnor_gate;
Architecture xnor_gate_df of xnor_gate is
Begin
c <= a xnor b;
end xnor_gate_df;
Structural Model:
Library IEEE;
Entity xnor_gate is
Port (
in
STD_LOGIC;
in
STD_LOGIC;
out
STD_LOGIC);
end xnor_gate;
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Architecture xnor_str of xnor_gate is

component xnor_gate
Port (
in
STD_LOGIC;
in
STD_LOGIC;
out
STD_LOGIC);
end component;
begin
U1
xnor_gate port map(a,b,c);
end xnor_str;
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XNOR GATE
TRUTH TABLE
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SIMULATION RESULTS:
Xnorgate:
RESULT:
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3 8 DECODER
AIM:
To write VHDL and verilog program for 3 8 Decoder simulate the program and verify the
results.
APPARATUS:
Computer system
Xilinx 7.1 software tool
PROCEDURE:
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for options.
OK.
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board.
VHDL PROGRAM:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity decoder is
Port ( g1,g2,g3 : in std_logic;
A : in std_logic_vector(2 downto 0);
Y : out std_logic_vector(0 to 7));
end decoder;
architecture Behavioral of decoder is
signal Y1:std_logic_vector(0 to 7 );
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begin
with A select Y1<= "01111111" when "000",

"10111111" when "001",
"11011111" when "010",
"11101111" when "100",
"11110111" when "011",
"11111011" when "101",
"11111101" when "110",
"11111110" when "111",
"11111111" when others;
Y<= Y1 when (G1 and not G2 and not G3)='1'
else "11111111";
end Behavioral;
VERILOG PROGRAM:
module decoderverilog(a,b,c,en, z);

input a,b,c,en;
output [7:0] z;
wire abar,bbar,cbar;
not(abar,a);
not(bbar,b);
not(cbar,c);
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and(z[0],en,abar,bbar,cbar);
and(z[1],en,abar,bbar,c);
and(z[2],en,abar,b,cbar);
and(z[3],en,abar,b,c);
and(z[4],en,a,bbar,cbar);
and(z[5],en,a,bbar,c);
and(z[6],en,a,b,cbar);
and(z[7],en,a,b,c);
endmodule

3 x 8 decoder
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G1
O
G2A
Y0
UT
OUT
G2B
Y1
O1
1
1
OUT
OU
Y2
T1
1
T1
OU
Y3
Y4
T1
OU
OU
Y5
T1
T1
OU
Y6
A (0)
Y7
OU
T1
A
(1)
OUT
OU
T1
OUT
A
(2)
1
T1
1
OUT
1
TRUTH TABLE
INPUTS
OUTPUTS
G1
G2A_L
G2B_L
Y7_L
Y6_L
Y5_L
Y4_L
Y3_L
Y2_L
Y1_L
Y0_L
RTL SCHEMATIC:
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SYNTHESIS REPORT:
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=========================================================================
*
Final Report
=========================================================================
Final Results
RTL Top Level Output File Name
Top Level Output File Name
Output Format
: decodervhdl.ngr
: decodervhdl
: NGC
Optimization Goal
: Speed
Keep Hierarchy
: NO
Design Statistics
# IOs
: 14
Macro Statistics :
# Decoders
#
:1
1-of-8 decoder
:1
Cell Usage :
# BELS
: 10
INV
:1
LUT2
:1
LUT3
:8
# FlipFlops/Latches
#
LDE
# IO Buffers
#
IBUF
OBUF
:8
:8
: 14
:6
:8
=========================================================================
Device utilization summary:
--------------------------Selected Device : xa2s50etq144-6
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Number of Slices:
5 out of
768
0%
Number of Slice Flip Flops:
8 out of 1536
0%
Number of 4 input LUTs:
9 out of 1536
0%
Number of bonded IOBs:
14 out of
13%
102
=========================================================================
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
----------------------------------------------------+------------------------+-------+
Clock Signal
| Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
_n0000(_n00001:O)
| NONE(*)(z_7)
|8
-----------------------------------+------------------------+-------+
(*) This 1 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial
logic.
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with
BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock
signals to help prevent skew problems.
Timing Summary:
--------------Speed Grade: -6
Minimum period: No path found
Minimum input arrival time before clock: 4.922ns
Maximum output required time after clock: 6.613ns
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Maximum combinational path delay: No path found
Timing Detail:
-------------All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock '_n00001:O'
Total number of paths / destination ports: 32 / 16
------------------------------------------------------------------------Offset:
Source:
Destination:
4.922ns (Levels of Logic = 2)

e3_inv (PAD)
z_7 (LATCH)
Destination Clock: _n00001:O falling

Data Path: e3_inv to z_7
Gate
Cell:in->out
Net
fanout Delay Delay Logical Name (Net Name)
---------------------------------------- -----------IBUF:I->O
1 0.797 0.920 e3_inv_IBUF (e3_inv_IBUF)
INV:I->O
8 0.468 2.050 z_0__n00011_INV_0 (z_0__n0001)
LDE:GE
0.687
z_0
---------------------------------------Total
4.922ns (1.952ns logic, 2.970ns route)

(39.7% logic, 60.3% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock '_n00001:O'
------------------------------------------------------------------------Offset:
Source:
Destination:

z_7 (LATCH)
z<7> (PAD)
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Source Clock:
_n00001:O falling
Data Path: z_7 to z<7>

Gate
Cell:in->out
Net
---------------------------------------- -----------LDE:G->Q
1 1.091 0.920 z_7 (z_7)
OBUF:I->O
4.602
z_7_OBUF (z<7>)
---------------------------------------Total

(86.1% logic, 13.9% route)
=========================================================================
CPU : 3.48 / 4.31 s | Elapsed : 4.00 / 4.00 s
-->
Total memory usage is 84452 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings :
Number of infos
1 ( 0 filtered)
: 1 ( 0 filtered)
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SIMULATION RESULTS:
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2x4 DE MULTIPLEXER
AIM:
To write VHDL & verilog program for demultiplexer , simulate the program and verify the
results
APPARATUS:
Computer system
PROCEDURE:
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for options.
OK.

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board.
VHDL PROGRAM:
library IEEE;
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entity demultiplexer is
Port ( s1 : in std_logic;
sel : in std_logic_vector ( 1 downto 0);
q : out std_logic_vector ( 3 downto 0));
end demultiplexer;
architecture Behavioral of demultiplexer is
signal q1 : std_logic_vector ( 3 downto 0);
begin
with sel select q1<= "1110" when "00",
"1101" when "01",
"1011" when "10",
"0111" when "11",
"1111" when others;
q<= q1 when s1= '0'
else "1111";
end Behavioral;
verilog program :
module demuxverilog(d,en, s, y);
input d,en;
input [2:0] s;
output [7:0] y;
wire s2bar,s1bar,s0bar;
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not(s2bar,s[2]);
not(s1bar,s[1]);
not(s0bar,s[0]);
and(y[0],d,en,s2bar,s1bar,s0bar);
and(y[1],d,en,s2bar,s1bar,s[0]);
and(y[2],d,en,s2bar,s[1],s0bar);
and(y[3],d,en,s2bar,s[1],s[0]);
and(y[4],d,en,s[2],s1bar,s0bar);
and(y[5],d,en,s[2],s1bar,s[0]);
and(y[6],d,en,s[2],s[1],s0bar);
and(y[7],d,en,s[2],s[1],s[0]);
endmodule

2 X 4 DEMULTIPLEXER
TRUTH TABLE
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EN
A
S0
OU
S1
T1
OU
T1
Y0
OU
Y1
T1
OU
Y2
T1
OU
Y3
T1
OU
T1
INPUTS
S0
S1
DATA
Y0
Y1
Y2
Y3
RTL SCHEMATIC:
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OUTPUT
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SYNTHESIS REPORT:
=========================================================================
*
Final Report
=========================================================================
Final Results
Output Format
: vhdldemux.ngr
: vhdldemux
: NGC
Optimization Goal
: Speed
Keep Hierarchy
: NO
Design Statistics
# IOs
:8
Cell Usage :
# BELS
:4
:4
LUT4
# IO Buffers
#
IBUF
OBUF
:8
:4
:4
=========================================================================
Number of Slices:
2 out of
768
0%
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4 out of 1536
0%
8 out of
7%
102
=========================================================================
TIMING REPORT
Clock Information:
-----------------No clock signals found in this design
Timing Summary:
--------------Speed Grade: -6
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 8.307ns
Timing Detail:
=========================================================================
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_____________________________________________________________________________________
Timing constraint: Default path analysis
------------------------------------------------------------------------Delay:
Source:
d (PAD)
Destination:
y<3> (PAD)
Data Path: d to y<3>

Gate
Cell:in->out
Net
---------------------------------------- -----------IBUF:I->O
4 0.797 1.520 d_IBUF (d_IBUF)
LUT4:I0->O
1 0.468 0.920 _n00101 (y_2_OBUF)
OBUF:I->O
4.602
y_2_OBUF (y<2>)
---------------------------------------Total

(70.6% logic, 29.4% route)
=========================================================================
CPU : 3.95 / 4.83 s | Elapsed : 4.00 / 4.00 s
-->
Number of infos
0 ( 0 filtered)
: 0 ( 0 filtered)
62

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________
SIMULATION RESULTS
63

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________
8_3 ENCODER
AIM:
To write VHDL & verilog program for encoder ,simulate the program and verify the results.
APPARATUS:
Computer system
PROCEDURE:
64

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________


65

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Ex. No:
Date:
_____________________________________________________________________________________
for options.
OK.
66

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Ex. No:
Date:
_____________________________________________________________________________________
board.
VHDL CODE :
library IEEE;
entity encoder is
Port ( d : in std_logic_vector(7 downto 0);
b : out std_logic_vector(2 downto 0));
end encoder;
architecture Behavioral of encoder is
begin
process(d)
begin
67

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________
case d is
when "00000001"=>b<="000";
when "00000010"=>b<="001";
when "00000100"=>b<="010";
when "00001000"=>b<="011";
when "00010000"=>b<="100";
when "00100000"=>b<="101";
when "01000000"=>b<="110";
when "10000000"=>b<="111";
when others =>null;
end case;
end process;
end Behavioral;
VERILOG CODE:
module encoder(d, en, y);
input [7:0] d;
input en;
output [2:0] y;
wire a,b,c;
or(a,d[1],d[3],d[5],d[7]);
or(b,d[2],d[3],d[4],d[7]);
or(c,d[4],d[5],d[6],d[7]);
and(y[0],a,en);
and(y[1],b,en);
68

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Ex. No:
Date:
_____________________________________________________________________________________
and(y[2],c,en);
endmodule
RTL SCHEMATIC:
69

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Ex. No:
Date:
_____________________________________________________________________________________
SYNTHESIS REPORT:
=========================================================================
*
Final Report
=========================================================================
Final Results
Output Format
: encoder.ngr
: encoder
: NGC
70

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________
Optimization Goal
: Speed
Keep Hierarchy
: NO
Design Statistics
# IOs
: 11
Cell Usage :
# BELS
: 11
LUT2
:2
LUT3
:1
LUT4
:8
# FlipFlops/Latches
#
LD
:3
:3
# IO Buffers
#
IBUF
OBUF
: 11
:8
:3
=========================================================================
Number of Slices:
6 out of
768
0%
3 out of 1536
0%
11 out of 1536
0%
11 out of
102
71
10%

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________
=========================================================================
TIMING REPORT
Clock Information:
----------------------------------------------------+------------------------+-------+
Clock Signal
-----------------------------------+------------------------+-------+
N167(_n0040148:O)
| NONE(*)(b_2)
|3
-----------------------------------+------------------------+-------+
(*) This 1 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial
logic.
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with
BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock
signals to help prevent skew problems.
Timing Summary:
--------------Speed Grade: -6
72

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Ex. No:
Date:
_____________________________________________________________________________________
Timing Detail:
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock '_n0040148:O'
------------------------------------------------------------------------Offset:
Source:
Destination:
d<2> (PAD)
b_0 (LATCH)
Destination Clock: _n0040148:O falling

Data Path: d<2> to b_0
Gate
Cell:in->out
Net
---------------------------------------- -----------IBUF:I->O
3 0.797 1.320 d_2_IBUF (d_2_IBUF)
LUT2:I0->O
2 0.468 1.150 Ker121 (N12)
LUT4:I1->O
1 0.468 0.000 _n0000<0> (_n0000<0>)
LD:D
0.724
b_0
---------------------------------------Total

(49.9% logic, 50.1% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock '_n0040148:O'
73

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Ex. No:
Date:
_____________________________________________________________________________________
------------------------------------------------------------------------Offset:
Source:

b_2 (LATCH)
Destination:
Source Clock:
b<2> (PAD)
_n0040148:O falling
Data Path: b_2 to b<2>

Gate
Cell:in->out
Net
---------------------------------------- -----------LD:G->Q
1 1.091 0.920 b_2 (b_2)
OBUF:I->O
4.602
b_2_OBUF (b<2>)
---------------------------------------Total

(86.1% logic, 13.9% route)
=========================================================================
CPU : 2.70 / 2.97 s | Elapsed : 2.00 / 3.00 s
-->
Number of infos
1 ( 0 filtered)
: 1 ( 0 filtered)
74

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________
SIMULATION RESULTS
75

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________
MOD-53 COUNTER
76

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________
AIM:
To write VHDL & verilog program for mod 53 counter ,simulate the program and verify the
results.
APPARATUS:
Computer system
PROCEDURE:
77

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________


for options.
78

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Ex. No:
Date:
_____________________________________________________________________________________
OK.
board.
79

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Ex. No:
Date:
_____________________________________________________________________________________
VHDL PROGRAM :
Library ieee;
Use iee.std_logic_1164.all;
Use iee.numeric_std_all;
Entity modul is
Generic (n bits:positive:=4;gpto positive:=12);
Port(clk,reset:in std_logic;
Q:out std_logic_vector(0 to nbits-1);
Qn:out std_logic_vector(0to n bits-1));
End module;
Architecture behavior of modul is
Begin
Process(clk)
Variable enter_value :unsigned(nbits-1 downto 0);
Begin
If(clk and clkevent==1)then
If(reset=1)then
80

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________
Enter_value:=(other=>0);
Else
Enter_value:=(enter_value+1)modupto;
End if;
End if;
Q<=std_logic_vector(enter_value);
Qn<=std_logic_vector(enter_value);
End process;
End behaviour;
RTL SCHEMATIC
81

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Ex. No:
Date:
_____________________________________________________________________________________
SYNTHESIS REPORT:
=========================================================================
*
Final Report
=========================================================================
Final Results
Output Format
: module.ngr
: module
: NGC
Optimization Goal
: Speed
Keep Hierarchy
: NO
Design Statistics
# IOs
: 20
Macro Statistics :
# Counters
#
7-bit up counter
:1
:1
Cell Usage :
82

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________
# BELS
: 29
GND
:1
INV
LUT1
:1
LUT2
:1
LUT3
:1
LUT3_L
LUT4
MUXCY
VCC
XORCY
:1
:7
:2
:7
:1
:7
# FlipFlops/Latches
#
:7
FDRSE
:7
# Clock Buffers
#
:1
BUFGP
:1
# IO Buffers
: 19
IBUF
: 11
OBUF
:8
=========================================================================
--------------------------Selected Device : 2s50eft256-6
Number of Slices:
6 out of
768
0%
7 out of 1536
0%
12 out of 1536
0%
20 out of
Number of GCLKs:
1 out of
182
4
10%
25%
=========================================================================
TIMING REPORT
83

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Ex. No:
Date:
_____________________________________________________________________________________
Clock Information:
----------------------------------------------------+------------------------+-------+
Clock Signal
-----------------------------------+------------------------+-------+
clk
| BUFGP
|7
-----------------------------------+------------------------+-------+
Timing Summary:
--------------Speed Grade: -6
Minimum period: 4.957ns (Maximum Frequency: 201.735MHz)
Timing Detail:
=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
Clock period: 4.957ns (frequency: 201.735MHz)
------------------------------------------------------------------------Delay:
Source:
Destination:
Source Clock:

iq_0 (FF)
iq_6 (FF)
clk rising
84

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Ex. No:
Date:
_____________________________________________________________________________________
Destination Clock: clk rising
Data Path: iq_0 to iq_6
Gate
Cell:in->out
Net
---------------------------------------- -----------FDRSE:C->Q
3 0.992 1.320 iq_0 (iq_0)
LUT3_L:I2->LO
1 0.468 0.000 iq_inst_lut3_01 (iq_inst_lut3_0)
MUXCY:S->O
1 0.515 0.000 iq_inst_cy_1 (iq_inst_cy_1)
MUXCY:CI->O
MUXCY:CI->O
MUXCY:CI->O
MUXCY:CI->O
MUXCY:CI->O
XORCY:CI->O
1 0.648 0.000 iq_inst_sum_6 (iq_inst_sum_6)
FDRSE:D
0.724
iq_6
---------------------------------------Total

(73.4% logic, 26.6% route)
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
------------------------------------------------------------------------Offset:
Source:
Destination:

ld (PAD)
iq_6 (FF)

Data Path: ld to iq_6
Gate
Cell:in->out
Net

85

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Ex. No:
Date:
_____________________________________________________________________________________
---------------------------------------- -----------IBUF:I->O
9 0.797 2.150 ld_IBUF (ld_IBUF)
LUT3:I0->O
7 0.468 1.950 _n00051 (_n0005)
FDRSE:CE
0.687
iq_0
---------------------------------------Total

(32.3% logic, 67.7% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
------------------------------------------------------------------------Offset:
Source:
iq_2 (FF)
Destination:
Source Clock:
rc0 (PAD)
clk rising
Data Path: iq_2 to rc0

Gate
Cell:in->out
Net
---------------------------------------- -----------FDRSE:C->Q
3 0.992 1.320 iq_2 (iq_2)
LUT4:I0->O
1 0.468 0.920 _n00017 (CHOICE23)
LUT2:I0->O
1 0.468 0.920 _n000119 (rc0_OBUF)
OBUF:I->O
4.602
rc0_OBUF (rc0)
---------------------------------------Total

(67.4% logic, 32.6% route)
=========================================================================
86

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Ex. No:
Date:
_____________________________________________________________________________________
------------------------------------------------------------------------Delay:
Source:
ent (PAD)
Destination:
rc0 (PAD)
Data Path: ent to rc0

Gate
Cell:in->out
Net
---------------------------------------- -----------IBUF:I->O
2 0.797 1.150 ent_IBUF (ent_IBUF)
LUT4:I2->O
1 0.468 0.920 _n00017 (CHOICE23)
LUT2:I0->O
1 0.468 0.920 _n000119 (rc0_OBUF)
OBUF:I->O
4.602
rc0_OBUF (rc0)
---------------------------------------Total

(67.9% logic, 32.1% route)
=========================================================================
CPU : 4.34 / 6.34 s | Elapsed : 5.00 / 6.00 s
-->
Number of infos
0 ( 0 filtered)
: 0 ( 0 filtered)
87

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________
SIMULATION RESULTS
88

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________
8x1 MULTIPLEXER
89

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________
AIM:
To write VHDL & verilog program for Multiplexer, simulate the program and verify the results
APPARATUS:
Computer system
PROCEDURE:
90

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________


for options.
91

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________
OK.
board.
92

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Ex. No:
Date:
_____________________________________________________________________________________
VHDL CODE
library IEEE;
entity multiplexer is
Port ( s : in std_logic_vector(2 downto 0);
d : in std_logic_vector(7 downto 0);
y,y1 : out std_logic);
end multiplexer;
architecture Behavioral of multiplexer is
begin
process ( s,d)
begin
case s is
when "000" => y<= d(0) ;y1 <= not d(0);

when "001" => y<= d(1) ;y1 <= not d(1);
when "010" => y<= d(2) ;y1 <= not d(2);
when "011" => y<= d(3) ;y1 <= not d(3);
93

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Ex. No:
Date:
_____________________________________________________________________________________
when "100" => y<= d(4) ;y1 <= not d(4);
when "101" => y<= d(5) ;y1 <= not d(5);
when "110" => y<= d(6) ;y1 <= not d(6);
when "111" => y<= d(7) ;y1 <= not d(7);
when others => y<='1';
end case;
end process;
end Behavioral;
VERILOG CODE:
module amuxverilog(a, s, y);
input [7:0] a;
input [2:0] s;
output y;
wire k,l,m,n,o,p,q,r,g,h,i;
not(g,s[2]);
not(g,s[1]);
not(i,s[0]);
and(k,a[0],g,h,i);
and(l,a[1],g,h,s[0]);
and(m,a[2],g,s[1],i);
and(n,a[3],g,s[1],s[0]);
and(o,a[4],s[2],h,i);
and(p,a[5],s[2],h,s[0]);
and(q,a[6],s[2],s[1],i);
and(r,a[7],s[2],s[1],s[0]);
or(y,k,l,m,n,o,p,q,r);
endmodule
94

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Ex. No:
Date:
_____________________________________________________________________________________

8X1 MULTIPLEXER
EN
A0
A1
OU
OU
A2
T1
T1
OU
A3
A4
OU
T1
OU
T1
A5
T1
OU
A6
T1
A7
OU
OU
T1
S0
T1
OU
S1
T1
OU
S2
T1
OU
T1
95

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________
TRUTH TABLE
INPUTS
OUTPUT
EN
S0
S1
S2
DATA
A0
A0
A1
A1
A2
A2
A3
A3
A4
A4
A5
A5
A6
A6
A7
A7
RTL SCHEMATIC
96

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Ex. No:
Date:
_____________________________________________________________________________________
SYNTHESIS REPORT:
=========================================================================
*
Final Report
=========================================================================
Final Results
Output Format
: mux.ngr
: mux
: NGC
Optimization Goal
: Speed
Keep Hierarchy
: NO
Design Statistics
# IOs
: 13
97

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________
Cell Usage :
# BELS
:7
LUT2
:1
LUT4
:5
MUXF5
:1
# IO Buffers
: 13
IBUF
: 12
OBUF
:1
=========================================================================
Number of Slices:
3 out of
768
0%
6 out of 1536
0%
13 out of
12%
102
=========================================================================
TIMING REPORT
Clock Information:
-----------------98

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________
No clock signals found in this design
Timing Summary:
--------------Speed Grade: -6
Timing Detail:
=========================================================================
------------------------------------------------------------------------Delay:
Source:
Destination:
s<2> (PAD)
y (PAD)
Data Path: s<2> to y

Gate
Cell:in->out
Net
---------------------------------------- -----------IBUF:I->O
LUT4:I0->O
4 0.797 1.520 s_2_IBUF (s_2_IBUF)

1 0.468 0.000 y97_F (N87)
99

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________
MUXF5:I0->O
1 0.422 0.920 y97 (CHOICE71)
LUT4:I2->O
1 0.468 0.920 y111 (CHOICE72)
LUT2:I0->O
1 0.468 0.920 y124 (y_OBUF)
OBUF:I->O
4.602
y_OBUF (y)
---------------------------------------Total

(62.8% logic, 37.2% route)
=========================================================================
CPU : 2.44 / 2.73 s | Elapsed : 3.00 / 3.00 s
Number of infos
0 ( 0 filtered)
: 1 ( 0 filtered)
SIMULATION RESULTS
100

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________
RIPPLE CARRY ADDER:

101

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________
AIM:
To write VHDL & verilog program for ripple carry adder , simulate the program and verify the
results
APPARATUS:
Computer system
PROCEDURE:

102

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________


for options.
103

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________
OK.
board.
104

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________
VHDL CODE:
entity rca is
port(a:in std_logic _vector(3 downto 0);
b:in std_logic_vector(3 downto 0);
cin:in std_logic;
sum:out std_logic _vector(3 downto 0);
cout:out std_logic);
end rca;
architecture rca of rca is
component fulladder is
port( a,b,c:in std_logic;
sum,carry:out std_logic);
end component;
sgnal c:std_logic_vector(2 downto 0);
begin
f1:fulladder portmap(a(0),b(0),cin,sum1(0),c(0));
f2:fulladder portmap(a(1),b(1),c(0),sum1(1),c(1));
f3:fulladder portmap(a(2),b(2),c(1),sum1(2),c(2));
f4:fulladder portmap(a(3),b(3),c(2),sum1(3),cout);
105

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Ex. No:
Date:
_____________________________________________________________________________________
end rca;
---------------sub program for ripple carry adder--------------Fulladder:

Entity fulladder is
Port(a,b,cin:in std_logic;
Sum,carry:out std_logic);
End fulladder;
Architecture behav of fulladder is
signal p,q,r,s,:std_logic;
begin
p<=a xorb;
sum<=p xor cin;
q<=a and b;
r<=b and c;
s<= and cin;
carry<=q or r or s;
end behav;
106

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________
VERILOG CODE:
Module rca(a,b,cin,sum,carry);
Input[3:0]a;
Input[3:0]b;
Input cin;
Ouput[3:0]sum;
Output carry;
Wire x,y,z;
F1(cin,a[0],b[0],sum[0],x);
F2(x,a[1],b[1],sum[1],y);
F3(y,a[2],b[2],sum[2],z);
F4(z,a[3],b[3],sum[3],carry);
End module
-------------sub program for ripple carry adder-------------Module fulladder(a,b,cin,sum,carry);
Input a,b,cin;
Output sum,carry;
107

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________
Reg p,q,t2,t3;
Always @(a or b or c)
Begin
Sum=a^b^c;
Ps1=a^b;
Qt1=a&b;
Rt2=b&c;
St3=a&c;
Carry=(a&b/(b&c)/(a&c));
End
End module
RTL SCHEMATIC
108

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________
SYNTHESIS REPORT:
=========================================================================
*
Final Report
=========================================================================
Final Results
Output Format
Optimization Goal
Keep Hierarchy
: rc_adder.ngr
: rc_adder
: NGC
: Speed
: NO
Design Statistics
109

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________
# IOs
: 13
Macro Statistics :
# Xors
#
:3
1-bit xor3
:3
Cell Usage :
# BELS
:7
LUT2
:1
LUT3
:4
LUT4
:2
# IO Buffers
#
IBUF
OBUF
: 13
:8
:5
=========================================================================
Number of Slices:
4 out of
768
0%
7 out of 1536
0%
13 out of
12%
102
=========================================================================
TIMING REPORT
110

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________
Clock Information:
-----------------No clock signals found in this design
Timing Summary:
--------------Speed Grade: -6
Timing Detail:
=========================================================================
------------------------------------------------------------------------Delay:
Source:
Destination:

num1<0> (PAD)
carry (PAD)
111

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________
Data Path: num1<0> to carry
Gate
Cell:in->out
Net
---------------------------------------- -----------IBUF:I->O
3 0.797 1.320 num1_0_IBUF (num1_0_IBUF)
LUT4:I1->O
2 0.468 1.150 Ker41 (N4)
LUT3:I2->O
2 0.468 1.150 c21 (c2)
LUT3:I0->O
1 0.468 0.920 Mxor_sum<3>_Xo<1>1 (sum_3_OBUF)
OBUF:I->O
4.602
sum_3_OBUF (sum<3>)
---------------------------------------Total

(60.0% logic, 40.0% route)
=========================================================================
CPU : 2.80 / 3.19 s | Elapsed : 3.00 / 4.00 s
Number of infos
0 ( 0 filtered)
: 0 ( 0 filtered)
SIMULATION RESULTS
112

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________
UNIVERSAL COUNTER
113

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________
AIM:
To write VHDL & verilog program for universal counter, simulate the program and verify the
results
APPARATUS:
Computer system
PROCEDURE:
114

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________


for options.
115

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________
OK.
board.
116

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________
Vhdl code:
entity counter is
generic(n:integer:=8);
Port ( clk,reset,load,ud : in std_logic; din: in std_logic_vector(n-1 downto 0); q: out
std_logic_vector(n-1 downto 0));
end counter;
architecture Behavioral of counter is
signal count :std_logic_vector(n-1 downto 0);
begin
process(clk,reset,load,ud)
begin
if(clk='1' and clk'event )then
if(reset='1')then
count<="00000000";
else if(load='1')then
count<=din;
else
if(ud='1')then
117

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________
count<=count+1;
else
count<=count-1;
end if;
end if;
end if;
end if;
q<=count;
end process;
end Behavioral;
VERILOG CODE:
module count(clk, reset, up_down, q);
input clk;
input reset;
input up_down;
output [7:0]q;
reg[7:0]count;
always@(posedge clk or posedge reset)
begin
if(reset==1)
count=0;
else
if(up_down==1)
count=count-1;
else
count=count+1;
end
assign q=count;
118

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________
endmodule
RTL SCHEMATIC
119

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Ex. No:
Date:
_____________________________________________________________________________________
SYNTHESIS REPORT:
=========================================================================
*
Final Report
=========================================================================
Final Results
Output Format
: counter.ngr
: counter
: NGC
Optimization Goal
: Speed
Keep Hierarchy
: NO
Design Statistics
# IOs
: 20
Macro Statistics :
# Counters
:1
120

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Ex. No:
Date:
_____________________________________________________________________________________
#
8-bit updown counter
:1
Cell Usage :
# BELS
: 35
GND
:1
INV
LUT2
LUT4_L
MULT_AND
MUXCY
VCC
XORCY
:1
:1
:8
:7
:8
:1
:8
# FlipFlops/Latches
#
:8
FDRSE
:8
# Clock Buffers
#
:1
BUFGP
:1
# IO Buffers
: 19
IBUF
: 11
OBUF
:8
=========================================================================
Number of Slices:
5 out of
768
0%
8 out of 1536
0%
9 out of 1536
0%
121

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Ex. No:
Date:
_____________________________________________________________________________________
20 out of
Number of GCLKs:
1 out of
102
4
19%
25%
=========================================================================
TIMING REPORT
Clock Information:
----------------------------------------------------+------------------------+-------+
Clock Signal
-----------------------------------+------------------------+-------+
clk
| BUFGP
|8
-----------------------------------+------------------------+-------+
Timing Summary:
--------------Speed Grade: -6
Timing Detail:
122

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Ex. No:
Date:
_____________________________________________________________________________________
=========================================================================
------------------------------------------------------------------------Delay:
Source:

count_0 (FF)
Destination:
count_7 (FF)
Source Clock:
clk rising

Data Path: count_0 to count_7
Gate
Cell:in->out
Net
---------------------------------------- -----------FDRSE:C->Q
2 0.992 1.150 count_0 (count_0)
LUT4_L:I1->LO
1 0.468 0.000 count_inst_lut4_01 (count_inst_lut4_0)
MUXCY:S->O
1 0.515 0.000 count_inst_cy_1 (count_inst_cy_1)
MUXCY:CI->O
MUXCY:CI->O
MUXCY:CI->O
MUXCY:CI->O
MUXCY:CI->O
MUXCY:CI->O
XORCY:CI->O
1 0.648 0.000 count_inst_sum_7 (count_inst_sum_7)
FDRSE:D
0.724
count_7
123

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Ex. No:
Date:
_____________________________________________________________________________________
---------------------------------------Total

(76.3% logic, 23.7% route)
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
------------------------------------------------------------------------Offset:
Source:
Destination:

load (PAD)
count_7 (FF)

Data Path: load to count_7
Gate
Cell:in->out
Net
---------------------------------------- -----------IBUF:I->O
2 0.797 1.150 load_IBUF (load_IBUF)
INV:I->O
8 0.468 2.050 count_inst_lut1_01_INV_0 (count_inst_lut1_0)
LUT4_L:I0->LO
1 0.468 0.000 count_inst_lut4_01 (count_inst_lut4_0)
MUXCY:S->O
MUXCY:CI->O
MUXCY:CI->O
MUXCY:CI->O
MUXCY:CI->O
MUXCY:CI->O
MUXCY:CI->O
XORCY:CI->O
1 0.648 0.000 count_inst_sum_7 (count_inst_sum_7)
FDRSE:D
0.724
count_7
124

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Ex. No:
Date:
_____________________________________________________________________________________
---------------------------------------Total

(55.4% logic, 44.6% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
------------------------------------------------------------------------Offset:
Source:

count_7 (FF)
Destination:
Source Clock:
q<7> (PAD)
clk rising
Data Path: count_7 to q<7>

Gate
Cell:in->out
Net
---------------------------------------- -----------FDRSE:C->Q
OBUF:I->O
2 0.992 1.150 count_7 (count_7)

4.602
q_7_OBUF (q<7>)
---------------------------------------Total

(82.9% logic, 17.1% route)
=========================================================================
CPU : 3.39 / 3.77 s | Elapsed : 4.00 / 4.00 s
-->
125

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Ex. No:
Date:
_____________________________________________________________________________________

Number of infos
1 ( 0 filtered)
: 0 ( 0 filtered)
SIMULATION RESULTS
126

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Ex. No:
Date:
_____________________________________________________________________________________
UNIVERSAL SHIFT REGISTER
127

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Ex. No:
Date:
_____________________________________________________________________________________
AIM:
To write VHDL & verilog program for universal shift register , simulate the program and verify
the results
APPARATUS:
Computer system
PROCEDURE:
128

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Ex. No:
Date:
_____________________________________________________________________________________


for options.
129

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Ex. No:
Date:
_____________________________________________________________________________________
OK.
board.
130

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Ex. No:
Date:
_____________________________________________________________________________________
VHDL CODE:
entity shiftreg is
Port ( clk : in std_logic;
dsr : in std_logic;
drl : in std_logic;
clk_l : in std_logic; s : in std_logic_vector(1 downto 0);

q : inout std_logic_vector(3 downto 0));
end shiftreg;
architecture Behavioral of shiftreg is
begin
process(clk,s,clr_l)
begin
if clr_l='0'then
q<=(others=>'0');
elsif clk_l='1'then
if(clk'event and clk='1')then
case s is
when"00"=>q<= q;
when"01"=>q<=q(2 downto 0)& dsr;
when"10"=>q<= drl & q(3 downto 1);
when"11"=>q<=d(3)& d(2)&d(1)&d(0);
131
clr_l : in std_logic;
d : in std_logic_vector(3 downto 0);

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________
when others=>null;
end case;
end if;
end if;
end process;
end Behavioral;
VERILOG CODE:
module shift (C, SI, SO);
input C,SI;
output SO;
reg [7:0] tmp;
always @(posedge C)
begin
tmp <= tmp << 1;
tmp[0] <= SI;
end
assign SO = tmp[7];
endmodule
port(
C, SI, CLR : in std_logic;
SO : out std_logic);
end shift;
132

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Ex. No:
Date:
_____________________________________________________________________________________
RTL SCHEMATIC
133

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Ex. No:
Date:
_____________________________________________________________________________________
SYNTHESIS REPORT:
=========================================================================
*
Final Report
=========================================================================
Final Results
Output Format
: shift.ngr
: shift
: NGC
Optimization Goal
: Speed
Keep Hierarchy
: NO
Design Statistics
# IOs
:3
Macro Statistics :
134

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________
# Shift Registers
:1
:1
8-bit shift register
Cell Usage :
# BELS
:2
GND
:1
VCC
:1
# FlipFlops/Latches
#
:1
FDE
:1
# Shifters
:1
SRL16E
:1
# Clock Buffers
#
:1
BUFGP
:1
# IO Buffers
:2
IBUF
OBUF
:1
:1
=========================================================================
--------------------------Selected Device : 2s50eft256-6
Number of Slices:
1 out of
768
0%
1 out of 1536
0%
1 out of 1536
0%
3 out of
1%
Number of GCLKs:
1 out of
182
4
25%
135

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________
=========================================================================
TIMING REPORT
Clock Information:
----------------------------------------------------+------------------------+-------+
Clock Signal
-----------------------------------+------------------------+-------+
C
| BUFGP
|2
-----------------------------------+------------------------+-------+
Timing Summary:
--------------Speed Grade: -6
Timing Detail:
136

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________
=========================================================================
Timing constraint: Default period analysis for Clock 'C'
------------------------------------------------------------------------Delay:
Source:
Destination:
Source Clock:

Mshreg_tmp<7>_srl_0 (FF)
Mshreg_tmp<7>_0 (FF)
C rising
Destination Clock: C rising

Data Path: Mshreg_tmp<7>_srl_0 to Mshreg_tmp<7>_0
Gate
Cell:in->out
Net
---------------------------------------- -----------SRL16E:CLK->Q
FDE:D
1 3.068 0.920 Mshreg_tmp<7>_srl_0 (Mshreg_tmp<7>__net0)

0.724
Mshreg_tmp<7>_0
---------------------------------------Total

(80.5% logic, 19.5% route)
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'C'
------------------------------------------------------------------------Offset:
Source:
Destination:

SI (PAD)
Mshreg_tmp<7>_srl_0 (FF)
Destination Clock: C rising

137

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________
Data Path: SI to Mshreg_tmp<7>_srl_0

Gate
Cell:in->out
Net
---------------------------------------- -----------IBUF:I->O
1 0.797 0.920 SI_IBUF (SI_IBUF)
SRL16E:D
0.583
Mshreg_tmp<7>_srl_0
---------------------------------------Total

(60.0% logic, 40.0% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'C'
------------------------------------------------------------------------Offset:
Source:
Destination:
Source Clock:

Mshreg_tmp<7>_0 (FF)
SO (PAD)
C rising
Data Path: Mshreg_tmp<7>_0 to SO

Gate
Cell:in->out
Net
---------------------------------------- -----------FDE:C->Q
OBUF:I->O
1 0.992 0.920 Mshreg_tmp<7>_0 (Mshreg_tmp<7>_0)

4.602
SO_OBUF (SO)
---------------------------------------Total

(85.9% logic, 14.1% route)
138

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________
=========================================================================
CPU : 3.38 / 5.47 s | Elapsed : 3.00 / 5.00 s
-->
Number of infos
0 ( 0 filtered)
: 0 ( 0 filtered)
SIMULATION RESULTS
139

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Ex. No:
Date:
_____________________________________________________________________________________
COMPARATOR
140

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Ex. No:
Date:
_____________________________________________________________________________________
AIM:
synthesis for digital Circuit.
d. Implement the place & route technique for major FPGA vendori.e. XILINX
APPARATUS:
1. System
2. Xilinx Software
3. Sparton-3 FPGA devices
PROCEDURE:

141

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________


142

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________
for options.
OK.
143

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________
board.
PROGRAM:
library IEEE;
entity comparator is
Generic(N:integer :=3);
port(a,b:in std_logic_vector(n downto 0); alb,aeb,agb: out std_logic);
end comparator;
architecture Behavioral of comparator is
begin
process(a,b)
144

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________
begin
if(a<b) then alb<='1';
else alb<='0';
end if;
if(a>b)
then agb<='1';else agb<='0';
end if;
if(a=b)then aeb<='1';else aeb<='0';
end if;
end process;
end Behavioral;
145

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________
RTL Schematic:
Fig:Block Diagram Representation For Comparator
146

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________
Fig: RTL Schematic Report for Comparator
147

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Ex. No:
Date:
_____________________________________________________________________________________
Fig:Technical Schematic Report For Comparator
148

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________
==================================================
==============================
*
Synthesis Report for Comparator
==================================================
===============================
Final Results
: comparator.ngr
: comparator
Output Format
: NGC
Optimization Goal
: Speed
Keep Hierarchy
: NO
Design Statistics
# IOs
: 11
Cell Usage :
# BELS
#
LUT2
LUT4
MUXF5
: 11
:1
:8
:2
# IO Buffers
: 11
149

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________
#
IBUF
:8
OBUF
==================================================
=============
Timing Report for Comparator:
==================================================
============
---------------------------------------------------------------------------------------------------Delay
Source
Destination :

:
a<1> (PAD)
agb (PAD)
Data Path: a<1> to agb

Gate
Cell: in->out
Net
fan-out Delay Delay Logical Name (Net Name)
---------------------------------------- --------------------------------------------------------IBUF:I->O
3 0.715 1.066 a_1_IBUF (a_1_IBUF)
LUT4:I0->O
2 0.479 1.040 agb139 (agb1_map106)
LUT4:I0->O
1 0.479 0.000 agb1842 (N198)

150

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________
MUXF5:I0->O
OBUF:I->O
1 0.314 0.681 agb184_f5 (agb_OBUF)

4.909
agb_OBUF (agb)
-------------------------------------------------------------------------------------------------Total

(71.2% logic, 28.8% route)
PRECAUTIONS:
Note down the results without parallax error.
Avoid the loose connections while designs the circuit.
Observe the waveforms carefully.
151

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________
Fig: Simulation Report For Comparator
152

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Ex. No:
Date:
_____________________________________________________________________________________
DFLIPFLOP
AIM:
synthesis for digital circuit.
APPARATUS:
1. System
2. Xilinx Software
PROCEDURE:
153

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________

154

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________
for options.
OK.
155

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________
board.
PROGRAM:
library IEEE;
entity dflipflop is
Port ( clk : in STD_LOGIC;
d : in STD_LOGIC;
q : out STD_LOGIC);
156

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________
end dflipflop;
architecture Behavioral of dflipflopf is
begin
process(clk)
begin
if(clk'event and clk='1')then
q<=d;
end if;
end process;
end Behavioral;
RTL SCHEMATIC:
157

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________
Fig: technology schematic
SYNTHESIS:
==================================================
==============*
Final Report
==================================================
=============
Final Results
Output Format
: dflipflop.ngr
: dflip-flop
: NGC
158

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________
Optimization Goal
: Speed
Keep Hierarchy
: NO
Design Statistics
# IOs
:3
Macro Statistics:
# Registers
:1
:1
1-bit register
Cell Usage:
# Flip-flops/Latches
#
FD
:1
:1
# Clock Buffers
#
:1
BUFGP
:1
# IO Buffers
:2
IBUF
OBUF
:1
:1
==================================================
==============Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
---------------------------------------------------------------------------------------------------------
159

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________
Offset:
Source:

d (PAD)
Destination:
q (FF)

Data Path: d to q
Gate
Cell:in->out
Net
---------------------------------------------------------------------------------------- ------IBUF:I->O
FD:D
1 0.797 0.920 d_IBUF (d_IBUF)

0.724
-------------------------------------------------------------------------------------------------Total

(62.3% logic, 37.7% route)
PRECAUTIONS:
160

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________
SIMULATION:
161

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________
JK FLIPFLOP
162

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________
AIM:
Synthesis for digital circuit.
APPARATUS:
1. System
2. Xilinx Software
PROCEDURE:

163

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________


164

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________
for options.
OK.

165

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________
board.
PROGRAM:
library IEEE;
entity jkff is
Port ( clk : in bit;
j : in bit;
k : in bit;
reset : in bit;
q : buffer bit);
end jkff;
166

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________
architecture Behavioral of jkff is
begin
process(clk,reset)
begin
if(reset='1') then
q <='0';
elsif(clk'event and clk='1') then
if(j='0' and k='0') then
q<=q;
elsif(j='0' and k='1') then
q<='0';
q<='1';
q<= not q;
end if;
end if;
end process;
end Behavioral;
167

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________
RTL SCHEMATIC:
168

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________
169

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________
SYNTHESIS:
==================================================
=============
*
Final Report
==================================================
=============
Final Results
Output Format
: jkff.ngr
: jkff
: NGC
170

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________
Optimization Goal
: Speed
Keep Hierarchy
: NO
Design Statistics
# IOs
:5
Macro Statistics :
# Registers
:1
:1
1-bit register
# Multiplexers
#
:1
1-bit 4-to-1 multiplexer
:1
Cell Usage :
# BELS
:2
LUT2
:1
LUT3_L
:1
# FlipFlops/Latches
#
FDCE
:1
:1
# Clock Buffers
#
:1
BUFGP
:1
# IO Buffers
:4
IBUF
:3
171

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________
#
OBUF
:1
==================================================
===========
----------------------------------------------------------------------------------------------------Delay:
Source:

q (FF)
Destination:
q (FF)
Source Clock:
clk rising

Data Path: q to
Cell:in->out
Gate
Net
---------------------------------------- ------------------------------------------------------FDCE:C->Q
2 0.992 1.150 q (q_OBUF)
LUT3_L:I2->LO
1 0.468 0.000 _n00011 (_n0001)
FDCE:D
0.724
-------------------------------------------------------------------------------------------------
172

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________
Total

(65.5% logic, 34.5% route)
PRECAUTIONS:
SIMULATION:
173

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________
SR FLIPFLOP
174

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________
AIM:
Synthesis for digital circuit.
APPARATUS:
1. System
2. Xilinx Software
PROCEDURE:

175

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________


176

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________
for options.
OK.

177

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________
board.
PROGRAM:
library IEEE;
use IEEE.STD_LOGIC_UNSIGNED.ALL
entity srff is
Port ( s : in bit;
r : in bit;
clk : in bit;
q : buffer std_logic);
end srff;
architecture Behavioral of srff is
begin
178

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________
process(clk)
begin
if clk='1' and clk'event then
if(s='0' and r='0') then q<=q;
elsif(s='0' and r='1') then q<='0';
elsif(s='1' and r='0') then q<='1';
elsif(s='1' and r='1') then q<='Z';
end if;
end if;
end process;
end Behavioral;
179

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________
RTL SCHEMATIC:
180

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________
FIG: TECHNOLOGICAL SCHEMATIC
181

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________
SYNTHESIS:
==================================================
==============
*
Final Report
==================================================
==============
Final Results
Output Format
: srff.ngr
: srff
: NGC
Optimization Goal
: Speed
Keep Hierarchy
: NO
Design Statistics
# IOs
:4
Macro Statistics :
# Registers
:2
:2
1-bit register
182

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________
# Multiplexers
#
1-bit 4-to-1 multiplexer
# Tristates
#
:1
:1
:1
1-bit tristate buffer
:1
Cell Usage :
# BELS
:3
:3
LUT2
# FlipFlops/Latches
#
FDE
:2
:2
# Clock Buffers
#
:1
BUFGP
:1
# IO Buffers
:3
IBUF
OBUFT
:2
:1
==================================================
==============Device utilization summary:
-------------------------------------------------------------------------------------------------------Selected Device : 2s50eft256-6
Number of Slices:
2 out of
768
183
0%

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________
2 out of 1536
0%
3 out of 1536
0%
4 out of
Number of GCLKs:
1 out of
182
4
2%
25%
==================================================
==============Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
------------------------------------------------------------------------------------------------------Offset:
Source:
Destination:

r (PAD)
Mtrien_q (FF)

Data Path: r to Mtrien_q
Gate
Cell:in->out
Net
---------------------------------------- ------------------------------------------------IBUF:I->O
LUT2:I0->O
FDE:CE
3 0.797 1.320 r_IBUF (r_IBUF)

2 0.468 1.150 _n00121 (_n0012)
0.687
Mtrien_q
184

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________
----------------------------------------------------------------------------------------------Total

(44.1% logic, 55.9% route)
PRECAUTIONS:
185

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________
SIMULATION
186

SINGRAYAKONDA
Ex. No:
Date:
_____________________________________________________________________________________
187

M.tech Lab Record VHDL

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MALINENI LAKSHMAIAH ENGINEERING COLLEGE

Double click on create new source.

MALINENI LAKSHMAIAH ENGINEERING COLLEGE

Write the program & click on program name in source window.

Once check syntax is completed successfully, you can go for simulation.

Click on + icon of model sim simulator then double click on simulator

Click on + (ZOOM) icon to maximize the window of waveform.

MALINENI LAKSHMAIAH ENGINEERING COLLEGE

Double click on configure target device & click on yes.

Turn on the power for the board and click on finish.

Impact will start to download the bit file to board.

MALINENI LAKSHMAIAH ENGINEERING COLLEGE

See the output ports by varying the input ports.

MALINENI LAKSHMAIAH ENGINEERING COLLEGE

MALINENI LAKSHMAIAH ENGINEERING COLLEGE

and_gate port map (a,b,c);

MALINENI LAKSHMAIAH ENGINEERING COLLEGE

LOGIC SYMBOL AND TRUTH TABLE:

MALINENI LAKSHMAIAH ENGINEERING COLLEGE

MALINENI LAKSHMAIAH ENGINEERING COLLEGE

MALINENI LAKSHMAIAH ENGINEERING COLLEGE

MALINENI LAKSHMAIAH ENGINEERING COLLEGE

or_gate port map(a,b,c);

MALINENI LAKSHMAIAH ENGINEERING COLLEGE

LOGIC SYMBOL AND TRUTH TABLE:

MALINENI LAKSHMAIAH ENGINEERING COLLEGE

MALINENI LAKSHMAIAH ENGINEERING COLLEGE

MALINENI LAKSHMAIAH ENGINEERING COLLEGE

MALINENI LAKSHMAIAH ENGINEERING COLLEGE

Architecture not_str of not_gate is

not_gate port map(a,c);

MALINENI LAKSHMAIAH ENGINEERING COLLEGE

LOGIC SYMBOL AND TRUTH TABLE:

MALINENI LAKSHMAIAH ENGINEERING COLLEGE

MALINENI LAKSHMAIAH ENGINEERING COLLEGE

MALINENI LAKSHMAIAH ENGINEERING COLLEGE

MALINENI LAKSHMAIAH ENGINEERING COLLEGE

Architecture nand_str of nand_gate is

nand_gate port map(a,b,c);

MALINENI LAKSHMAIAH ENGINEERING COLLEGE

LOGIC SYMBOL AND TRUTH TABLE:

MALINENI LAKSHMAIAH ENGINEERING COLLEGE

MALINENI LAKSHMAIAH ENGINEERING COLLEGE

MALINENI LAKSHMAIAH ENGINEERING COLLEGE

MALINENI LAKSHMAIAH ENGINEERING COLLEGE

Architecture nor_str of nor_gate is

nor_gate port map(a,b,c);

LOGIC SYMBOL AND TRUTH TABLE:

MALINENI LAKSHMAIAH ENGINEERING COLLEGE

MALINENI LAKSHMAIAH ENGINEERING COLLEGE

MALINENI LAKSHMAIAH ENGINEERING COLLEGE

MALINENI LAKSHMAIAH ENGINEERING COLLEGE

MALINENI LAKSHMAIAH ENGINEERING COLLEGE

xor_gate port map(a,b,c);

LOGIC SYMBOL AND TRUTH TABLE:

MALINENI LAKSHMAIAH ENGINEERING COLLEGE

MALINENI LAKSHMAIAH ENGINEERING COLLEGE

MALINENI LAKSHMAIAH ENGINEERING COLLEGE

MALINENI LAKSHMAIAH ENGINEERING COLLEGE

MALINENI LAKSHMAIAH ENGINEERING COLLEGE

Architecture xnor_str of xnor_gate is

xnor_gate port map(a,b,c);

MALINENI LAKSHMAIAH ENGINEERING COLLEGE