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IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 25, NO. 2, MARCH/APRIL 1989

Analysis and Design of a Three-phase Current Source Solid-state Var Compensator

Absfrucf-A reactive power compensation (RPC) system which employs a three-phase current-source force-commutated PWM rectifier is presented and analyzed. Pulsewidth modulation is also investigated as a means of reducing the size of reactive components. The proposed RPC system can compensate for leading and lagging displacement power factor. Other areas of investigation include the selection of rectifier input and output filter components and the closing of the loop around the reactive power command signal. Finally, predicted results are verified experimentally.

MRINS

" : T S
-j1 1

Balanced

Controllable Current Source

Fig. 1. Principle of reactive current compensation.

I. INTRODUCTION
HE ADVANTAGES of introducing force-commutated inverters and rectifiers in reactive power compensation have been confirmed by many researchers [1]-[7] and are gradually being recognized by the static converter industry and the large-scale users of electric power [8], [9]. These advantages include potential size, weight, and cost reduction of associated reactive components [4], [7], precise and continuous reactive power control with fast response times [ 11-[3], and avoidance of resonances created by peripheral low-frequency current sources. The topology of the reactive power generator presented in this paper is shown in Fig. 2 . The proposed scheme can compensate for displacement power factor value in a threephase balanced system. It can also provide either leading or lagging reactive power which represents a considerable reduction in passive storage element ratings as compared with other static var compensator approaches [9]. Although singlephase and three-phase versions of the topology shown in Fig. 2 have already been presented in the technical literature [ 11-[3], [7], the solid-state compensator scheme used in this paper differs from previously discussed approaches in the following ways. 1) It is targeted towards applications which mainly require displacement power factor compensation (i.e., harmonics excluded) with a slow response time. 2 ) Slow response times allow the use of PWM current waveshaping switching patterns that minimize the generation of unwanted harmonics.
Paper IPCSD 88-7, approved by the Static Power Converter Committee of the IEEE Industry Applications Society for presentation at the 1987 Power Electronics Specialists Conference, Blacksburg, VA, June 22-26. Manuscript released for publication May 13, 1988. L. Moran and P. D. Ziogas are with the Department of Electrical and Computer Engineering, Concordia University, 1455 de Maisonneuve Boulevard, Montreal, PQ, Canada H3G 1M8. G. Joos is with the Universite de Quebec, Ecole de Technologie Superieure, 4750 rue Henri-Julien, Montreal, PQ, Canada H2T 2C8. IEEE Log Number 8825290.

3) These patterns can be easily stored in an EPROM, thus simplifying logic software and hardware requirements. 4) The use of an optimized PWM current waveshaping pattern allows significant reduction in the filter component values and sizes. They also require lower switching frequencies, which contribute to lower switching stresses of converter components. 5 ) Lower component stresses allow higher levels of output power from the same converter topology. Moreover, the treatment presented in this paper includes methods of reactive current control for optimizing the system response, input and output filter component design, analysis of current and voltage stresses of converter components, and a method of closing the reactive power demand loop. Finally, a design example and experimental steady-state results obtained on a scaled-down laboratory unit are also presented, discussed, and evaluated.
11. PRINCIPLESOPERATION OF

The RPC system used in this paper can be explained by considering a controllable current source connected in parallel with the load as shown in Fig. 1. The controllable current source generates a sinusoidal current waveform I / , leading or lagging by 90" with respect to the corresponding phase-toThis implies only reactive power neutral source voltage Vun. flows in bilateral form, going from the controllable current source to the ac system for leading 90, and vice-versa for lagging 90". The amount of reactive power generated or absorbed by the controllable current source can be easily controlled by adjusting the amplitude of the current I / . The expression becomes var = Vu,,I/.
(1)

However, 1, must be made to lag or lead V,, by an angle approximately equal to 90" so that the controllable current source absorbs adequate real power from the ac system, which coincides with the current source losses. Fig. 2 depicts a practical version of the controllable current source shown in Fig. 1. The force-commutated PWM rectifier

0093-9994/89/0300-0356$01.OO O 1989 IEEE

MORAN el al.: CURRENT SOURCE SOLID-STATE VAR COMPENSATOR

357

T O R

RENCE

Fig. 2.

Reactive power compensator configuration

is set to operate at a phase-shift angle CY which is close to 90" (leading or lagging). At this point the force-commutated rectifier is capable of compensating for system losses while maintaining the required reactive power level. The required reactive power value can be regulated by adjusting the amplitude of the ac input current I, through a gating control of rectifier switches. It is noted that the magnitude of the ac input , current Z is dependent on the magnitude of the dc current Zdc. To increase the amplitude of I,, a small positive dc voltage must be applied to the reactor so that Idcwill increase until it reaches the required value. The expression becomes

a
MR I NS

Force-

Gating

PWM SIgnalsRect i-

Reactive C u rce na t o r al r ul t

Fig. 3.

Closed-loop control of compensating current.

storage element. The clamping circuit connected to the dc side is designed to absorb, in case of fault, the whole energy of the In the same way, if it is necessary to decrease the amplitude dc reactor while keeping the resulting voltage stresses on of I,, then a small negative dc voltage must be applied to the system components within safe limits. reactor. The expression is given by B. CY Phase-Shift Control Circuit Description The block diagram of the a phase-shift control circuit shown (3) in Fig. 3 is expanded in Fig. 4. This circuit consists of an adder, a voltage-controlled osci!lator (VCO), a counter, and a The required levels of positive or negative Vdc voltages are stored switching pattern. An optimized stored PWM current obtained through CY control around the 90" point with a closed- waveform switching pattern which minimizes the generation loop control. The block diagram of the closed-loop control is of unwanted harmonics is continuously applied to the six shown in Fig. 3. converter switches [lo]. The main advantage of the CY phaseshift control scheme is that is does not require a zero crossing 111. SYSTEM DESCRIPTION detector for gating signal synchronism. This avoids jittering A . Power Circuit Description problems caused by harmonic components in the voltage The power circuit of the force-commutated PWM rectifier system. is shown in Fig. 2. The nature and functions performed by Principle of Operation: Under steady-state operating conditions (i.e., CY = 90" leading or lagging) the var demand each major system component are described as follows. The first major system component is a three-phase force- is zero and the stored switching pattern is read at a fixed commutated PWM rectifier. The ac terminals of the rectifier frequency f,(i.e., ac supply frequency). If the var reference are connected to the ac mains through an LC input filter. The changes, the control system adjusts the input voltage of the rectifier input ac filter acts as an interface between the 3-4 VCO to read the stored pattern at a different frequency, thus PWM force-commutated rectifier and the ac mains. As such, providing the correct value for the phase-shifting angle CY. its function is to minimize the dumping of current and voltage Note that the frequency of the VCO is changed only until CY harmonics on utility lines. The dc side of the force-commu- reaches the new value. For leading var compensation, if the tated rectifier is connected to a reactor which carries a pattern is read at a frequency lower thanfo (i.e., CY > 270"); unidirectional current Zdc and is the main reactive energy then the value of the reactive power generated will increase,

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IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 25, NO. 2 , MARCHIAPRIL 1989

Recti Demand ,Control

osc I

led

Counter

I Iator

Fig. 4.

Phase-shift

01

control circuit.

a2

a4?6$8

TABLE I
FREQUENCY SPECTRA OF CURRENT WAVEFORM ASSOCIATED WITH THE SWITCHING PATTERN

Order

n
Fig. 5. Rectifier modulation scheme and associated switching angles ( a l =
2.1", a2 = 13.8", a3 = 17.5", a4 = 25.2", 42.5", a8 = 46.2", a9 = 57.9").

Amplitude (percent)
100 0.113 0.288 2.121 1.273 1.641 8.511

Order n
23 25 29 31 35 37 41

Amplitude (percent)
4.603 8.872 25.906 2 1.473 9.176 9.331 6.927

as

= 30",

a6

= 34.8",

a,

1 5 7 11 13 17 19

7) The rectifier switching pattern is as shown in Fig. 6 .

Design data are expressed in per unit with respect to the following base: Vbase = rated value of the fundamental component of the force-commutated rectifier input line-to-neutral voltage Vu,, rated value of the fundamental component of the force-commutated rectifier input phase current I,.

base

Fig. 6.

(a) Switching function. (b) Respective frequency spectrum.

and for lagging var compensation, the reactive power generated will increase if the pattern is read at a frequency higher thanfo (i.e., a < 90").

The base values of the dc side, for the modulation scheme used (Fig. 6 ) are

I, base = 1.38581,,1 ,
Z,, base = 1.562 Z,, base.
A . Input Filter Design

(4)
(5)

C. P WM Switching Pattern Description

The optimized stored PWM current waveshaping pattern is shown in Figs. 5 and 6. Table I and Fig. 6 show the frequency spectrum of the ac input current waveform I, generated with this pattern. Inspection of this frequency spectrum (Fig. 6 and Table I) shows that the PWM scheme selected for the forcecommutated rectifier (Fig. 2) attenuates the low-order harmonics of the current I, effectively. The amplitude of the fundamental component of I, has been taken as 100-percent A.

The size, cost, and complexity of the input filter is determined mainly by the specified total harmonic distortion in the ac current (THD,) and in the ac voltage (THD,). By definition, THD, and THD; are

IV. POWER CIRCUIT DESIGN

The power circuit design data presented in this section have been obtained with the following assumptions.
1) The three ac mains voltages are balanced. 2) The rectifier switching elements are ideal. 3) The filter components are ideal. 4) The direct current Idc is ripple-free. 5 ) The input ac filter delivers rated reactive power. 6) The force-commutated rectifier is delivering rated leading reactive power.

where Vu is the rms value of the force-commutated rectifier phase-to-neutral voltage, Val is the rated rms value of the fundamental component of Vu,and (7) where ZI is the rms value of the line current, and I / , ]is the rated rms value of the fundamental component of I / . Since input current I / ( t ) contains an infinite number of harmonic components, for a leading power factor it is

M O W N et a/.: CURRENT SOURCE SOLID-STATE VAR COMPENSATOR

359

analytically defined by
rn

I/(t)=
k= 1

I/,k

sin { k ( w t + 9 0 " ) } .

(8)

Similarly, the force-commutated rectifier PWM input line current is analytically defined by
rn

Za(t) =
k= 1

Ia,k

sin { k ( wt + 90"))

(9)
(d) Fig. 7. Analytical model for input filter. (a) Single-phase equivalent input filter circuit. (b) Single-phase equivalent circuit at fundamental frequency. (c) Phasor diagram for leading power factor. (d) Phasor diagram for lagging power factor.
Ill, L

and the Fourier coefficients I a k for odd k are defined by

where M is the number of chops per half-cycle in the input current Za(t)( M = 11). With the assumption that all the harmonics I a k circulate through the capacitor, from Fig. 8
I

Fig. 8. Single-phase equivalent input filter circuit for harmonics.

filter components are given by (18) and (19): then TkVal= X/Z;, +k=5 k=5

Xf
k-5

';,k

k3

is the total apparent power required by the reactor, and TkVa,=;+X,

and from (6)

"f

cc

' f k

X,=

[ 5 [4] '1
Vu,1 THDu
k=5

x c

k=5

Fig. 8 shows that in magnitude

and from (7)

[5
k=S

[!!$-I21

From Fig. 7
f

is the total apparent power required by the capacitor. Solving (lo), (13), and (15)-(19) with the constraints that under rated operating condition THDi 5 percent and THD, 10 percent, for leading power factor it is found that X, = 7.27 pu and X, = 0.0684 pu. The apparent power required by the capacitor and by the reactor is 0.1767 pu and 0.0939 pu. The input filter design data associated with the forcecommutated PWM rectifier and with a respective structure which utilizes a six-step rectifier are summarized in Table 11. Table I1 shows that the proposed RPC structure yields significant reductions in the ac input filter component values (approximately 70 percent) and in the filter reactive kVA (approximately, 74 percent) as compared to structures which utilize six-step rectification.

<

<

/,I

-. -J

B. Semiconductor Switch Ratings

For rated operating conditions the design data presented in Table I11 include rms, average, and peak current rating for each switch, as well as peak forward and reverse blocking voltages and switching frequencies. The type of gate commutated switches (i.e., power FET's, bipolars, GTO's, etc.) is not specified, because the choice of switches depends on the respective voltage and current levels. All the relevant data are presented, in summary form and in pu with respect to ac base values, in Table 111.

or

I / , ~ =j for leading or lagging power factor. The total apparent power (TkVA) required by the input

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IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 25, NO. 2, MARCHIAPRIL 1989

TABLE I1
DESIGN DATA FOR AC INPUT FILTER (pu)

System Configuration

XI

x c
7.27 2.1565

TkVAl L,

TkVA, C,

TkVA

I, rmsa

I,,

V, rms

V,,

11rms

111

Force-commutated PWM rectifier 0.0684 Rectifier working without PWM 0.2524

a

0.0939 0.5479

0,1767 0.4913

0.2706 1.0392

1.0768 1.0441

1 1

1.005 1.005

1 1

1.139 1.4655

1.1376 1.4637

RMS value of the force-commutated rectifier ac input current.

TABLE III
RECTIFIER SWITCH RATINGS (PU)

System Configuration Force-commutated PWM rectifier Rectifier working without PWM

a

Peak Current

Average Current

RMS Current

Peak ForwardBlocking Voltage

Peak ReverseBlocking Voltage

fs
(W
660

1.3858 1.2825

0.4619 0.4275

0.8
0.7405

2.45 2.45

2.45 2.45

60

f , : switching frequency

(fs = Np x

f ).

C. DC Reactor Design
For symmetrical and sinusoidal ac waveforms, reactive power is compensated by interchanging energy among the phases. In this case the dc reactor only serves to ensure correct operation of the RPC converter. For this reason, the design of the dc reactor is performed with the constraint that under rated operating conditions the ripple factor for the direct current Id, is less than five percent and the ac line-to-line input voltages are balanced and sinusoidal. Hence

The voltage across the reactor

Vd,(t)

is given by

ldc

where
v r ,k Ir,k=-

kwL

where ( a ) , ( b ) , and ( c ) are the switching functions of the force-commutated rectifier obtained with the PWM scheme (Fig. 6), and V,,(t), Vb,(t), V,,(t) are the inputs phase-toneutral voltages. The maximum apparent power allowed in the reactor is limited by inductor saturation and is given by kV
A p k = vr,peakIr,peak.

and

(24)

K; ripple current factor, Irk rms value of the kth current harmonic through the dc
reactor, average value of the direct current through the reactor, v r k rms value of the kth voltage harmonic across the dc reactor, W L impedance of the dc reactor at mains frequency (i.e., WL = 1207rL a),
Id,

and

Table IV summarizes the design data for the dc reactor associated with the force-commutated PWM rectifier and with the typical six-step rectification scheme. The dominant direct-current harmonic with the PWM scheme employed here are the thirtieth and the sixth, respectively. Consequently, the required inductance L value will be significantly smaller with the PWM scheme (Table IV). However, the maximum apparent power of the dc reactor is higher with the PWM scheme than with the typical six-step structure, as shown in Table IV. The reason becomes clear as soon as one examines the values of peak voltages and peak current across and through the dc reactor with both schemes.

MORAN et al.: CURRENT SOURCE SOLID-STATE VAR COMPENSATOR

36 1
TABLE IV

DESIGN DATA FOR DC REACTOR^

System Configuration Force-commutated PWM rectifier Rectifier working without PWM

a

WL

kVA Peak

0.2779 1.0822

3.4492 3.3395

PU with respect to the ac base values.

V.

CY

PHASE-SHIFT CONTROL CIRCUIT DESIGN

CY

The main parameters for the design of the control circuit are

phase-shift

1) the ac mains frequency f a c , 2) the storage resolution 6 of the PWM switching pattern in degrees. Assuming a storage resolution of 6 degrees per memory location, it follows that the total number of memory locations N required becomes 3 60 N=6 Furthermore, for better compatibility with existing memory devices, 6 should be chosen such that
-1

where m is an appropriate integer number. Consequently, the number of stages m of the counter required to address sequentially the aforementioned memory locations must satisfy (26). Also, since the switching pattern must be read f , times per second, the corresponding frequency of the address counter clock becomes

(4 Fig. 9 . Rectifier simulated waveforms for capacitive mode of operation with = PWM scheme (X, 7.27 pu, X I = 0.0684 pu, THD, = 0.05 pu, THD, = 0.1 pu). (a) Switching function phase A . (b) AC line current Z(wt)phase A , , waveform; phase-to-neutral V( wt) waveform. (c) Rectifier ac input current I,(wt) waveform; rectifier phase-to-neutral input voltage Vok(wt) waveform. (d) DC voltage Vdc(wt) waveform.

VI. SIMULATED RECTIFIER PWM RESULTS To verify analytical key results, the aforementioned RPC structure, as specified in the first row of Tables 11-IV, was tested by simulation on a HP 9836-DATA 6000 system. A dedicated computer program was employed to generate the switching functions and the steady-state voltage and current waveforms shown in Figs. 9(a)-(d), 10(a)-(d), and ll(a) and 1l(b). Further processing of these waveforms on the DATA 6000 waveform analyzer yielded the frequency spectra shown in Figs. ll(a) and ll(b). Figs. 9(a) and 10(a) show the switching function for the phase A for leading and lagging modes of operation. Figs. 9(b) and 10(b) show the ac line current I,and the corresponding phase-to-neutral voltage Vanobtained with the operating conditions depicted in Figs. 9 and 10. Figs. 9(c) and 1O(c) show the input phase-to-neutral voltage of the force-commutated PWM rectifier Vak with the corresponding ac input current I,. Figs. 9(d) and 10(d) show the dc voltage applied across the dc reactor for leading and lagging reactive power compensation. Finally, Fig. ll(a) and (b) show the input line current I, waveform and its frequency spectrum obtained for leading var compensation and lagging var compensation, respectively. VII. DESIGN EXAMPLE To illustrate the significance and facilitate the use of the theoretical results obtained in the previous section, the following example is given.

A . Power Circuit
van

fi

ac supply, 117 V, RPC input apparent power, I . 1 kVA, supply frequency, 60 Hz.

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IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 25, NO. 2, MARCHiAPRIL 1989

r l
"

(d) Fig. 10. Rectifier simulated waveforms for inductive mode of operation with PWM scheme ( X , = 7.27 pu, X , = 0.0684 pu, THD, = 0.05 pu, THD, = 0.1 pu). (a) Switching function phase A . (b) AC line current I / ( w f ) phase A waveform; phase-to-neutral V,,(wt) waveform. (c) , Rectifier ac input current I( wt) waveform; rectifier phase-to-neutral input waveform. voltage V,,(wt) waveform. (d) DC voltage Vdc(wt)

1 pu

Z=36.5 Q

1 pu f=60 Hz. Therefore, using Tables 11-IV, the specifications of the components of the RPC system are given by the following. 1) Input Filter: X,=2.5 Q Xc=265 Q Li=6.6 mH kVAL = 35.2 VA kVAc= 66.3 VA.

C;= 10 pF

2) Semiconductors:
Peak current = 4.4 A. Average current = 1.5 A. Rrns current = 2.6 A. Peak forward voltage = 287 V. Peak reverse voltage = 287 V. Switching frequency = 660 Hz.

3) DC Reactor:
Fig. 11. Simulated input current I , ( w f ) waveform with its respective frequency spectrum. (a) Capacitive mode of operation. (b) Inductive mode of operation.

wL=10.14 0

L = 2 7 mH

kVA,,k=

1293 VA.

B.

CY

Phase-Shift Control Circuit

Using the preceding specifications, 1 pu 1 pu 1 pu V=117 V S = 3 7 5 VA 1=3.2 A

Theoretical investigation of the switching pattern employed in this paper (Section 111-C) has shown that a resolution of 0.0879' per memory location maintains to a clme degree the harmonic spectrum shown in Table I. Consequently, the number of memory locations chosen for the experimental investigation of the KPC system becomes N = 360/0.0879 =

MORAN et al.: CURRENT SOURCE SOLID-STATE VAR COMPENSATOR

363

Fig. 12. Experimental RPC voltage and current waveforms for capacitive var compensation with PWM scheme. (a) Input line current I,; 2 A/div, phase-to-neutral source voltage V,: 50 V/div,fo = 60 Hz.(b) Input line current I, and its frequency spectrum. (c) Rectifier input line-to-line voltage Vob:100 V/div. rectifier input current I,; 2 A/div, fo = 60 Hz.(d) Voltage across the dc reactor Vdc: 100 V/div,f, = 360 Hz.

4096 memory locations. The frequency of the address counter clock is given by

fclock=60 4096 = 245.76 ~ H z . X

VIII. EXPERIMENTAL RESULTS

experimental currentholtage waveforms and values. Moreover, agreement in waveforms implies agreement in respective peak average and rms currentholtage values.

A . Dynamic Performance
The RPC system was tested for dynamic response using a To check the validity of the proposed analysis and design biased sinusoidal-wave var reference. The amplitude of the method, selected theoretical results were verified with an reference was adjusted to cause the RPC system to swing to its experimental 1.1-kVA unit. Steady-state results obtained with rated limits. The frequency of the sinusoidal reference var this RPC experimental unit are depicted in Figs. 12 and in 13. reference was increased until the vars generated by the RPC Figs. 12(a) and 13(a) show the input line current Z,(wt) with could no longer track the reference. The performance evaluathe phase-to-neutral source voltage Van( wt) for leading and tion of the subject model has revealed excellent system lagging var compensation. Figs. 12(b) and 13(b) show the response under dynamic conditions with maximum bandwidth input line current I , ( w t ) and its frequency spectrum. From of 10 Hz, as shown in Fig. 14. these figures, it is apparent that I,(wt) has a low total IX. CONCLUSION harmonic distortion (THD;). This result is in close agreement 5 percent specification that has been with the THD; In this paper a reactive power compensation system which included in the design of the RPC structure. Figs. 12(c) and employs a three-phase current source force-commutated w 13(c) illustrate experimental input line-to-line voltage Vab( t ) PWM rectifier has been presented and analyzed. The proposed and input line current Ia(wt). Finally, Figs. 12(d) and 13(d) scheme is targeted for applications which mainly require show the dc voltage applied across the force-commutated displacement power factor compensation (leading or lagging) rectifier for leading and lagging modes of operation. with a slow response time (i.e., harmonics excluded). PulseComparison with simulated waveforms shown in Figs. 9 width modulation is used as a means of reducing the size of and 10 reveals a close agreement between predicted and reactive components. The close agreement between analytical

<

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IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 25, NO. 2, MARCHIAPRIL 1989

(b) (4 Fig. 13. Experimental RPC voltage and current waveforms for inductive var compensation with PWM scheme. (a) Input line current I,; 2 A/div, phase-to-neutral source voltage Van: 50 V/div, f o = 60 Hz. (b) Input line current I , and its frequency spectrum. (c) Rectifier input line voltage Vob: 100 V/div, f o = 60 Hz. (d) Voltage across dc reactor Vdc: 100 V/div,fo = 360 Hz.

Fig. 14. Response of RPC to biased sinusoidal-wave var reference. (a) Var reference. (b) DC current I,, .

and experimental results proves the validity of the analysis and the feasibility of the proposed RPC system.

REFERENCES
L. H. Walker, Force-commutated reactive power compensator, IEEE Trans. Ind. Appl., vol. IA-22, no. 6, pp. 1091-1104, Nov./ Dec. 1986. [2] L. Malesani, L. Rossetto, and P. Tenti, Active filter for reactive power and harmonic compensation, in Conf. Rec. 1986 17th Annu.
[l]

Meer. IEEE Pow. Elec. Council, Vancouver, Sept. 1986, pp. 321330. 131 J . Van Wyk, D. A . Marshall, and S . Boshoff, Simulation and experimental study of a reactively loaded PWM converter as a fast source of reactive power, IEEE Trans. Ind. Appl., vol. IA-22, no. 6, pp. 1082-1096, Nov./Dec. 1986. [4] L. Gyugyi, Reactive power generation and control by thyristor circuits, lEEE Trans. Ind. Appl., vol. IA-15, no. 5 , pp. 521-532, Sept ./Oct. 1979. [SI F. Harashima, H. Inaba, and K . Tsuboi, A closed-loop control system

MORAN et al.: CURRENT SOURCE SOLID-STATE VAR COMPENSATOR

365
Phoivos D. Ziogas (S75-M78) received the B.S., M.S., and Ph.D. degrees from the University of Toronto, Toronto, ON, Canada, in 1973, 1974, and 1978, respectively. Since 1978 he has been with the Department of Electrical Engineering of Concordia University in Montreal, PQ, Canada, where he is engaged in teaching and research in the area of static power converters. He also has participated as a Consultant in several industrial projects.

for the reduction of reactive power required by electronic converters, IEEE Trans. Ind. Electron. Contr. Instrum., vol. IECI-23, no. 2, pp. 162-166, May 1976. A. Alexandrovits, A. Yair, and E. Epstein, Analysis of static var compensator with optimal energy storage element, IEEE Trans. Ind. Electron., vol. IE-31, no. I , pp. 28-33, Feb. 1984. r71 Y. Sumi et al., New static var control using force-commutated inverters, IEEE Trans. PowerApp. Syst., vol. PAS-100, no. 9 , pp. 4216-4223, Sept. 1981. W. Hochstetter, Properties of static compensators for power supply systems, Siemens Rev., vol. XLIV, no. 8, pp. 356-360, Aug. 1977. E. Wirth, B. Roesle, 1. Sadek, and M. Hausler, Static var compensators for H.V. system-basic design and operation, BrownBoveri Publication, no. CH-N. P. Ziogas, Y. Kang, and V. Stefanovic, Optimum system design of a three phase rectifier-inverter type of frequency changer, IEEE Trans. Ind. Appl., vol. IA-21, no. 5 , pp. 1215-1225, Sept./Oct. 1985.

Luis T. Moran (S78-M82) received the degree in electrical engineering from University of Concepcion, Chile, in 1982. He is currently working towards the Ph.D. degree in electrical engineering at Concordia University in Montreal, PQ, Canada. From 1982 to 1985 he was with the Department of Electrical Engineering of University of Concepcion, Concepcion, Chile.

Geza Joos (M78) was born in France on March

18, 1951. He received the M.Eng. and Ph.D. degrees from McGill University, Montreal, PQ, Canada, in 1974 and 1987, respectively. He has worked for Brown-Boveri Canada on traction equipment and has been with the Department of Electrical Engineering, Ecole de Technologie Supixieure, since 1978. His main interests are rotating machines and power electronics. Dr. Joos is a member of the Order of Engineers of the Province of QuCbec.