我的stm32f4学习历程

90
51
2012 1 17

2011 9 cortex-m4 stm32f407VG
168M FPU DSP st
MCU
TI cm4 65nm Cortex M4 MCU
StellariAtmel cortex-m3 ST
M4 cortex-m4 ST
STM32f4 DSP
TI M4 ST M3 NXP M4-M0
M4
stm32f4-discovery
MEM
USB
ST
^*^
IAR Keil IAR
Zigbee Keil
Cortex-M4 Devices Generic User GuideARM M4

RM0090 Reference manualST stm32f4
stm32f407_datasheetstm32f407

STM
M32F4Disscovery
STM32F4Diiscovery
STM32F4077VGT6 STLINK/V2
2
MEMSUSBO
OTG
STM
F4 h
http://www.st.com/stm322f4discovery
1. STM32F407V
VGT6 32 A
ARMCortexM
M4F 1MBFlash
192KBRAM
M
LQFP100

2. STLINK
K/V2 //
STLINK
K/V2
SW
WD
3. USB
5V

3
3.0V~5.0V
4. LIS302DLSSTMEMS
5. CS43L22
D
DAC
C
6. 8 LED
LD1(red/green) USB
LD2(red) 3.3V
4 LEDs,LD3(orange),LD4(green),LD5(red)andLD6(blue)
2USBOTGLEDsLD7(green)VBusandLD8(red)overcurrent
STM32F407VGT6
16MHz RC RC 1
RC 426MHz
RC
PLL 168MHz
AHB APBAPB2
APBAPB1AHB 168M APB 84M APB
42M
PLLPLLI2S I2S 8 kHz 192 kHz
SYSCLK
HSI
HSE
PLL
32K
32.768K
STM32F44xx
IAR
IAREmbedd
dedWorkben
nchforARM ARM
C/C++
+
IAREmbeeddedWorkb
bench
ARM
for A
C/C++
ARM
ARM
M IAREmbedd
dedWorkben chforARM
IAR
R Embedded Workbench for ARM
ARM
M
FLASH//PROMable

IARSysstems
IA
AR
1.
userinc
startup
2. st
http://www.stmcu.org/do
ownload/indeex.php?act=d
down&id=723
3
3. STTM32F4Disco
overy_FW_V11.1.0\Project\Demonstrattion\EWARM
stm32f40x_fflash.icf
STM32F4Discovery_FW_V1.1.0\Libbraries\CMSIS\Include core__cm4.h
core_cm4_simd.h core_
_cmFunc.h core_cmInstr.h in
nc
STM32F4Disc
S
covery_FW_V
V1.1.0\Libraries\CMSIS\ST
T\STM32F4xxx\Include
stm32f4xx.h system_sttm32f4xx.h
in
nc in
nc
4. STM32F4Discovery_FW_V1.1.0\Libbraries\CMSIS\ST\STM32F4xx\Source\\Templates\ia
ar
starttup_stm32f4xxx.s sstartup
5. STM32F4Discovery_FW_V1.1.0\Libbraries\CMSIS\ST\STM32F4xx\Source\\Templates
system__stm32f4xx.cc
user
6. IAR
Project>
>CreatNewPProject,
OK
7. Filles
Add
AddG
Group
user OK
O
6 Grroup
startup inc
8. inc>Ad
dd>Files

inc
7 Groupstartup
startup startup_stm32f4xx.ss Group
G
userr
user
system_stm
m32f4xx.c
9. File
mian.c user
10. Grroupuser
11. Op
ptions
Target
C/C++C
Compler
Prerocesssor
Linker
Overridede
efault
stm32f4
40x_flash.icf
DebuggerDriver ST
TLINK

Download
Useflashloadeer
STLINKIn
nterface
SWD
OK
main.c
//filemain.c
#include<stm32f4xx.h>
voidmain()
{
while(1);
}
F7
inc
stm32f4xx.h
h
stm332f4
C51 reg52
2.h
core_cm4.h
NVIC
core_cmInsttr.h

core_cmFun
nc.h
core_cm4_ssimd.h
system_stm32f4xx.h system_stm332f4xx.c
user
syste
em_stm32f4xxx.c
main.c
systeem_stm32f4xxx.c
startup
startup_sstm32f4xx.s
1. SP
P
2. PC
C
3.
4.
5.
6. mian
syste
em_stm32f4xxx.c SystemInit()
S
main
IAR
Linkkerconfigurattionfile
OK
GPIO
stm32f407VG PAPE 516 80 IO I/O
4 32 GPIOx_MODERGPIOx_OTYPERGPIOx_OSPEEDRGPIOx_PUPDR
32 GPIOx_IDR GPIOx_ODR
32 /GPIOx_BSRR
32 GPIOx_LCKR 32 GPIOx_AFRH
GPIOx_AFRL
1.
2. IO
3. \
4.
5. >=50M
6.
7.

/************************************
GPIO
IARforARM6.21
stm32f4discovery
168M
author
data20120116
*************************************/
uint32_tGb_TimingDelay;
voidDelay(uint32_tnTime);
voidmain()
{
SysTick_Config(SystemCoreClock/1000); // systemtick
RCC>AHB1ENR|=0x00000008; // GPIOD
RCC>APB2ENR|=(1<<14); // syscfg
GPIOD>MODER&=0x00FFFFFF;
// PD12,13,14,15
GPIOD>MODER|=0x55000000;
GPIOD>OTYPER&=0xFFFF0FFF; // PD12,13,14,15
GPIOD>OSPEEDR&=0x00FFFFFF; //PD12,13,14,15 100m

GPIOD>OSPEEDR|=0xff000000;
SYSCFG>CMPCR=0x00000001; // IO
// GPIO 50M
GPIOD>PUPDR&=0x00FFFFFF; //PD12,13,14,15
GPIOD>BSRRH=0xf000; //resetregisterGPIOx_BSRRH,writeonly
//setregisterGPIOx_BSRRL,writeonly
while(1)
{
GPIOD>BSRRH=0xf000;
GPIOD>BSRRL=0x1000;
Delay(500);
GPIOD>BSRRH=0xf000;
GPIOD>BSRRL=0x1000<<1;
Delay(500);
GPIOD>BSRRH=0xf000;
Delay(500);
GPIOD>BSRRH=0xf000;
Delay(500);
}
}
voidDelay(uint32_tnTime)
{
Gb_TimingDelay=nTime;
while(Gb_TimingDelay!=0);
}
voidSysTick_Handler(void)
{
if(Gb_TimingDelay!=0x00)
{
Gb_TimingDelay;
}
}
RM0090R
Referencema
anual
GPIO
Ox_MODER
31
30
29
28
27
26
25
24
23
3
22
21
2
20
19
18
17
16
MODER
R15[1:0]
MODEER14[1:0]
MOD
DER13[1:0]
MOD
DER12[1:0]
MO
ODER11[1:0]
MODER10[1:0]
M
MODER9[1:0]
MODER8[1:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
w
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
MODEER7[1:0]
rw
rw
MODER6[1:0]
MOD
DER5[1:0]
MO
ODER4[1:0]
rw
rw
rw
rw
rw
rw
MODER3[1:0]
MODER2[1:0]
MODER1[1:0]
MODER0[1:0]
rw
w
rw
rw
rw
rw
rw
rw
rw
MOD
DERy[1:0]
x
I//O
00
01
10
11
GPIOx_OTY
YPER
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
OT15
OT14
OT13
OT12
OT11
OT10
OT9
OT8
OT7
OT6
OT5
OT4
OT3
OT2
OT1
OT0
rw rw rw rw rw rw rw
rw
rw
rw
rw
rw
rw rw rw rw
31:116
115:0 x
I/O

0
GPIOx_OSP
PEEDR
OSPEEDRy[1:0] x
Y=0..155

I/O
002MHz
0125MHz
1050MHz
11100MHz
300pF80MHzz 15pF
SYSCFG
G_CMPCR
331:9
0II/O
7:2
0 CMP_PD
0
I/O
1
I/O
/
GPIOx_PUPDR
PUPDRy[1:0]
x
Y=0..15
I/O
00
01
10
11
GPIOx_IDR
31:116
115:0IDRy[15:0
0]
Y=00..15

I/O
GPIOx_ODR
R
31:116
115:0ODRy[15
5:0]Y==0..15
GPIOx_BSRR
331:16 x
Word
W
0
ODRxx
1
ODRx
BSX BRXBSX
115:0 x
Word
W
0
ODRxx
1
ODRx
GPIOx_LCKR
R
31:117
16 LCKK[16]
GPIO
Ox_LCKR
MCU
LOCK
LCKR[16]='1'+LCKR[15:0]
LCKR[16]=0+LCKR[15:0]
LCKR[16]='1'+LCKR[15:0]
LCKR
LCKR[16]='1'
LOCK
LCK[15:0]
LCKK
K
'1
1'
CPU
115:0LCKy
X YY=0..15
/ LCKK 0
GPIOx_
_AFRL
331:0
x YY= 0..7
I/O
AFRLLy
0001AFF1
00000AF0
00 10AF2
01011AF5
0110AFF6
01 11AF7
10100AF10
1011AFF11
11 00AF12
11111AF15
0011A
AF3
1000A
AF8
1101A
AF13
00100AF4
11001AF9
11110AF14
GPIOx_
_AFRH
331:0
x YY= 8..15
I/O
AFRLLy
0001AFF1
00000AF0
00 10AF2
01011AF5
0110AFF6
01 11AF7
10100AF10
1011AFF11
11 00AF12
11111AF15
0011A
AF3
1000A
AF8
1101A
AF13
00100AF4
11001AF9
11110AF14

NVIC
ST
T
AR
RM Cort ex-M4 Devi
ices Generi
ic User Guiide

Cortex--M4 Devices Generic U ser Guide
NVIC_ISER[[8]
8 ISER[0]
0~31
IS
SER[1] 32~63
IS
SER[0]
[31:00]SETENA
0=
1=
0=
1=
38
NVIC_ISER[1]
0 1
6 1
R M0090Referrence
man
nual
9 Table3
30.Vectortabble Positio
on
NVIC_ICER[8]
8 ICER[0]
0~31
IC
CER[1] 32~63
IC
CER[0]
[31:00]SETENA
0=
1=
0=
1=
8
***R[0]
NVIC_IISPR[8]
[31:00]SETPEND
0=
1=
0=
1=
NVIC_IICPR[8]
[31:00]CLRPEND
0=
1=
0=
1=
NVIC_IAB
BR[8]
[31:00]
0=
1=
NVIC_IPR
R[60]
60 32
st
240 8
NVIC
C>IP[240]
ARM
NVIC
C
SCB_AIRCR
[31:16] [10:8][3
31:16]
[10:8]
[31:16]
VECTKEYSTA
AT
VECTKEY
RW
0xFA05
0xx05FA VE
ECTKEY
[10:88]
ARM
M M4
8
stm32f44
4
16
4
stm32f4
[10:8]
0b011
xxxx
[7:4]
none
16
0b100
xxx.y
[7:5]
[4]
0b101
xx.yy
[7:6]
[5:4]
0b110
x.yyy
[7]
[6:4]
0b111
yyyy
none
[7:4]
16
NVIC
NVIC_SSTIR
SSCB_CCR USERSETMPEN
U
ND 1
[31:99]
[8:0]]INTID ID
0239
0x03
IRQ
Q3
EXTI
/ 23 /
EXTI 0~15 PX0~15()

EXTI 16 PVD
EXTI 17 RTC
EXTI 18 USBOTGFS
EXTI 19
EXTI 20 USBOTGHS FS
EXTI 21 RTC TimeStamp
EXTI 22 RTC
1.
2.
3. IO
4.
5.
6. IO
7.
8.
9.
10.
11.
12.

/************************************
EXTI
IARforARM6.21
stm32f4discovery
168M
author
data20120117
*************************************/
voidLed_Init(void);
voidmain()
{
RCC>AHB1ENR|=0x00000009;// GPIOD GPIOA

RCC>APB2ENR|=(1<<14); // syscfg
SCB>AIRCR=0x05AF0000|0x400; // =3:1
Led_Init();
GPIOA>MODER&=0xFFFFFFFC;//
GPIOA>PUPDR&=0xFFFFFFFC;
EXTI>IMR|=(1<<0); // 0
EXTI>FTSR|=(1<<0);//
SYSCFG>EXTICR[1]&=0xFFFFFF00; // 0 PA
NVIC>IP[6]=0xe0; // 1110
NVIC>ISER[0]|=(1<<6); // 6 0
while(1)
{
};
}

voidLed_Init()
{
GPIOD>MODER&=0x00FFFFFF;// PD12,13,14,15
GPIOD>OTYPER&=0xFFFF0FFF;// PD12,13,14,15
GPIOD>OSPEEDR&=0x00FFFFFF;//PD12,13,14,15 100m
GPIOD>OSPEEDR|=0xff000000;
SYSCFG>CMPCR=0x00000001;// IO
}
voidEXTI0_IRQHandler(void)
{
uint32_ttmp;
if(EXTI>PR&0x00000001!=0) // 0
{
tmp=(~GPIOD>ODR)&0x0000f000; //PD15141312 , LED
GPIOD>ODR&=0xffff0fff;
GPIOD>ODR|=tmp;
EXTI>PR=(1<<0); // 0
}
}
RM0090R
Referencema
anual
EXTI_IMR
31:223
22200 MRxx
x
0
x
1
x
EXTI_EMR
31:223
22200 MRxx
x
0
x
1
x
EXTII_RTSR
31:223
222:0 TRx x
EXTII_FTSR
31:223
222:0 TRx x
EXTI_SSWIER
31:223
222:0 SWIERxx
x
0 1
EXTI_P
PR
EXTI_IMR EXTTI_EMR
EXTI_PR 1
EXTTI_PR
31:223
222:0 PRx
0
1SYSC
CFG_EXTICR[11]
31:116
115:0EXTIx[3:0
0]EXTI
XX=033
EXTIx
00000:PA[x]pin
00011:PB[x]pin
00100:PC[x]pin
00111:PD[x]pin
01000:PE[x]pin
01011:PF[C]pin
01100:PG[x]pin
01111:PH[x]pin
10000:PI[x]pin
2 SYSSCFG_EXTICR
R2
3 SYSSCFG_EXTICR
R3
4 SYSSCFG_EXTICR
R4
USART
STM32F407xx /USART1USART2USART3 USART6

UART4 UART5 6 IrDA SIR ENDEC
LIN / USART1 USART6
10.5Mbit/s 5.25bit/sUSART1USART2USART3
USART6 CTSRTS ISO7816 SPI
DMA
USART
Standard
Modem
SPI
LIN
name
features
(RTS/CTS)
Max.baudrate
Max.baudrate
Smartcard
inMbit/s
inMbit/s
APB
(ISO7816)
(oversampling
(oversampling
mapping
by16)
by8)
irDA
master
APB2
USART1
5.25
10.5
(max.84
MHz)
APB1
USART2
2.62
5.25
(max.42
MHz)
APB1
USART3
2.62
5.25
(max.42
MHz)
APB1
UART4
2.62
5.25
(max.42
MHz)
APB1
UART5
2.62
5.25
(max.42
MHz)
APB2
USART6
5.25
10.5
(max.84
MHz)
USART APB USART_BRR USART_BRR

32 16 16 [15:4][3:0][15:4]
[2:0] OVER8 [15:4] USARTDIV [3:0][2:0]
USART =
fck
8 (2 OVER 8) USARTDIV
USARTDIV 16 8 USART_BRR[3:0][2:0]
115200
115200=
fck
42M
=
8 (2 OVER 8) USARTDIV
8 (2 0) USARTDIV
OVER8=0
USARTDIV=22.768
USART_BRR[15:4]=22=0x16
USART_BRR[3:0]=0.768*16=13=0xC
USART_BRR=0x0000016C
1.
2.
3.
4. CR
5. GPIO
6. GPIO
7. GPIO
8. USART
9. USART
10.
11.
12.

/*********************************************
USART
IARforARM6.21
stm32f4discovery
168M
author
data20120201
**********************************************/
u8suffer[100];
u8ok_to_send;
u8Rx_data_counter;
voidmain()
{
charTx_data_counter;
SCB>AIRCR=0x05AF0000|0x400; // =3:1
RCC>AHB1ENR|=0x00000008;// GPIOD
RCC>APB1ENR|=(1<<18); // usart3
USART3>BRR=0x0000016C; // 115200
/*
usart3
usart3
usart3

8bit

*/
USART3>CR1|=((1<<13)|(1<<3)|(1<<2)|(1<<5));
GPIOD>AFR[1]|=0x00000077;// PD8,9
GPIOD>MODER&=0xFFF0FFFF;// PD8,9,
GPIOD>MODER|=0x000A0000;
// GPIOD>OTYPER&=0xFFFFDFFF;// PD9
GPIOD>OSPEEDR&=0xFFFCFFFF;//PD8 50m
GPIOD>OSPEEDR|=0x00020000;
GPIOD>PUPDR&=0xFFFCFFFF;//PD8
GPIOD>PUPDR|=0x00010000;
NVIC>IP[39]=0xf0;// 1111
NVIC>ISER[1]|=(1<<(3932));// 39 usart3
while(1)
{
if(ok_to_send) //
{
if((USART3>SR&(1<<7)))//
{
USART3>DR=suffer[Tx_data_counter];
Tx_data_counter++;
if(suffer[Tx_data_counter]=='\0')
{
Tx_data_counter=0;
USART3>CR1|=1<<5; //
ok_to_send=0;
}
}
}
}
}
voidUSART3_IRQHandler(void)
{
if(USART3>SR&(1<<5))//
{
suffer[Rx_data_counter]=USART3>DR;
Rx_data_counter++;
if(suffer[Rx_data_counter1]=='\0')
{
Rx_data_counter=0;
USART3>CR1&=~(1<<5);//
ok_to_send=1;
}
}}
}
RM0090R
Referencema
anual
USA
ART_SR
331:10

99CTSCTS
NCTS
CTSE
USART
T_CR3
CCTSIE=1
0NNCTS
1 NCTS
UART4 UART5
88LBDLIN
LIN
USA
ART_CR2
LBDIE= 1
0
LIN
L
1
LIN
LBDIE==1 LBD= 1
1
77TXE
TDR
USART_CR11 TXEIE
T
1
USART__DR
66 TC
TXE
USART__CR1 TCIE=1
1. USART_SR
R
2. USART_DR
'0'
0
5RXNE
RDR USART_DR USART_CR1
RXNEIE=1
USART_DR RXNE 0
0
1
4IDLE
USART_CR1 IDLEIE=1
1. USART_SR
2. USART_DR
0
1
RXNE
3 ORE
RXNE=1 RDR
USART_CR1 RXNEIE=1
1. USART_SR
2. USART_DR
0
1
RDR EIE
ORE
2NF 1
1. USART_SR
2. USART_DR
0
1
RXNE EIE
NF
NF ONEBIT 1
1 FE
1. USART_SR
2. USART_DR
RXNE
EIEE
FE
0 PE
USART__DR
PE
RXNE
US
SART_CR1 PEIE=1
USART_BRR
U
331:16

115:4 DIV_Mantissa[11:0]USARTD
DIV
112 USART
( USARTDIV)
33:0 DIV_Fracttion[3:0]USSARTDIV
4 USART
U
(U
USARTDIV)
OVER8=1 D
DIV_Fraction[3
3]
0
1USSART_CR1
31:16
15 OVER8
016
18
8 IrDA LIN
SCEN= 1IREN=1 LINEN = 1 OVER8 0
14
13 UE USART
USART
0USART
1USART
12 M : (Word length)
08n
19 n
11: WAKE (Wakeup method)
USART
0
1
10 PCE (Parity control enable)
(
)(M=19M=0
8)10
0
1
9 PS (Parity selection)
1 0
0
1
8 (PE interrupt enable)
0
1 USART_SR PE 1 USART
7 TXEIE (TXE interrupt enable)
0
1 USART_SR TXE 1 USART
6 TCIE (Transmission complete interrupt enable)
0
1 USART_SR TC 1 USART
5 RXNEIE (RXNE interrupt enable)
0
1 USART_SR ORE RXNE 1 USART
4 IDLEIEIDLE (IDLE interrupt enable)
0
1 USART_SR IDLE 1 USART
3 TE (Transmitter enable)
0
1
1 TE 0( 0
1)()
2 TE
2 RE (Receiver enable)
0
1 RX
1 RWU (Receiver wakeup)
USART
0
1
1 USART ( RWU )USART
2(WAKE =1) RXNE RWU
0 SBK
(S
Send break))
2USSART_CR2
331:15
114 LINENLIN
(LINmoddeenable)

0
LIN

1
LIN

LLIN USART_CR1
SBK LIN (( 13 )
LIN
113:12 STOP
P (STOPbits)
2

001
010.5

102
111.5

UART4 UART5
1.5
U
0.5

111 CLKEN (Clockenablee)
CK
0
CK

1
CK

UART4 UART5
U
110 CPOL (C
Clockpolarityy)
SLCK
CPHA

0
CK

1
CK

UART4 UART5
U
99 CPHA
(Clockphase)
SLCK
CPOL
( 2599 260) 544/754

0

UART4 UART5
U
8 LBCL
(Lastt bit clock

k pulse)
CCK
(MSB)
CK
1
CK
8 9
(
USART_CR1
M
8
9 )
2UUART4 UARRT5
6 LBDIELLIN
(LIN brea
ak detectio
on interruppt enable)
)
0
1
USART_SR LBD 1
5 LBDLLIN
(LINN break det
tection len
ngth)
11 10
1
0110
1111
4
33:0 ADD[3:0]
USART
USART
USAART
3USSART_CR3
31:12
11ONEBIT
NF
03
1
10CTSIECTS (CTS interrupt enable)
0
1USART_SR CTS 1
UART4 UART5
9 CTSECTS (CTS enable)
0 CTS
1CTS nCTS ()
nCTS nCTS
nCTS
UART4 UART5
8 RTSERTS (RTS enable)
0 RTS
1RTS
nRTS ()
UART4 UART5
7 DMATDMA (DMA enable transmitter)
0 DMA
1 DMA
UART4 UART5
6 DMAR: DMA (DMA enable receiver)
0 DMA
1 DMA
UART4 UART5
5 SCEN: (Smartcard mode enable)
0
1
UART4 UART5
4 NACK
NACK
(Smarttcard NACK enable)
0
NACK
1
NACK
N
UART4 UAART5
3 HDSEL (Half-dupllex selecti

ion)
2 IRLP
(IrDA low-ppower)
1 IREN
(IrDA modde enable)
0 EIE (Error intterrupt ena

able)
(USAR
RT_SR FEE=1 OR
RE=1
NE=1)
0
1
USART_CR3 DMA
AR=1 UUSART_SR
FE=1
ORE=1
NE=1
USART_GTPR
R
311:16
155:8 GT[77:0]
(Guarrd time val
lue)
UART4UARRT5
7:0 PSC[7:0] (Prescaler value)

- (IrDA)
PSC[7:0]=
(8)
00000000
000000011
000000102
- (IrDA)PSC00000001
-
PSC[4:0]
(5)2
00000
000012
000104
000116
1[7:5]
2UART4UART5
DMA
DMA
CPU DMA CPU
DMA AHB
FIFO
DMA 16 stream
DMA
1.
2. burst
DMA
1. ADC
DMA_SxCR CIRC
burst
DMA_SxNDTR ((Mburst beat) (Msize)/(Psize))
2. DMA_SxCR DBM
DMA
DMA_SxCR CT 0 DMA_SxM1AR
DMA_SxCR CT 1 DMA_SxM0AR

1.
2. DMA_SxCR EN
0
EN 0
EN
DMA DMA_LISR and
DMA_HISR
3. DMA_SxPAR
4. DMA_SxMA0R
DMA_SxMA1R
5. DMA_SxNDTR burst
6. DMA_SxCR CHSEL[2:0] DMA

7.
DMA_SxCR PFCTRL
8. DMA_SxCR PL[1:0]
9. FIFO
10. DMA_SxCR /
burst
11. DMA_SxCR EN
12. DMA

/*********************************************
DMA
IARforARM6.21
stm32f4discovery
168M

USART3 DMA
author
data20120203
**********************************************/
u8USART_DMA_Completed;
u8Rx_Completed;
u8Rx_data_counter;
u8usart3_buffer[100];
voidUSART3_DMA_config(void);
voidUSART3_config(void);
voidmain()
{
SCB>AIRCR=0x05AF0000|0x400; // =3:1
RCC>AHB1ENR|=((1<<3)|(1<<21));// GPIOD , DMA1

USART3_DMA_config();
USART3_config();
USART_DMA_Completed=1;
while(1)
{
if(USART_DMA_Completed & Rx_Completed) //
{
DMA1_Stream3>CR&=0xFFFFFFFE;// DMA1_Stream3
while(DMA1_Stream3>CR&0x00000001);// DMA
DMA1>LIFCR|=0x0f800000;// DMA1_Stream3
DMA1_Stream3>NDTR=Rx_data_counter;// dma
if((USART3>SR&(1<<7)))//
{
USART3>CR3&=~(1<<7);// usartdma
DMA1_Stream3>CR|=1;// dma
USART3>CR3|=(1<<7);// usartdma
Rx_Completed=0;
Rx_data_counter=0;
}
}
}
}
/****************************************
USART3_DMA_config

DMA1 3 usart3
****************************************/
voidUSART3_DMA_config(void)
{
DMA1_Stream3>PAR = (uint32_t)&USART3>DR;// USART3>DR

0x40004804
DMA1_Stream3>M0AR=(uint32_t)usart3_buffer;//
//DMA1_Stream3>FCR|=0x00000007;// fifo
/*
dma 4 usart3tx
Medium

*/
DMA1_Stream3>CR|=(0x08000000|0x00010000|(1<<6)
|(1<<10)|(1<<4));
USART3>CR3&=~(1<<7);//usart3dma

NVIC>IP[14]=0xA0;
NVIC>ISER[0]|=(1<<14);
/**************************
USART3_config

usart3
************************/
voidUSART3_config(void)
{
USART3>BRR=0x0000016C; // 115200
/*
usart3
usart3
usart3

8bit

*/
USART3>CR1|=((1<<13)|(1<<3)|(1<<2)|(1<<5));
GPIOD>AFR[1]|=0x00000077;// PD8,9
NVIC>IP[39]=0xf0;// 1111
NVIC>ISER[1]|=(1<<(3932));// 39 usart3
}
voidUSART3_IRQHandler(void)
{
if(USART3>SR&(1<<5))//
{
usart3_buffer[Rx_data_counter]=USART3>DR;
Rx_data_counter++;
if(usart3_buffer[Rx_data_counter1]=='\0')
{
USART3>CR1&=~(1<<5);//
Rx_Completed=1;
}
}
}
voidDMA1_Stream3_IRQHandler(void)
{
if(DMA1>LISR&0x08000000)//DMA
{
USART3>CR1|=1<<5; // usart3
DMA1>LIFCR|=0x08000000;//
}
}
RM0090R
Referencema
anual
DMA
A
DM
MA_LISR
331:2815:12
2
227, 21, 11, 5 TC

CIFx
x
X=3..0
1 DMA_LIFCR
0
x
1
x
226, 20, 10, 4 HTIFx

H
x
X=3..0
1 DMA_LIFCR
0
x
1
x
225, 19, 9, 3 TEIFx

x
X=3..0
1 DMA_LIFCR
0
x
1
x
224, 18, 8, 2 DMEIFx

x
X =3..0
1 DMA_LIFCR
0
x
1
x
2231771
222, 16, 6, 0 FEIFx

xFIFO
X=3..0
1 DMA_LIFCR
0
x FIFO
1
x
FIFO
DMA
A
DM
MA_HISR
331:2815:12
2
227, 21, 11, 5 TC

CIFx
x
X=3..0
1 DMA_LIFCR
0
x
1
x
226, 20, 10, 4 HTIFx

H
x
X=3..0
1 DMA_LIFCR
0
x
1
x
225, 19, 9, 3 TEIFx

x
X=3..0
1 DMA_LIFCR
0
x
1
x
224, 18, 8, 2 DMEIFx

x
X =3..0
1 DMA_LIFCR
0
x
1
x
2231771
222, 16, 6, 0 FEIFx

xFIFO
X=3..0
1 DMA_LIFCR
0
x FIFO
1
x
FIFO
DMA
A
DMA_LIFCR
R
331:2815:12
227, 21, 11, 5 CTCIFx
X = 3.. 0
1
DMA_LLISR
TCIFFx
226, 20, 10, 4 CHTIFx
x
X = 3..0
1
DMA_LLISR
HTIFFx
225, 19, 9, 3 CTEIFx
x
X = 3..0
1
DMA_LLISR
TEIFFx
224, 18, 8, 2 CDMEIFx
x
X = 3...0
1
DMA_LLISR
DMEIIFx
2231771
222, 16, 6, 0 CFEIFx

x FIFO
X = 3..0
1
DMA_LLISR
FEIFFx
DMA
A
DMA_LIFCR
R
331:2815:12
227, 21, 11, 5 CTCIFx
X = 3.. 0
1
DMA_LLISR
TCIFFx
226, 20, 10, 4 CHTIFx

x
X = 3..0
1
DMA_LLISR
HTIFFx
225, 19, 9, 3 CTEIFx
x
X = 3..0
1
DMA_LLISR
TEIFFx
224, 18, 8, 2 CDMEIFx
x
X = 3...0
1
DMA_LLISR
DMEIIFx
2231771
222, 16, 6, 0 CFEIFx

x FIFO
X = 3..0
1
DMA_LLISR
FEIFFx
DMA
A X
DMA_SxCR
D
331:28
227:25 CHSELL[2:0]
000
0
001
1
010
2
011
3
100
4
101
5
110
6
111
7
EN 0
24:23MBURST burst
00
01INCR4 4
10INCR8 8
11INCR16 16
EN 0
0x0 EN=1
22:21 PBURST burst
00
01INCR4 4
10INCR8 8
11INCR16 16
EN 0
0x0 EN=1
20
19 CT
0 0 DMA_SxM0AR
1 1 DMA_SxM1AR
EN 0
18DBM
0
1 DMA
EN 0
17:16 PL[1:0]
00
01
10
11
EN 0
15 PINCOS
0 PSIZE
1 4 32
PINC= 0
EN= 0
PBURST 00 EN= 1
14:13 MSIZE[1:0]
008
0116
10 32
11
EN 0
MSIZE PSIZE EN=1
12:11PSIZE[1:0]
008
0116
10 32
11
EN 0
10 MINC
0
1 MSIZE
EN 0
9 PINC
0
1
EN 0
8 CIRC
0
1
7:6DIR[1:0]
00
01
10
11
EN 0
5 PFCTRL
0DMA
1
EN 0
DIR[1:0]=10
0
4 TCIE
0TC
1TC
3HTIE
0 HT
1HT
2TEIE
0TE
1TE
1DMEIE
0DME
1DME
0EN/
0
1
DMA
AHB
AHB FIFO
DMA x DMA_SxNDTR
331:16
115:0NDT[15:0
0]
0 65535
DMA
DMA
A x
DMA_SxxPAR
DMA
A x
0
DMA__SxM0AR
DMA
A x
1
DMA__SxM1AR
DMA
A xFIFO
DMA_SxxFCR
331:8
7 FEIE
0
FE
1FFE
55:3 FS[2:0]FIFO
000
0<fifo_leveel<1/4
001
1/4fifo_level<1/2
0101/2fifo_level<3/4
0113/4fifo_level<
100FIFO
101FIFO
DMDIS
2DMDIS
0
1
EN 0
DMA_SxCR DIR 10 DMA_SxCR EN
'1'
1:0FTH[1:0]FIFO
00 FIFO 1/4
01 FIFO 1/2
10 FIFO 3/4
11 FIFO
DMIS
EN 1
M
MyDebu
ugger
usart DM
MA

MyDebugg
ger
USAR
RT
DMA
DMA USART3_DMA_conffig()
MyD
Debugger_Meessage(char*
*str_address,,unsignedinttstr_len)
MyDebugger
M
USAR
RT3
MyDeb
bug_with_USSART3
MyDebugger
/*********************************************
MyDebugger
IARforARM6.21
stm32f4discovery
168M
author
data20120204
**********************************************/
#include<stdbool.h>
/******LED *******/
#definegreen0x00001000
#defineorange0x00002000
#definered0x00004000
#defineblue0x00008000
/*************/
boolUSART_DMA_Completed;
enumLED_State{on,off,turn};
/*************/
voidLEDs_Init(void);
voidUSART3_DMA_config(void);
voidUSART3_config(void);
boolMyDebugger_Message(char*str_address,unsignedintstr_len);
voidMyDebugger_LEDs(uint32_tLED,enumLED_Statestate);
voidmain()
{
SysTick_Config(SystemCoreClock/1000);// systemtick
SCB>AIRCR=0x05AF0000|0x400; // =3:1
LEDs_Init();
USART3_config();
while(1)
{
MyDebugger_Message("MynameisXianYongwen\n",
sizeof("MynameisXianYongwen\n")/sizeof(char));
MyDebugger_Message("\n",
sizeof("\n")/sizeof(char));
}
}
/*********************************************
MyDebugger_Message
char*str_address
unsignedintstr_len
bool
USART3
**********************************************/
boolMyDebugger_Message(char*str_address,unsignedintstr_len)
{
if(USART_DMA_Completed) //
{
DMA1_Stream3>CR&=0xFFFFFFFE; // DMA1_Stream3
DMA1>LIFCR|=0x0f800000; // DMA1_Stream3
DMA1_Stream3>M0AR=(uint32_t)str_address;//
if((USART3>SR&(1<<7)))//
{
DMA1_Stream3>NDTR=str_len;// dma
USART3>CR3|=(1<<7);//usart3dma
returntrue;
}
}
returnfalse;
}
/****************************************
MyDebugger_LEDs
uint32_tLED LED
enumLED_Statestate

LED
****************************************/
voidMyDebugger_LEDs(uint32_tLED,enumLED_Statestate)
{
uint32_ttmp;
switch(state)
{
caseon:
{
GPIOD>BSRRL|=LED;
break;
}
caseoff:
{
GPIOD>BSRRH|=LED;
break;
}
caseturn:
{
tmp=(~GPIOD>ODR)&LED;
GPIOD>ODR&=~LED;
GPIOD>ODR|=tmp;
break;
}
}
}
/****************************************
USART3_DMA_config

DMA1 3 usart3
****************************************/
{
RCC>AHB1ENR|=(1<<21);// DMA1

0x40004804
//
DMA1_Stream3>FCR&=0x00000000;
DMA1_Stream3>FCR|=(1<<7);// fifo
/*
dma 4 usart3tx

*/
DMA1_Stream3>CR|=(0x08000000|0x00030000|(1<<6)
|(1<<10)|(1<<4)|(1<<2)|(1<<1));
NVIC>IP[14]=0xA0;
NVIC>ISER[0]|=(1<<14);
/**************************
USART3_config

usart3
************************/
{
USART3>BRR=0x0000016C; // 115200
/*
usart3
usart3
8bit

*/
USART3>CR1|=((1<<13)|(1<<3));
GPIOD>AFR[1]|=0x00000077;// PD8,9
/****************************************
LEDs_Init

LED
****************************************/
voidLEDs_Init(void)
{
}
{
{
DMA1>LIFCR|=0x08000000;//
}
if(DMA1>LISR&0x03000000) // LED
{
MyDebugger_LEDs(orange,on);
DMA1>LIFCR|=0x03000000;
}
if(DMA1>LISR&(1<<22)) // fifo
{
MyDebugger_LEDs(red,on);
DMA1>LIFCR|=(1<<22);
}
}

MyDebugger.h
//file:MyDebugger.h
#ifndef__MyDebugger_H
#define__MyDebugger_H
#include<stdbool.h>
/******LED *******/
#definegreen0x00001000
#defineorange0x00002000
#definered0x00004000
#defineblue0x00008000
/*************/
enumLED_State{on,off,turn};
/*************/
voidMyDebugger_Init(void);
boolMyDebugger_Message(char*str_address,unsignedintstr_len);
voidMyDebugger_LEDs(uint32_tLED,enumLED_Statestate);
#endif
C MyDebugger.c
//file:MyDebugger.c
#include<MyDebugger.h>
#ifdefMyDebug_with_USART3
boolUSART_DMA_Completed=true;
/****************************************
USART3_DMA_config

DMA1 3 usart3
****************************************/
{

0x40004804
//
DMA1_Stream3>FCR&=0x00000000;
DMA1_Stream3>FCR|=(1<<7);// fifo
/*
dma 4 usart3tx

*/
DMA1_Stream3>CR|=(0x08000000|0x00030000|
(1<<6)|(1<<10)|(1<<4));
NVIC>IP[14]=0xA0;
NVIC>ISER[0]|=(1<<14);
}
/**************************
USART3_config

usart3
************************/
{
USART3>BRR=0x0000016C; // 115200
/*
usart3
usart3
8bit

*/
USART3>CR1|=((1<<13)|(1<<3));
GPIOD>AFR[1]|=0x00000077;// PD8,9
}
{
{
DMA1>LIFCR|=0x08000000;//
}
}
#endif
/*********************************************
MyDebugger_Message
char*str_address
unsignedintstr_len
bool
USART3
**********************************************/
boolMyDebugger_Message(char*str_address,unsignedintstr_len)
{
#ifdefMyDebug_with_USB
boolUSB_Actioned;
#endif
boolUSART3_Actioned;
if(USART_DMA_Completed) //
{
DMA1_Stream3>CR&=0xFFFFFFFE; // DMA1_Stream3
DMA1>LIFCR|=0x0f800000; // DMA1_Stream3
DMA1_Stream3>M0AR=(uint32_t)str_address;//
if((USART3>SR&(1<<7)))//
{
DMA1_Stream3>NDTR=str_len;// dma
USART3>CR3|=(1<<7);//usart3dma
USART3_Actioned=1;
}
}
#endif
// USB
// USB
USB_Actioned=1;
#endif
#ifndefMyDebug_with_USB
returnUSART3_Actioned;
#endif
#endif
#ifndefMyDebug_with_USART3
returnUSB_Actioned;
#endif
#endif
return(USART3_Actioned|USB_Actioned);
#endif
#endif
}
/****************************************
LEDs_Init

LED
****************************************/
voidLEDs_Init(void)
{
}
/****************************************
MyDebugger_LEDs
uint32_tLED LED
enumLED_Statestate

LED
****************************************/
voidMyDebugger_LEDs(uint32_tLED,enumLED_Statestate)
{
uint32_ttmp;
switch(state)
{
caseon:
{
GPIOD>BSRRL|=LED;
break;
}
caseoff:
{
GPIOD>BSRRH|=LED;
break;
}
caseturn:
{
tmp=(~GPIOD>ODR)&LED;
GPIOD>ODR&=~LED;
GPIOD>ODR|=tmp;
break;
}
}
}
/*********************************************
MyDebugger_Init

MyDebugger
**********************************************/
voidMyDebugger_Init(void)
{
LEDs_Init();
USART3_config();
#endif
}
main.c
//main.c
/*********************************************
MyDebugger
IARforARM6.21
stm32f4discovery
168M
author
data20120204
**********************************************/
#include<MyDebugger.h>
voidmain()
{
SCB>AIRCR=0x05AF0000|0x400; // =3:1
MyDebugger_Init();
while(1)
{
MyDebugger_Message("MynameisXianYongwen\n",
sizeof("MynameisXianYongwen\n")/sizeof(char));
MyDebugger_LEDs(blue,on);
MyDebugger_Message("\n",
sizeof("\n")/sizeof(char));
}
}
t rue
TIM6&TIM7
TIM6 TIM7 16
DAC
DAC
1.
2.
3.
4.
5.
6.
7.
8.

/************************************
TIM7
IARforARM6.21
stm32f4discovery
168M
author
data20120206
*************************************/
#include"MyDebugger.h"
voidmain()
{
SCB>AIRCR=0x05AF0000|0x400; // =3:1
RCC>APB1ENR|=(1<<5);// TIM7
TIM7>PSC=8399;// 84M 8400 10k
TIM7>ARR=10000; //
TIM7>CNT=0; //
TIM7>CR1|=(1<<7);//
TIM7>DIER|=1;//
NVIC>IP[55]=0x80;
NVIC>ISER[1]|=(1<<(5532));
TIM7>CR1|=1;//
MyDebugger_Init();
while(1)
{
};
}
voidTIM7_IRQHandler(void)
{
if(TIM7>SR)
{
MyDebugger_LEDs(blue,turn);
TIM7>SR&=~(0x0001);
}
}
RM0090R
Referencema
anual
TIM6&TIM7
1TIIMx_CR1
115:8
77ARPE

0TTIMx_ARR
1TTIMx_ARR
66:4
33OPM 3

0
( CEN
C )
22URS
UEV
DMA
DMA

UG

DMA
D
DMA
11UDIS
UEV
0U
UEV
(UEV
V)

UG

1
UEV
(UEV)
(ARRPSC))
U
UG
00CEN

0

1

CE N
CEN

CEN
TIM6&TIM7
2TIIMx_CR2
115:7
66:4MMS

(TRGO)

000

(

TIMx_EG
GR UG
(TRG
GO)
TRGO

001

CNT_EN
(TRGO
O)

CEN
TRG
GO
/
( TIMx__SMCR MSM )
010

(TRGO)
TIM6&TIM7DMA
A
TIMx__DIER
115:9
88UDE:
DMA

0
DM
MA
1
DM
MA
77:1
00UIE
TIM6&TIM7
TIM
Mx_SR
115:1
00UIF
TIMx_CR11 UDIS=
=0

TIMx_CR
R1 URS=
=0 UDIS =0 TIMx_EGR
UG
CNT
TIM6&TIM7
TIMx_EGR
115:1
00UG
0

1
TIM6&TIM7
TIMx_C
CNT
TIM6&TIM7
TIMx_PSC
115:0PSC[15:0
0]
CK_CNT
fCK_PSCC/(PSC[15:0]+
+1)
PSC
TIM6&TIM7
TIMx_ARR
R
115:0ARR[15:0
0]

ARR

TIM2toTIM5 16 32
PWM RCC
TIMx
1. 16 TIM3 TIM4 32 TIM2 TIM5/
2. 16 1 65535
3. 4

PWM

4.
5. /DMA
//
/

6.
7.
RM0090R
Referencema
anual
1TIMx_CR1
115:10

99:8CKD[1:0]:
(CK_INT)
(ETRTIx)
00tDTS=tCK_INT
01tDTS=2xtC
CK_INT
10tDTS=4xtC
CK_INT
11
77ARPE

0TTIMx_ARR
1TTIMx_ARR
66:5CMS[1:0]

00
(DIR)

01
1
(TTIMx_CCMRx CCCxS=00)
10
2
11
3

(CEN=1)
44DIR
0
33OPM 3

0
( CEN
C )
22URS
UEV
DMA
DMA

UG

DMA
D
DMA
11UDIS
UEV
0U
UEV
(UEV
V)

UG

1
UEV
(UEV)
(ARRPSC))
U
UG
00CEN

0

1

CE N
CEN

CEN
2TIMx_CR2
115:8
77TI1STII1
0TTIMx_CH1 TI1
1TTIMx_CH1TTIMx_CH2 TIMx_CH3
TI1
66:4MMS

(TRGO)

000

(

TIMx_EG
GR UG
(TRG
GO)
TRGO

001

CNT_EN
(TRGO
O)

CEN
TRG
GO
/
( TIMx__SMCR MSM )
010

(TRGO)
011

CC
C1IF (
)
(TRGO)
100
OC
C1REF
(TRGO)
101
OC
C2REF
(TRGO)
110
OC
C3REF
(TRGO)
111
OC
C4REF
(TRGO)
33CCDS
/ DMA
D
0
CCx
CCx DM
MA
1
CCx DM
MA
TIMx_SM
MCR
77MSM/
0

1
(TR
RGI)
(
TRGO)
66:4TS[2:0]

000
001
1(ITR1)
010
2(ITR2)
011

100
TI1
(TI1FF_ED)
101
1(TI1FP1)
1
110
2(TI2FP2)
2
111
(ETRF)
(
SMS=000)
22:0SMS[2:0]
(TRGI)
((
000
CE
EN=1

001
1 TI1FP1
T
TI2FP2
/

010
2 TI2FP2
T
TI1FP1
/
011
TI1FP1
T
TI22FP2
/

100

(TRG I)

101

(TRGI)
(
)

110

TR
RGI
(
)

111
(TRGI)

TI1F_EEN
(TS=1000)
TI1F_ED
TTI1F
DMA
A
TIMx_
_DIER
115
114TDE
DMA
0
DM
MA
1
DM
MA
112CC4DE
/
4 DMA
0
/
4 DMA
A
1
/
4 DMA
A
111CC3DE
/
3 DMA
0
/
3 DMA
A
1
/
3 DMA
A
110CC2DE
/
2 DMA
0
/
2 DMA
A
1
/
2 DMA
A
99CC1DE
/
1 DMA
0
/
1 DMA
A
1
/
1 DMA
A
88UDE
DMA
A
0
DMA
1
DMA
66TIE

0
44CC4IE
/ 4
0
/
4
1
/
4
33CC3IE
/ 3
0
/
3
1
/
3
22CC2IE
/ 2
0
/
2
1
/
2
11CC1IE
/ 1
0
/
1
1
/
1
00UIE

0
TIM
Mx_SR
112CC4OF
/ 4
111CC3OF
/ 3
110CC2OF
/ 2
99CC1OF
/ 1

1
00

0
TIMx_CCR1
T
C
CC1IF 1
66TIF

TRGI
1
0
0
44CC4IF
/ 4
33CC3IF
/ 3
22CC2IF
/ 2
11CC1IF
/ 1
CC1
(
TIMx_CR
R1 CMS )
0
0

1TTIMx_CNT
TIMx_C
CCR1

CC1
1
0
TIMxx_CCR1 0
0
()) TIMx_CCR
R1( IC1
00UIF
1
0
0
1
TIMx_CR1
UD
DIS=0URS==0 TIMx_
_EGR
UG=1
CNTT
)
TIMx_CR1
UD
DIS=0URS=00
CNT
TIMx_EGR
115:7
66TG
0
0

1TTIMx_SR
TIF=1
DMA
D
DMA
44CC4G
/ 4
33CC3G
/ 3
22CC2G
/ 2
11CC1G
/ 1

1
/
0
0

1
CC1
CC1

CC1IF=1
DM
MA
DMA
CC1

TIMxx_CCR1
CC
C1IF=1
DMA
DMA CC1IF
C
1 CC1OF=1
00UG
10
0

1
0(
DIR=0(
)
0 DIR=1(
D
)
TIMx_AR
RR
/
1TIM
Mx_CCMR1
(
)( ) CCCxS
OCxx
ICxxx
115OC2CE
2 0
114:12OC2M[2
2:0]
2
111OC2PE
2
110OC2FE
2
99:8CC2S[1:0]/
2
(/
)

00CC2

01CC2
IC2
TI2
10CC2
IC2
TI1
11C
CC2
IC2 TTRC
TIMx_SMCR TS )
CC2S (TIMx_CCER CC2E=0)
7OC1CE 1 0
0OC1REF ETRF
1 ETRF OC1REF=0
6:4OC1M[2:0] 1
3 OC1REF OC1REF OC1 OC1REF
OC1 CC1P
000
TIMx_CCR1 TIMx_CNT OC1REF
001 1
TIMx_CNT / 1(TIMx_CCR1) OC1REF
010 1
TIMx_CNT / 1(TIMx_CCR1) OC1REF
011
TIMx_CCR1=TIMx_CNT OC1REF
100
OC1REF
101
OC1REF
110PWM 1
TIMx_CNT<TIMx_CCR1 1
TIMx_CNT>TIMx_CCR1 1 (OC1REF=0)
(OC1REF=1)
111PWM 2
TIMx_CNT<TIMx_CCR1 1
TIMx_CNT>TIMx_CCR1 1
1 LOCK 3(TIMx_BDTR LOCK ) CC1S=00(
)
2 PWM 1 PWM 2
PWM OC1REF
3OC1PE 1
0 TIMx_CCR1 TIMx_CCR1

1 TIMx_CCR1 TIMx_CCR1

1 LOCK 3(TIMx_BDTR LOCK ) CC1S=00(
)
2(TIMx_CR1 OPM=1)
PWM
2OC1FE 1
CC
0 CCR1 CC1
CC1 5
1OC
CC1 3
PWM1 PWM2
1:0CC1S[1:0]/ 1
2 (/)
00CC1
01CC1 IC1 TI1
10CC1 IC1 TI2
11CC1 IC1 TRC
( TIMx_SMCR TS ) CC1S
(TIMx_CCER CC1E=0)
15:12 IC2F[3:0]2
N
0000 fDTS
0001 fSAMPLING=fCK_INTN=2
0100 fSAMPLING=fDTS/2N=6
ICxF[3:0]=12 3 fDTS CK_INT
11:10 IC2PSC[1:0]/2
2 CC1 (IC1) CC1E=0(TIMx_CCER )
00
01 2
10 4
11 8
9:8 CC2S[1:0]/ 2
2 (/)
00CC2
01CC2 IC2 TI2
10CC2 IC2 TI1
11CC2 IC2 TRC
( TIMx_SMCR TS )
CC2S (TIMx_CCER CC2E=0)
7:4 IC1F[3:0] 1
TI1
N
0000 fDTS
ICxF[3:0]=12 3 fDTS CK_INT
3:2 IC1PSC[1:0]/ 1
2 CC1 (IC1) CC1E=0(TIMx_CCER )
00
01 2
10 4
11 8
1:0 CC1S[1:0]/ 1
2 (/)
00CC1
01CC1
IC1
TI1
10CC1
IC1
TI2
11CC1
IC1
TRC
( TIMx_
_SMCR
TS
) CC1S
(TIMx_CCER
R CCC1E=0)
/
2 TIM
Mx_CCMR2
/
TIMx
x_CCER
115CC4NP
/ 4
CC1NP
113 CC4P
/ 4
CC1P
112 CC4E
/ 4
CC1E
113 CC3NP/ 3
CC1NP
99 CC3P
/ 3
CC1P
88 CC3E/ 3
CC1E
77 CC2NP
/ 2
CC1NP
55 CC2P
/ 2

CC1P
44 CC2E/ 2
CC1E
33 CC1NP
/ 1
CC1
CC
C1NP
CC1
CC1P
TI1FP1/TTI2FP1
CC1P
11 CC1P
/ 1
CC1
0O
OC1
1O
OC1
CC1
CC1N
NP/CC1P TI11FP1 TI2FP1
00/
TTIxFP1
TIxFP1
01/
TTIxFP1
TIxFP1
10
11/
TIxFP1
TIxFP1
00 CC1E/ 1
CC1
0
OC1
1
OC1
CC1
TI Mx_CCR1
0

1

TIMx_CN
NT
TIMx_PSSC
115:0PSC[15:0
0]
CK_CNT
fCK_PSCC/(PSC[15:0]+
+1)
PSC
TIMx_ARR
115:0ARR[15:0
0]

ARR
/
1TIMx_CC
CR1
115:0CCR1[15:0]: / 1
CC1
CCR1
/
1
(
)
TIMx_CC
CMR1
(OC1PE )
/
1
TIM
Mx_CNT
OC
C1

C
CC1

CCR1
1 (ICC1)
/
2TIMx_CC
CR2
/
3TIMx_CC
CR3
/
4TIMx_CC
CR4
DMA
A
TIMx_DCR
12:8 DMA burst
(
TIMx_DMARR
0000001
0000012
0001103
....... ......
10000118
44:0 DBA[4:0]: DMA
DMMA burst
(
TIMx_DMAAR
) DBA
TIMx_CR1
000000TIMx_CRR1
000001TIMx_CRR2
000110TIMx_SMMCR
....... ......
DBL=7transfers&D
DBA=TIMx_C
CR1
TIMxx_CR1
......
DMA
A TIMxx_DMAR
115:0DMAB[15
5:0]:DMA

TTIMx_DMAR

(TIMx_CR1add
dress)+(DBA
A+DMAindexx)x4
TIMx_C
CR1
11(TIMx_CR1)
DBA TTIMx_DCR
DMA
DM
MA
TIM
Mx_DCR
DBL
DMA burst
DMA
Aburst
CCRx
C
D
DMA
X=234CCRx
1
DMA
DM
MA DMA
AR
DM
MA
RAM
CCRxx DMA
=3
2 DCR
DBA DBL
D
DBL=3transfers,DBA=0xE.
3
TIMx
DMA
D
DIER
UDE

4
TIMx
5
DMA
Notee:Thisexamp
pleisfortheccasewhereevveryCCRxreg
gistertobeup
pdatedonce..IfeveryCCRxx
regissteristobeu
updatedtwice
eforexamplee,thenumberrofdatatotrransfershoulldbe6.Let's
takeetheexampleeofabufferin
ntheRAMcoontainingdatta1,data2,da
ata3,data4,ddata5and
data
a6.Thedataiistransferred
dtotheCCRx registersasffollows:onth
hefirstupdateeDMA
requ
uest,data1istransferredttoCCR2,dataa2istransferrredtoCCR3,d
data3istranssferredto
CCR44andonthesecondupda
ateDMArequuest,data4istransferredttoCCR2,dataa5is
transferredtoCC
CR3anddata6
6istransferreedtoCCR4.
TIM2
TIM2_OR
111:10 ITR1__RMP
1
00: T
TIM8_TRGOU
UT
01PTP TIM
M2_ITR1
10: OTG FS SOFF TIM
M2_ITR1
11: OTG HS SOFF TIM2_ITR1
TIM5
TIM5_OR
77:6 TI4_RMP
P
4
00TIM5 4 GPIO
STM332F40x STM332F41x
01 LSI TIM55_CH4
10 LSE TIM55_CH4
11 RTTC
TIM55_CH4
PWM
TIMx_ARR TIMx_CCRx
PWM OCx PWM TIMx_CCMRx

OCxM 110PWM 1 111PWM 2
TIMx_CCMRx
OCxPE TIMx_CR1 ARPE
()
TIMx_EGR UG
OCx TIMx_CCER CCxP
TIMx_CCER CCxE OCx
TIMx_CCERx
1.
2.
3. TIM
4.
5. ARR =
(PSC + 1) ARR
TIMx
6.
7. CCMR PWM
8. =
9.
10.
11.
CCRx
ARR

/************************************
4 PWM
IARforARM6.21
stm32f4discovery
168M
author
data20120208
*************************************/
voidmain()
{
SCB>AIRCR=0x05AF0000|0x400; // =3:1
RCC>AHB1ENR|=(1<<2);// GPIOC
GPIOC>MODER|=0X000AA000;//pc6789
//
GPIOC>OSPEEDR|=0x000ff000;// 100m
GPIOC>PUPDR|=0x00055000;//
GPIOC>AFR[0]|=0x22000000;//pc6789 AF2
GPIOC>AFR[1]|=0x00000022;
TIM3>PSC=83;// 84M 84 1M
TIM3>ARR=10000; // 10ms
TIM3>EGR|=1;//
TIM3>CCMR1|=0x6060;//PWM 1
TIM3>CCR1=8000;// 80%
TIM3>CCR2=6000;// 60%
TIM3>CCR3=4000;// 40%
TIM3>CCR4=2000;// 20%
TIM3>CCER|=0x1111;//
TIM3>CCMR1|=0x0808;//
TIM3>CCMR2|=0x0808;

TIM3>CR1|=1;//
while(1)
{
};
}

PWM
PWM PWM
PWM CCER
BDTR
1.
2.
3. TIM
4.
(PSC + 1) ARR
TIMx
5. ARR =
6.
7. CCMR PWM
CCRx
8. = ARR
9.
10.
11.
12.

/************************************
PWM
IARforARM6.21
stm32f4discovery
168M
PWM PWM
PE8TIM1_CH1N
PE9TIM1_CH1
PE10TIM1_CH2N
PE11TIM1_CH2
PE12TIM1_CH3N
PE13TIM1_CH3
PE14TIM1_CH4
author
data20120209
*************************************/
voidmain()
{
SCB>AIRCR=0x05AF0000|0x400; // =3:1
RCC>AHB1ENR|=(1<<4);// GPIOE
GPIOE>MODER|=0X2AAA0000;//PE891011121314
//
GPIOE>OSPEEDR|=0x3fff0000;// 100m
GPIOE>PUPDR|=0x15550000;//
//PE891011121314 AF1
GPIOE>AFR[1]|=0x01111111;
TIM1>PSC=167;// 168M 168 1M
TIM1>ARR=10000; // 10ms
TIM1>EGR|=1;//
TIM1>CCR1=8000;//
TIM1>CCR2=6000;
TIM1>CCR3=4000;
TIM1>CCR4=2000;
TIM1>CCER|=0x1ddd;//
TIM1>CCMR1|=0x0808;//
TIM1>CCMR2|=0x0808;
TIM1>BDTR|=1<<15; // 1
TIM1>BDTR|=0xCD; //
TIM1>CR1|=1;//
while(1)
{
};
}
DAC
Stm32f4 DAC 12 DAC 8
12 DMA DAC 12
DAC 2 DAC
2 2 DAC
VREF+
2 DAC 1
8 12
12
DAC
DMA
VREF+
1. GPIOPA45
2. TIMx TIMx
3. DAC
4. DMA
5. DMA DMA

/************************************
DAC
IARforARM6.21
stm32f4discovery
168M
author
data20120212
*************************************/
#include"sintable.h"
voidmain()
{
SCB>AIRCR=0x05AF0000|0x400; // =3:1
/***GPIO ***/
RCC>AHB1ENR|=(1<<0);// GPIOA
GPIOA>MODER|=0x00000F00;//PA45
GPIOA>PUPDR&=0xfffff0ff;//
/******/
TIM6>PSC=0;
TIM6>ARR=83; // 1m
TIM6>CR2|= 0x00000020;//
TIM6>CR1|=1;//
/***DAC ***/
RCC>APB1ENR|=(1<<29);// DAC
DAC>CR&=0xffff0000;
/*
DMA
1
*/
DAC>CR|=((1<<13)|(1<<2));
NVIC>IP[54]=0xA0;
NVIC>ISER[1]|=(1<<(5432));
/***DMA ***/
DAC>CR&=~(1<<12);//DACdma
DMA1>HIFCR|=0x000004f0;// DMA1_Stream5
DMA1_Stream5>PAR=(uint32_t)&DAC>DHR12R1;//
DMA1_Stream5>M0AR=(uint32_t)SinTable;//
DMA1_Stream5>CR|=0x0002800;//16
DMA1_Stream5>NDTR=1024;// dma
/*
dma 7 DAC1
Medium

*/
DMA1_Stream5>CR|=(0x0e000000|0x00010000|(1<<6)
|(1<<10)|(1<<8));
DMA1_Stream5>CR|=1;//DMA 5
DAC>CR|=(1<<0); //DAC 1
DAC>CR|=(1<<12);//DACdma
MyDebugger_Init();
while(1)
{
};
}
voidTIM6_DAC_IRQHandler(void)
{
if(DAC>SR&(1<<13))
{
MyDebugger_LEDs(red,on);
DAC>SR&=~(1<<13);
}
}
RM0090R
Referencema
anual
DAC
C
DAC_CR
299 DMAUDRIE22 DAC

2DMA
0
DAC
2 DMA
1
DAC
2 DMA
288 DMAEN2DDAC2 DM
MA
0
DAC
2 DMA
1
DAC
2 DMA
277:24 MAMP22[3:0]DAC
C2/
00000LSSFR0 /
1
3
00011LSSFR[1:0] /
7
00100LSSFR[2:0] /
15
00111LSSFR[3:0] /
31
01000LSSFR[4:0] /
63
01011LSSFR[5:0] /
127
01100LSSFR[6:0] /
255
01111LSSFR[7:0] /
511
10000LSSFR[8:0] /
1023
10011LSSFR[9:0] /
10100LSSFR[10:0] /
2047
7
10011
LSFR[11:0] /
40
095
233:22 WAVE2[[1:0]DAC
2/
00
01
1x
221:19 TSEL2[2:0]DAC 2
3
DAC 2
000
TIM6 TRGOO
001
TIM8 TRGOO
010
TIM7 TRGOO
011
TIM5 TRGOO
100
TIM2 TRGOO
101
TIM4 TRGOO
110
9
111
3
TEN2 = 1(DAC
2
)
18 TEN2DACC 2
/
DAC 2
0
DAC
2
DAC_DHRx
1 APB
B1
DAC_
_DOR2
1
DAC
2
DAC_DHRx
3 APB
B1
DAC_
_DOR2
DACC_DHRx
1 APB1
DAC_DOR2
17 BOFF2
DAC
2
/
DAC 2
0
DAC
2
1
DAC
2
16 EN2DAC 2
/
DAC 2
2
0
DAC
2
1
DAC
2
15:0
DAC DAC_SW
WTRIGR
1 SWTRIG2DDAC 2
0
DAC
2
1
DAC
2
DAC_DHR2
DAC_DO
OR2(1 APB1
)
00
0 SWTRIG1DDAC 1
0
DAC
1
1
DAC
1
DAC_DHR1
DAC_DO
OR1(1 APB1
)
00
DAC 1 12
DAC_DHR12
2R1
11:0 DACC1DHHR[11:0]D
DAC 1 12
DAC 1 122
DAC 1 12
DAC_DHR12
2R1
DAC 1 12
DAC 1 12
DAC 1 8
DAC_DHR8R1
77:0 DACC1DHRR[7:0]DAC
C 1 8
DAC 1 8
DAC 2 12
DAC_DHR12
2R2
DAC 1 12
DAC_DHR12
2R2
DAC 1 8
DAC_DHR8R2
DDAC 12
DDAC_DHR12RD
D
227:16 DACC2DDHR[11:0]DAC 2 12
DAC 2 122
DAC 1 12
DAC 1 122
DDAC 12
DDAC_DHR12LD
D
DDAC 8
DAAC_DHR8RD
DAC 1 DAC_DOR1
DAC 1
11:0 DACC1DOR[11:0]D
DAC 1
DAC 2 DAC_DOR2
11:0 DACC2DOR[11:0]D
DAC 2
DAC 2
DAC DAC_SR
229 DMAUDR2 DAC 2 DMA
0
DAC 2
1
DAC 2
ADC 2
DMA
ADC
12 ADC 19 16
2 Vbat A/D
ADC 16
/
16
3 8 2 2
0 2 2 15
16 ADC_SQRx
ADC_SQR1 L[3:0]
4 ADC_JSQR
ADC_JSQR L[1:0] ADC_SQRx ADC_JSQR
ADC

ADC ADC_CR2 ADON
()() CONT
0

16 ADC_DR
EOC() EOCIE

16 ADC_DRJ1
JEOC() JEOCIE
ADC

ADC
ADC_CR2 ADON CONT 1

16 ADC_DR
EOC()
EOCIE

ADC_CR1 SCAN ADC
ADC_SQRX () ADC_JSQR()
CONT

DMA EOC DMA SRAM
ADC_JDRx
ADC_SR EOC
EOCS 0
EOCS 1
ADC_JDRx

ADC_CR1 JAUTO SCAN
1. ADC_CR2 ADON
2. JSWSTART

3.

30 ADC ( 2 3 )
31 ADC

JAUTO
ADC_SQRx ADC_JSQR 20

JAUTO CONT

ADC_CR1 DISCEN n
(n<=8) ADC_SQRx n ADC_CR1
DISCNUM[2:0]
ADC_SQRx n
ADC_SQR1 L[3:0]

n=3 =012367910
012
367
910 EOC
012

01 2

ADC_CR1 JDISCEN
ADC_JSQR
ADC_JSQR
ADC_JSQR JL[1:0]
n=1 =123
1
2
3 EOC JEOC
1
1 IO
2 DMA
3 ADC ADC
4 ADC

/************************************
ADC
IARforARM6.21
stm32f4discovery
168M
author
data20120214
*************************************/
__IOuint16_tADC3ConvertedVault[10000];
charTXbuffer[]="PC1 :x.xxxV\n\r";
voidADC3_IN11_Config(void);
voidmain()
{
SCB>AIRCR=0x05AF0000|0x400; // =3:1
ADC3_IN11_Config();
MyDebugger_Init();
while(1)
{
};
}
voidADC3_IN11_Config(void)
{
/***GPIO ***/
GPIOC>MODER&=0xfffffff3;//PC1
GPIOC>MODER|=0x0000000C;
GPIOC>PUPDR&=0xfffffff3;//
/***DMA ***/
ADC3>CR2&=~(1<<8);//ADC3dma
DMA2>LIFCR|=0x0000003D;// DMA1_Stream5
DMA2_Stream0>PAR=(uint32_t)&ADC3>DR;//
DMA2_Stream0>M0AR=(uint32_t)ADC3ConvertedVault;//
DMA2_Stream0>CR|=0x0002800;//16
/*
dma2 2 ADC3
Medium

*/
DMA2_Stream0>CR|=(0x04000000|0x00010000|0x0
|(1<<10)|(1<<8)|(1<<4));
NVIC>IP[56]=0xB0;
NVIC>ISER[1]|=(1<<(5632));
DMA2_Stream0>CR|=1;//DMA2 0
/***ADC3 ***/
RCC>APB2ENR|=(1<<10);// ADC3
ADC3>SQR1=0x00000000;//
ADC3>SQR3=0x0000000B;// ADC3_in11
ADC3>CR1&=0x00000000;
ADC3>CR2&=0x00000000;
ADC3>CR2|=(1<<1); //
ADC3>CR2|=(1<<9);// ADC dma
ADC3>CR2|=(1<<0); // AD
ADC3>CR2|=(1<<8);//ADCdma
ADC3>CR2|=(1<<30);//
}
{
uint32_ti;
uint32_tAverage;
if(DMA2>LISR&0x00000010)
{
DMA2>LIFCR|=0x00000010;
for(i=0;i<10000;i++) //
Average+=ADC3ConvertedVault[i];
Average*=3;
Average/=40960;
TXbuffer[14]=(Average/1000)%10+0x30;// ASCII
TXbuffer[16]=(Average/100)%10+0x30;
TXbuffer[18]=Average%10+0x30;
MyDebugger_Message(TXbuffer,sizeof(TXbuffer)/sizeof(char));
}
}
RM0090R
Referencema
anual
ADC
C
ADC_SR
55OVRoverrun
DMA=1 EOCS=1

0
44STRT
33JSTRT
22JEOC
0

1

11EOC
ADC_DR

0

1

00AWD
ADC__LTR ADC_HTR
ADC
C
1ADC_CR1

226OVRIE
225:24RES
00:112 (15 ADCCLK
)
01:110 (13
ADCCLK
)
10:88 (11 ADCCLK
A
))
11:66 (9 ADCCLK
A
))
223AWDEN
222JAWDEN

115:13DISCNU
UM[2:0]

000
1
001
2

111
8
112JDISCEN
111DISCEN

110JAUTO

0
1
9AWDSGL
AWDCH[4:0]
0
1
8SCAN
ADC_SQRx
ADC_JSQRx
0
1
EOCIE JEOCIE EOC JEOC

7JEOCIE

0 JEOC
1 JEOC
JEOC
6AWDIE

0
1
5EOCIE EOC

0 EOC
1 EOC
EOC
4:0AWDCH[4:0]

00000ADC 0
00001ADC 1

01111ADC 15
10000ADC 16
10001ADC 17
10010ADC 18
ADC
C
2ADC_CR2
330SWSTART
ADON=1
229:28EXTEN

00
01
10
11
227:24EXTSEL[[3:0]
00000 1CC1
00011 1CC2
00100 1CC3
00111 2CC2
01000 2CC3
01011 2CC4
01100 2TRGO
01111 3CC1
10000 3TRGO
10011 4CC4
10100 5CC1
10111 5CC2
11000 5CC3
11011 8CC1
11100 8TRGO
11111 EXTIline11
222JSWSTART

JEXTSEL[2:0] JSWSTART
0
1
21:20JEXTEN
00
01
10
11
19:16JEXTSEL[3:0]
0000 1CC4
0001 1TRGO
0010 2CC1
0011 2TRGO
0100 3CC2
0101 3CC4
0110 4CC1
0111 4CC2
1000 4CC3
1001 4TRGO
1010 5CC4
1011 5TRGO
1100 8CC2
1101 8CC3
1110 8CC4
1111 EXTIline15
11ALIGN
0
1
10EOCS
0EOC DMA=1
1EOC
9DDSDMA ADC
0 DMA DMA
1 DMA=1 DMA

88 DMA ADC
DMA
0
DMA
A
1
DMA
11 CONT
00ADON// A/D
0
ADC

1
ADC
ADC
C
1ADC_
_SMPR1
226:0SMPx[2:0
0]
x
(Channe
elxSampletimeselectionn)
000
3
001
15
010
28
011
56
100
84
101
112
110
144
111
480
ADC
C
1ADC_
_SMPR1
ADC
C
x ADC_J
_JOFRx
111:0JOFFSETxx[11:0]
x
ADC
C_JDRx
ADC
C
ADC_HTR
111:0HT[11:0]
ADC
C
ADC_LRT
111:0LT[11:0]
ADC
C
1ADC_
_SQR1
223:20L[3:0]

000001
000112

1111116
119:15SQ16[4:0]
166
16
(0~17)
ADC
C
2ADC_
_SQR2
ADC
C
3ADC_
_SQR3
ADC
C
ADC_JSQR
221:20JL[1:0]

001
012
103
114
119:15JSQ4[4::0]
4
4
(0~17)
: JL[1:0]=3 (4
), AD C
: JSQ1[4:0], JSQ2[4
[4:0], JSQ3[4
4:0],
and JSQ4[4:0].
JL
L=2 (3
), ADC
A
:JSQ
Q2[4:0], JSQ3[4:0], and JJSQ4[4:0].
JL
L=1 (2
), ADC
: JS
SQ3[4:0], and
d then JSQ44[4:0].
JJL=0 (1
),
) ADC
JSQ4[4:0
0]
ADC
C
x AD
DC_JDRx(x=11..4)
155:0JDATA[15:0]
ADC
C ADC_D
DR
155:0 DATA[15
5:0]
ADC
C ADC_C
CSR
ADC
ADC__SR
0
211OVR3 AD
DC3
ADC3_SROV
VR
200STRT3AD
DC3
ADC3_SRSTR
RT
199JSTRT3
ADC3
3

ADC3_SRJST
TRT
18
JEOC3ADC
C3
ADC3_SRJEO
OC
177EOC3ADC
C3
ADC3_SREOC
AWD
D3ADC3
ADC3_SRAW
WD
ADC
CADC_CC
CR
233 TSVREFE
VREFINT
/
VR
REFINT
0
VREFINT
VREFINT
222 VBATEV
VBAT
/VB
BAT
0V
VBAT
1V
VBAT
17:16 ADCPREEADC
ADC
00PCLK2 2
01PCLK2 4
10PCLK2 6
11PCLK2 8
15514 DMA
AADC
00DMA
01DMA1
2/3
123
3
10DMA2
2/3 22&11&33&2
11DMA3
2/3 2&
&11&33
3&2
133DDSDMA
ADC
DMA
DMA
A
DMA
1
DMA=011011DMA
1118 delay 2
000005*TADCC
CLK
000116*TADCC
CLK
001007*TADCC
CLK
...
1111120*TADC
CCLK
4::0 MULTI[4::0]: ADC

ADC
000000
AD
DC300001
01001A
ADCA
ADC1ADC2
A
ADC3
000001
+
000110
+
000111
001001
001110
001111
010001
10000111001
ADC12
3
100001
+
100110
+
100111
101001
101110
101111
110001
ADC
ADC_
_CDR
311:16DATA2[1
15:0]

A
ADC2
ADC
ADC2ADC1ADC3ADC
15:0 DATA1[15:0]
ADC1ADC
ADC1ADC3ADC2ADC
ADC
ADC ADC1 ADC2 ADC3

ADC_CCR MULTI[4:0]
ADC ADC_CDR
ADC_CSR
ADC DMA
1 AD DMA ADC_CDR
1st request: ADC_CDR[31:0] = ADC1_DR[15:0]

2nd request: ADC_CDR[31:0] = ADC2_DR[15:0]
3rd request: ADC_CDR[31:0] = ADC3_DR[15:0]
4th request: ADC_CDR[31:0] = ADC1_DR[15:0]
2 AD DMA
ADC
ADC2 ADC1
1st request: ADC_CDR[31:0] = ADC2_DR[15:0] | ADC1_DR[15:0]
2nd request: ADC_CDR[31:0] = ADC2_DR[15:0] | ADC1_DR[15:0]
ADC
3rd request: ADC_CDR[31:0] = ADC3_DR[15:0] | ADC2_DR[15:0]
4th request: ADC_CDR[31:0] = ADC2_DR[15:0] | ADC1_DR[15:0]
2 AD DMA 2 DMA
6 8
ADC
8 ADC2 8 ADC1
ADC
3rd request: ADC_CDR[15:0] = ADC3_DR[7:0] | ADC2_DR[7:0]
4th request: ADC_CDR[15:0] = ADC2_DR[7:0] | ADC1_DR[7:0]
ADC
1.
2.
3.
4.
5. +
6. +
1 IO
2 DMA
3 ADC ADC
a. ADC
b. DMA
c. ADC DMA
d. ADC
e.
4 ADC ADC1

/************************************
ADC
IARforARM6.21
stm32f4discovery
168M
author
data20120216
*************************************/
__IOuint16_tADCConvertedVault[10000];
charTXbuffer[]="PC1 :x.xxxV\n\r";
voidADC_IO_Config(void);
voidADC_DMA_Config(void);
voidADC_Common_Config(void);
voidmain()
{
SCB>AIRCR=0x05AF0000|0x400; // =3:1
ADC_IO_Config();
ADC_DMA_Config();
ADC_Common_Config();
ADC3_IN11_Config();
ADC2_IN11_Config();
ADC1_IN11_Config();
ADC3>CR2|=(1<<0); // ADC3
ADC2>CR2|=(1<<0); // ADC2
ADC1>CR2|=(1<<0); // ADC1
ADC1>CR2|=(1<<30);//

MyDebugger_Init();
while(1)
{
};
}
voidADC_Common_Config(void)
{
RCC>APB2ENR|=((1<<8)|(1<<9)|(1<<10));// ADC
ADC>CCR&=0x00000000;
/*
DMA 1
ADC dma

2 5
*/
ADC>CCR|=(0x00004000|(1<<13)|0x00000017|0x00000000);
/***ADC1 ***/
{
ADC1>SQR1=0x00000000;//
ADC1>SQR3=0x0000000B;// ADC1_in11
ADC1>CR1&=0x00000000;
ADC1>CR2&=0x00000000;
ADC1>CR2|=(1<<1); //
ADC1>CR2|=(1<<8);//ADCdma
}
/***ADC2 ***/
{
ADC2>SQR1=0x00000000;//
ADC2>SQR3=0x0000000B;// ADC1_in11
ADC2>CR1&=0x00000000;
ADC2>CR2&=0x00000000;
ADC2>CR2|=(1<<1); //

}
/***ADC3 ***/
{
ADC3>SQR1=0x00000000;//
ADC3>SQR3=0x0000000B;// ADC3_in11
ADC3>CR1&=0x00000000;
ADC3>CR2&=0x00000000;
ADC3>CR2|=(1<<1); //
}
/***GPIO ***/
voidADC_IO_Config(void)
{
}
/***DMA ***/
voidADC_DMA_Config(void)
{
ADC3>CR2&=~(1<<8);//ADC3dma
DMA2>LIFCR|=0x0000003D;// DMA2_Stream0
DMA2_Stream0>PAR=(uint32_t)&ADC>CDR;//
DMA2_Stream0>M0AR=(uint32_t)ADCConvertedVault;//
DMA2_Stream0>CR|=0x0002800;//16
/*
dma2 0 ADC1
Medium

*/
DMA2_Stream0>CR|=(0x00000000|0x00010000|0x0|(1<<10)|(1<<8)|(1<<4));

NVIC>IP[56]=0xB0;
NVIC>ISER[1]|=(1<<(5632));
DMA2_Stream0>CR|=1;//DMA2 0
}
{
uint32_ti;
uint32_tAverage;
if(DMA2>LISR&0x00000010)
{
DMA2>LIFCR|=0x00000010;
for(i=0;i<10000;i++) //
Average+=ADCConvertedVault[i];
Average*=3;
Average/=40960;
TXbuffer[14]=(Average/1000)%10+0x30;// ASCII
TXbuffer[18]=Average%10+0x30;
MyDebugger_Message(TXbuffer,sizeof(TXbuffer)/sizeof(char));
}
}
stm32f4 ADC DAC

stm32f4 DAC DAC
ADC DAC
GF ( s ) =
Y ( s)
1
=
X (s) s + 1
y (k ) =
T
x(k ) + (1 ) y (k 1)
T T
a. 1024 DAC1
b. 6 1M
c. DAC TIM6 1024 0.5M
d. TIM6 AD
e. AD DAC2 DAC2

/************************************

IARforARM6.21
stm32f4discovery
168M
DAC1
ADC 11
ADC
DAC2
author
data20120217
*************************************/
#include"sintable.h"
/*****************/
uint16_tY0,Y1;//
floatT=0.000001;//
floatC=0.00003;//
/*****************/
voidtimer6_Init(void);
voidDAC_channel2_Config(void);
voidGenerate_SinSignal_with_Noise(void);
voidmain()
{
SCB>AIRCR=0x05AF0000|0x400; // =3:1
MyDebugger_Init();
ADC3_IN11_Config();
Generate_SinSignal_with_Noise();
DAC_channel2_Config();
timer6_Init();
while(1)
{
};
}
/**************************************
timer6_Init

6 1M
6 DAC12
ADC
**************************************/
voidtimer6_Init(void)
{
/******/
TIM6>PSC=0;
TIM6>ARR=83; // 1m
TIM6>CR2|= 0x00000020;//
TIM6>DIER|=1;//
TIM6>CR1|=1;//
}
/**************************************
Generate_SinSignal_with_Noise

DAC1
***************************************/
voidGenerate_SinSignal_with_Noise(void)
{
/***GPIO ***/
RCC>AHB1ENR|=(1<<0);// GPIOA
GPIOA>MODER|=0x00000F00;//PA45
GPIOA>PUPDR&=0xfffff0ff;//
/***DAC ***/
DAC>CR&=0xffff0000;
/*
DMA
1

*/
DAC>CR|=((1<<13)|(1<<2)|0x00000040|0x00000800);
NVIC>IP[54]=0xA0;
NVIC>ISER[1]|=(1<<(5432));
/***DMA ***/
DAC>CR&=~(1<<12);//DACdma
DMA1>HIFCR|=0x000004f0;// DMA1_Stream5
DMA1_Stream5>PAR=(uint32_t)&DAC>DHR12R1;//
DMA1_Stream5>M0AR=(uint32_t)SinTable;//
DMA1_Stream5>CR|=0x0002800;//16
/*
dma 7 DAC1
Medium

*/
DMA1_Stream5>CR|=(0x0e000000|0x00010000|(1<<6)
|(1<<10)|(1<<8));
DMA1_Stream5>CR|=1;//DMA 5
DAC>CR|=(1<<0); //DAC 1
DAC>CR|=(1<<12);//DACdma
}
/**************************************
ADC3_IN11_Config

ADC 11
***************************************/
{
/***GPIO ***/

/***ADC3 ***/
RCC>APB2ENR|=(1<<10);// ADC3
ADC3>SQR1=0x00000000;//
ADC3>SQR3=0x0000000B;// ADC3_in11
ADC3>CR1&=0x00000000;
ADC3>CR2&=0x00000000;
//
ADC3>CR1|=(1<<5);//
NVIC>IP[18]=0xc0;
NVIC>ISER[0]|=(1<<18);
}
/**************************************
DAC_channel2_Config

DAC2
***************************************/
voidDAC_channel2_Config(void)
{
/***DAC ***/
DAC>CR&=0x0000ffff;
/*
2

*/
DAC>CR|=((1<<18)|(0x00380000));
DAC>CR|=(1<<16); //DAC 2
}
voidTIM6_DAC_IRQHandler(void)
{
if(DAC>SR&(1<<13))
{
MyDebugger_LEDs(red,on);// DAC1 DMA
DAC>SR&=~(1<<13);
}
if(TIM6>SR)
{
ADC3>CR2|=(1<<0); // AD
ADC3>CR2|=(1<<30);//
TIM6>SR&=~(0x0001);
}
}
voidADC_IRQHandler(void)
{
if(ADC3>SR&(1<<1))
{
Y0=(uint16_t)((float)((T/C)*ADC3>DR)//
+(float)((1T/C)*Y1));
Y1=Y0;
DAC>DHR12R2=Y0; //DAC2
DAC>SWTRIGR|=(1<<1);
ADC3>SR&=~(1<<1);
}
}
A
AD

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90

Cortex-M4 Devices Generic User GuideARM M4

GPIOD>OSPEEDR&=0x00FFFFFF; //PD12,13,14,15 100m

Cortex--M4 Devices Generic U ser Guide

EXTI 0~15 PX0~15()

RCC>AHB1ENR|=0x00000009;// GPIOD GPIOA

STM32F407xx /USART1USART2USART3 USART6

USART APB USART_BRR USART_BRR

7 TXEIE (TXE interrupt enable)

1 USART ( RWU )USART

2(WAKE =1) RXNE RWU

111 CLKEN (Clockenablee)

( 2599 260) 544/754

(Lastt bit clock

5 SCEN: (Smartcard mode enable)

3 HDSEL (Half-dupllex selecti

(IrDA modde enable)

0 EIE (Error intterrupt ena

7:0 PSC[7:0] (Prescaler value)

6. DMA_SxCR CHSEL[2:0] DMA

RCC>AHB1ENR|=((1<<3)|(1<<21));// GPIOD , DMA1

DMA1_Stream3>PAR = (uint32_t)&USART3>DR;// USART3>DR

227, 21, 11, 5 TC

226, 20, 10, 4 HTIFx

225, 19, 9, 3 TEIFx

224, 18, 8, 2 DMEIFx

222, 16, 6, 0 FEIFx

227, 21, 11, 5 TC

226, 20, 10, 4 HTIFx

225, 19, 9, 3 TEIFx

224, 18, 8, 2 DMEIFx

222, 16, 6, 0 FEIFx

227, 21, 11, 5 CTCIFx

222, 16, 6, 0 CFEIFx

227, 21, 11, 5 CTCIFx

226, 20, 10, 4 CHTIFx

222, 16, 6, 0 CFEIFx

22:21 PBURST burst

DMA1_Stream3>PAR = (uint32_t)&USART3>DR;// USART3>DR

DMA1_Stream3>PAR = (uint32_t)&USART3>DR;// USART3>DR

12:8 DMA burst

11: OTG HS SOFF TIM2_ITR1

PWM OCx PWM TIMx_CCMRx

299 DMAUDRIE22 DAC

229 DMAUDR2 DAC 2 DMA

4::0 MULTI[4::0]: ADC

ADC ADC1 ADC2 ADC3

1st request: ADC_CDR[31:0] = ADC1_DR[15:0]

ADC2>CR2|=(1<<9);// ADC dma

stm32f4 ADC DAC

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