EE 402 Introduction to VLSI Design


Prof. Youngmin Kim ECE, UNIST 2013, 1st


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Outline

Logistics What I expect you to learn in this class CMOS processing sequence


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Logistics

Instructor: Prof. Youngmin Kim
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Email: youngmin@unist.ac.kr Office: EB2, 401-1 Phone: +2115 Office hour: Tue. & Thu. 10:00 ~ 12:00 AM (Other time available by appointment) Digital Integrated Circuits: A Design Perspective, 2nd edition by Rabaey, Chandrakasan, and Nikolic N. Weste and D. Harris, "CMOS VLSI Design: A Circuits and Systems Perspective, 3rd edition", Addison-Wesley, 2005. "Design of High-Performance Microprocessor Circuits", edited by A. Chandrakasan, W. Bowhill, and F. Fox, IEEE Press, 2001. D.A. Hodges, H.G. Jackson, and R.A. Saleh, "Analysis and Design of Digital Integrated Circuits in Deep Submicron Technology", 3rd edition, McGraw Hill, 2004.

Textbook
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References
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Lecture note will be posted online shortly before class sessions Supplement handouts

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Text Book

Digital Integrated Circuits

A Design Perspective
Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic

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Course Setup

Two 125 min lectures (Tue. & Thu. 1:00~3:05) @ EB2 T-206 Prerequisite: Logic design, circuit theory, electronic

devices, computer architecture, and etc

No fixed discussion session
l TA:

Yesung Kang (), @ EB2 402 for CAD supports bi-weekly, 4~5 CAD assignments IC design methodologies

HWs & CAD assignments

l Roughly l Custom
- - -

Circuit design, layout, simulations, and logic design (Verilog HDL) LVS and DRC Etc.
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Grading Breakdown

HW + CAD assignments: Midterm Exam: Final Exam: Final Project and Report:

30% (5+) 20% 30% 20%

CAD late policy: 25% penalty within 24 hours, 50% 24~48

hours, no point after 48 hours (2 days)

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What you will learn in this class


The entire process of very large-scale digital design (ASIC)
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Custom integrated circuit layout Sub-system design such as adders, register files, program counters, etc. Synthesis + automated place/route design flow (?)

Advanced circuit design topics such as:

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Multipliers, pulsed latches, memory decoder and sense amplifiers, etc. Current technology issues Process variations Robust design SRAM Power and performance optimization Timing Your interests and etc
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Research Area (NanoDA: Nano-System Design & Automation)


Very Large Scale Integration (VLSI)
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Ex., >1 billion transistors in Intels 32nm Efficient and inevitable way of design in VLSI Still require human (custom) design in certain area

Computer Aided Design (CAD)

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12 ~30cm

4.5cm

45nm = 45*10-9m = 0.000000045m Human hair: 50um ~ 100um (x1000)


270mm2

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The latest IC news


Phoenix mm-scale all-in-one computer 5nW !! power Eye pressure sensor <courtesy UMICH>
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8 cores Beckton die 45nm Intel Xeon ~ 2.26GHz, 130W $3,692 <courtesy Intel>
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Transistors


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Recent Devices


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More Recent Devices

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More Recent Devices


SOI (Silicon On Insulator)

High speed, low power

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Sub-5nm FinFET


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FinFET

Conducting channel is wrapped by a thin silicon "fin", which forms the

gate of the device.


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Why FinFET?

Reduced Short Channel Effect Increase driving current high performance Better leakage current control low power Good for low voltage (power) applications Compatible with current CMOS manufacturing and many more

Leakage Reduced

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Carbon-based Transistors


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Major Bottlenecks Researches


Managing complexity l How to design a 10 billion transistor chip? l And what to use all these transistors for? l Mask complexity (e.g., OPC, double exposure, etc) Cost of integrated circuits is increasing
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It takes >$10M to design a chip, >$100M in 1~2 years (e.g., Snapdragon ~ $60M) Mask costs are more than $3M in 45nm technology

The end of frequency scaling - Power as a limiting factor l Multi-core in a chip (e.g., dual, quad, 6, 8 cores, etc) l Beyond CMOS (?) after <10nm l Dealing with leakages Robustness issues
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Variations, SRAM, soft errors, coupling

The interconnect problem

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CMOS Process


N-well LOCOS isolated CMOS process

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Circuit Under Design and Layout View


VDD

Vin

Vout

Vout2

VSS

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The First Computer

Use decimal


The Babbage Difference Engine (1832) 25,000 parts 17,470 (in1834!)

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ENIAC - The first electronic computer (1946)

Still decimal, ~18,000 vacuum tubes, 63m2, 150kW


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The Transistor Revolution

First transistor Bell Labs, 1948

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The First Integrated Circuits (IC)

1st IC by J. Kilby@TI, 1958

Bipolar logic 1960s

ECL 3-input Gate Motorola 1966

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Intel 4004 Micro-Processor

1971~1981 4bit CPU 10um pMOS only 2300 transistors <1 MHz operation (740 KHz)

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Modern microprocessors

Pentium 4 180nm~65nm tech. ~ 3.8GHz, ~125 mil. Trs. 112mm2, 115W TDP (Thermal Design Power) LGA (Land Grid Array) 775

Core i7 45nm & 32nm tech. ~ 3.47GHz, 731 mil. Trs. 263mm2 , 18 ~ 130W TDP LGA 1366

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Moores Law
In

1965, Gordon Moore noted that the number of transistors on a chip (or die) doubled every 18 to 24 months. (2 yrs 18 mon.)
He

made a prediction that semiconductor technology will double its effectiveness (e.g., tr #) every 18 months
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Moores Law

Electronics, April 19, 1965.

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Evolution in Complexity

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Courtesy, Intel

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Moores law in Microprocessors

1000 Transistors (MT) 100 10 1 0.1 0.01 8085 8086 8080 8008 4004 1980 1990 Year 2000 2010 386 286 486

2X growth in 1.96 years!

P6 Pentium proc

0.001 1970

Transistors on Lead Microprocessors double every 2 years

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Courtesy, Intel
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Die Size Growth

100

Die size (mm)

10 8080 8008 4004 1 1970 8086 8085 286

386

P6 Pentium proc 486

~7% growth per year ~2X growth in 10 years

1980

1990 Year

2000

2010

Die size grows by 14% to satisfy Moores Law

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Courtesy, Intel

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Frequency
10000 1000 Frequency (Mhz) 100 486 10 1 0.1 1970 8085 8086 8080 8008 4004 1980 1990 Year 2000 2010 286 386

Doubles every 2 years

P6 Pentium proc

Courtesy, Intel

Lead Microprocessors frequency doubles every 2 years But, not true anymore !
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Power Dissipation
100 P6 Pentium proc 10 8086 286 1 8008 4004 8085 8080 386 486

Power (Watts)

0.1 1971 1974 1978 Year 1985 1992 2000

Courtesy, Intel

Lead Microprocessors power continues to increase

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Power density
10000 Power Density (W/cm2) 1000 100

Rocket Nozzle Nuclear Reactor

8086 10 4004 Hot Plate P6 8008 8085 Pentium proc 386 286 486 8080 1 1970 1980 1990 2000 2010 Year

Power density too high to keep junctions at low temp

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Courtesy, Intel

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Not Only Microprocessors

Cell Phone
Small Signal RF Power RF

Digital Cellular Market (Phones Shipped)

Power Management

1996 1997 1998 1999 2000

Units

48M 86M 162M 260M 435M

Analog Baseband
Digital Baseband (DSP + MCU)

(data from Texas Instruments) EE402

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Challenges in Digital Design

DSM
Microscopic Problems
Ultra-high speed design Interconnect Noise, Crosstalk Reliability, Manufacturability Power Dissipation Clock distribution. Everything Looks a Little Different

1/DSM
Macroscopic Issues
Time-to-Market Millions of Gates High-Level Abstractions Reuse & IP: Portability Predictability etc. and Theres a Lot of Them!

?
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Why Scaling?
Technology shrinks by 0.7/generation (49% smaller area) With every generation can integrate 2x more functions

per chip; chip cost does not increase significantly Cost of a function decreases by 2x But
l How

to design chips with more and more functions? l Design engineering population does not double every two years
Hence, a need for more efficient design methods l Exploit different levels of abstraction l Divide-and-conquer l CAD
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Design Abstraction Levels

SYSTEM

MODULE + GATE

CIRCUIT

DEVICE G S n+ n+ D

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Design Metrics
How to evaluate performance (quality) of a digital

circuit (gate, block, )?

l Cost:

Mass production l Reliability: Military or Medical l Scalability l Speed (delay, operating frequency): server l Power dissipation: handheld devices l Energy to perform a function

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Cost of Integrated Circuits

NRE (non-recurrent engineering) costs: fixed
l design

time and effort, mask generation T/O cost factor on the complexity of the design, the spec. and designers

l one-time l Depends l +

R&D costs

Recurrent costs: variable

l Silicon

manufacturing processing, packaging, test to volume to chip area

l proportional l proportional

= /+ /
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NRE Cost is Increasing

IC design costs for many devices are projected to hit the dreaded $100 million level within the next three years. Not long ago (and even today), IC design costs ranged between $20-to-$50 million Mentor CEO, EETimes, 3/2/2010

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Die Cost
Single die

Wafer
Going up to 12 (30cm) 775um thickness
From http://www.amd.com

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Cost per Transistor

-per-transistor

cost: 1 0.1 0.01 0.001

Fabrication capital cost per transistor (Moores law)

0.0001 0.00001 0.000001 0.0000001 1982 1985 1988 1991 1994 1997 2000 2003 2006 2009 2012

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Yield
No. of good chips per wafer Y= 100% Total number of chips per wafer Wafer cost Die cost = Dies per wafer Die yield (wafer diameter/2 )2 wafer diameter Dies per wafer = die area 2 die area

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Defects

defects per unit area die area die yield = 1 + where, is complexity of manufacturing process

is approximately 3 ( ~ # of masks) Defects: 0.5 ~ 1 defects/cm2

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die cost = f (die area)4

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Some Examples (1994)

Chip
386DX 486 DX2 Power PC 601 HP PA 7100 DEC Alpha Super Sparc Pentium

Metal Line Wafer layers width cost 2 3 4 3 3 3 3 0.90 0.80 0.80 0.80 0.70 0.70 0.80 $900 $1200 $1700 $1300 $1500 $1700 $1500

Def./ Area Dies/ Yield cm2 mm2 wafer 1.0 1.0 1.3 1.0 1.2 1.6 1.5 43 81 121 196 234 256 296 360 181 115 66 53 48 40 71% 54% 28% 27% 19% 13% 9%

Die cost $4 $12 $53 $73 $149 $272 $417

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Reliability Noise in Digital Integrated Circuits

v( t) i ( t)

V DD

Inductive coupling

Capacitive coupling

Power and ground noise

Noise: unwanted variations of (V) and (I) at the logic nodes

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DC Operation Voltage Transfer Characteristic (VTC)

V(y)

OH

f V(y)=V(x)

Vout = f(Vin) VOH = f(VOL) VOL = f(VOH) VM = f(VM)

VM Switching Threshold V OL V OL V OH V(x)

Nominal Voltage Levels (VDD=1, GND=0)

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Mapping between analog and digital signals

V
1 V OH V IH Undefined Region V 0 V

out Slope = -1 =

OH

dVout dVin

IL

Slope = -1 V OL V IL V IH V in

OL

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Definition of Noise Margins

"1" V OH NM H

Noise margin high

IH Undefined Region

V OL "0" Gate Output Stage M EE402

NM L

IL

Noise margin low

Gate Input Stage M+1

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Noise Budget
Allocates gross noise margin to expected sources of noise Sources: supply noise, cross talk, interference, offset Differentiate between fixed and proportional noise sources

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Key Reliability Properties

Absolute noise margin values are deceptive
l a

floating node is more easily disturbed than a node driven by a low impedance (in terms of voltage)

Noise immunity is the more important metric the

capability to suppress noise sources

Key metrics: Noise transfer functions, Output impedance of the

driver and input impedance of the receiver;

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Regenerative Property

v0

v1

v2

v3

v4

v5

v6

A chain of inverters

Simulated response
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Regenerative Property

Regenerative
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Non-Regenerative

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Fan-in and Fan-out

Fan-out N
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Fan-in M

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The Ideal Gate

V out

g=

Ri = Ro = 0 Fanout =
NMH = NML = VDD/2

V in

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An Old-time Inverter
5.0 4.0 3.0 NM L

Vout (V)

2.0 1.0

VM NM H

0.0

1.0

2.0 3.0 V in (V)

4.0

5.0

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Delay Definitions
Vin

Vout

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Ring Oscillator

T = 2 tp N
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A First-Order RC Network

vout C

vin

tp = ln (2) = 0.69 RC

Important model matches delay of inverter

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Power Dissipation
Instantaneous power: p(t) = v(t)i(t) = Vsupplyi(t) Peak power: Ppeak = Vsupplyipeak Average power:

Vsupply t +T 1 t +T Pave = p(t )dt = t isupply (t )dt T t T

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Energy and Energy-Delay

Power-Delay Product (PDP) = E = Energy per operation = Pav tp Energy-Delay Product (EDP) = quality metric of gate = E tp

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A First-Order RC Network
Vdd E0->1 = C LVdd2

R PMOS
A1 NETWORK

vout supply
Vout CL!

vin AN

NMOS NETWORK

CL

T E

Vdd 0 C dV = C V 2 L out L dd

= P ( t ) dt = V i t dt = V 01 dd sup ply( ) dd 0 0 T T Vdd

E ca p = P cap ( t ) dt = V out i ca p( t ) dt = 0 0

1 2 C L Vout dVout = -- CL V dd 2 0

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Summary
Digital integrated circuits have come a long way and still

have quite some potential left for the coming decades

Some interesting challenges ahead
l Getting

a clear perspective on the challenges and potential solutions is the purpose of this book

Understanding the design metrics that govern digital

design is crucial
l Cost,

reliability, speed, power and energy dissipation

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Looking Ahead


Read ch1, ch2 Lecture 2: ch2, insert A
l Manufacturing l Design l Layout l Etc


process

rules

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