What is the difference between Synchronous and Asynchronous?

Asynchronous Communication (independent transmit & receive clocks)

Asynchronous transmission uses start & stop bits which are added at the start & end of data segments. Asynchronous transmission provides 38.4 Kbps speed. Simple interface (limited data rate, typically < 64 kbps) Used for connecting: Printer, Terminal, Modem, home connections to the Internet No clock sent (Tx & Rx have own clocks) Requires start and stop bits which provides byte timing and increases overhead Parity often used to validate correct reception

Ex:UART Synchronous Communication (synchronised transmit & receive clocks)

Synchronous Transmission does not start & stop bits for sending data segments so a faster transmission speed is achieved Synchronous transmission provides 64 or 128 Kbps speed but More complex interface (high data rates supported up to ~ 10 Gbps) Used for: Connections between computer and telephony networks Clock sent with data (more configuration options)

Ex:I2C and SPI What is the difference between RS232 and UART? RS232 is a specification for serial communications between a DCE and DTE (eg, computer and modem); it defines electrical characteristics, the 25-way D connector and the various functions of the various signal lines. A UART is a Univeral Asynchronous Receiver and Transmitter it is an electronic circuit which handles communication over an asynchronous serial interface very often an RS232 interface. A USART is a Univeral Synchronous/Asynchronous Receiver and Transmitter its like a UART, but also supports Synchronous links USART is hardware Universal Synchronous Asynchronous Receive & Transmit Engine. No fixed protocol (7,8 or 9 bit with or without Receiver Addressing) but is normally capable of protocols that incorporate: Asynchronous usually RS232, RS422 & RS485 two wires TX & RX with pre-defined data rate and receiving synchronised to incoming data stream. No pre-defined master or slave and may be full duplex.

Synchronous two wires, fixed Clock (from single master) and Data half-duplex 8 or 9 bit & no slave address SPI is a communication protocol normally a three wire, synchronous, single master, multislave & duplex system. Wires are Master-Clock, Data In, Data Out & Slave Select(n). What is the difference between rs232 and rs485 port? RS232 full duplex point to point short distance(1 meter) at 115kbaud at least 3 wires (more with handshake control) RS485 half duplex point to multi-point (master to multiple slaves) 1200 m distance at 115kbaud 2 wire (RS422 uses 4 wires) Difference between Rs232 and RS485 is Only Distance RS232 is not for long or far distance.. But RS485 can be use for LONGEST distance .. RS232 is single ended communication where as RS485 is Differential communication. Max.no of receivers in RS232 is only ONE, whereas in RS485 is 32. Max.no of transmitters in RS232 is only ONE whereas in RS485 is 32. IN RS232 there is no pin to change from transmitter mode receiver mode. But, In RS485 have DE pin to set transmitter mode and RI to set receiver mode. Baud Rate Formula

#include<reg51.h> void main() { unsigned char i = 0xAA; PCON |= 080; //Double the baud rate value SCON = 050; //REN enable & 8-bit uart enable TMOD = 002; //Select auto reload mode in timer 1 TL1 = 0xA0; //Lower Byte

TH1 = 096; //Upper Byte TR1=1; //enable timer while(1) { WDT_RST = 0xA1; if(TF1) TF1=0; if(TI) { TI=0; SBUF=i; } if(RI) { RI=0; value=SBUF; SBUF=value; } } } for this program i choose the baud rate by using the following formula which i came to know by manual. baudrate=((2^smod)32*Oscillator Frequency)/(24*(256-TH1)) Framing in Data Transmissions UART Communication is bit oriented communication

Byte-oriented framing Computer data is normally stored as alphanumeric characters that are encoded with a combination of 8 bits (1 byte). This type of framing differentiates one byte from another. It is an older style of framing that was used in the terminal/mainframe environment. Examples of byte-oriented framing include IBMs BISYNC protocol.

Bit-oriented framing This type of framing allows the sender to transmit a long string of bits at one time. IBMs SDLC (Synchronous Data Link Control) and HDLC (Highlevel Data Link Control) are examples of bit-oriented protocols. Most LANs use bitoriented framing. There is usually a maximum frame size. For example, Ethernet has a maximum frame size of 1,526 bytes. The beginning and end of a frame is signaled with a

special bit sequence (01111110 for HDLC). If no data is being transmitted, this same sequence is continuously transmitted so the end systems remain synchronized.

Clock-based framing In a clock-based system, a series of repetitive pulses are used to maintain a constant bit rate and keep the digital bits aligned in the data stream. SONET (Synchronous Optical Network) is a synchronous system in which all the clocks in the network are synchronized back to a master clock reference. SONET frames are then positioned within the clocked stream.

What is the maximum distance of the I2C bus? This depends on the load of the bus and the speed you run at. In typical applications, the length is a few meters (9-12ft). The maximum capacitive load has been specified (see also the electrical Specs in the I2C FAQ). Another thing to be taken into account is the amount of noise picked up by long cabling. This noise can disturb the signal transmitted over the bus so badly that it becomes unreadable. The length can be increased significantly by running at a lower clock frequency. One particular application clocked at about 500Hz had a bus length of about 100m (300ft). If you are careful in routing your PCBs and use proper cabling (twisted pair and/or shielded cable), you can also gain some length. If you need to go far at high speed, you can use an active current source instead of a simple pullup resistor. Philips has a standalone product for this purpose. Using a charge pump also reduces ghost signals caused by reflections at the end of the bus lines. Id like to extend the I2C bus. Is there something like a repeater for I2C? Yes indeed this exists. Philips manufactures a special chip to buffer the bi-directional lines of the I2C bus. Typically, this is a current amplifier. It forces current into the wiring (a couple of mA). That way you can overcome the capacitance of long wiring. However, you will need this component on both sides of the line. The charge pump in this devices can deliver currents up to 30mA which is way too much for a normal I2C chip to handle. With these buffers you can handle loads up to 2nF. The charge amplifier transforms this load down to a 200pF load which is still acceptable by I2C components. Difference between spi and i2c? SPI or CSI is a simple master/slave communication protocol. I2C is a networking communication protocol with a multi-master support

Incase of I2C programmer has to take care of right sequence of data transfer on bus like address, start, stop, ack, nak etc where as in case of SPI just SS (slave select) is to be managed and data read/write is done from SSPDAT register 1) I2C is half duplex while SPI can be full duplex. 2) Device addressing in I2C is simple because it uses Addresses as part of the data stream. SPI generally requires additional Chip Select signals. 3) SPI can achieve much higher data rates compared to I2C. context switch A context switch is the computing process of storing and restoring the state (context) of a CPU so that execution can be resumed from the same point at a later time. This enables multiple processes to share a single CPU resource. The context switch is an essential feature of a multitasking operating system. Context switches are usually computationally intensive and much of the design of operating systems is to optimize the use of context switches. A context switch can mean a register context switch, a task context switch, a thread context switch, or a process context switch. What constitutes the context is determined by the processor and the operating system. Switching from one process to another requires a certain amount of time for doing the administration saving and loading registers and memory maps, updating various tables and list etc. Interrupts An interrupt is an event in hardware that triggers the processor to jump from its current program counter to a specific point in the code. Interrupts are designed to be special events whose occurrence cannot be predicted precisely (or at all). The MSP has many different kinds of events that can trigger interrupts, and for each one the processor will send the execution to a unique, specific point in memory. Each interrupt is assigned a word long segment at the upper end of memory. This is enough memory for a jump to the location in memory where the interrupt will actually be handled. Interrupts in general can be divided into two kinds- maskable and nonmaskable. A maskable interrupt is an interrupt whose trigger event is not always important, so the programmer can decide that the event should not cause the program to jump. A non-maskable interrupt (like the reset button) is so important that it should never be ignored. The processor will always jump to this interrupt when it happens. Often, maskable interrupts are turned off by default to simplify the default behavior of the device. Special control registers allow nonmaskable and specific non-maskable interrupts to be turned on. Interrupts generally have a priority; when two interrupts happen at the same time, the higher priority interrupt will take precedence over the lower priority one. Thus if a peripheral timer goes off at the same time as the reset button is pushed, the processor will ignore the peripheral timer because the reset is more important (higher priority). interrupt service routine (ISR)

An interrupt service routine (ISR) is a software routine that hardware invokes in response to an interrupt. ISRs examine an interrupt and determine how to handle it. ISRs handle the interrupt, and then return a logical interrupt value. If no further handling is required because the device is disabled or data is buffered, the ISR notifies the kernel with a SYSINTR_NOP return value. An ISR must perform very fast to avoid slowing down the operation of the device and the operation of all lower priority ISRs.

In SPI protocol why clk pin is used? is it neccessary?

To begin a communication, the master first configures the clock, using a frequency less than or equal to the maximum frequency the slave device supports. Such frequencies are commonly in the range of 1-70 MHz. The master then pulls the slave select low for the desired chip. If a waiting period is required (such as for analog-to-digital conversion) then the master must wait for at least that period of time before starting to issue clock cycles. During each SPI clock cycle, a full duplex data transmission occurs: the master sends a bit on the MOSI line; the slave reads it from that same line the slave sends a bit on the MISO line; the master reads it from that same line Not all transmissions require all four of these operations to be meaningful but they do happen. Transmissions normally involve two shift registers of some given word size, such as eight bits, one in the master and one in the slave; they are connected in a ring. Data is usually shifted out with the most significant bit first, while shifting a new least significant bit into the same register. After that register has been shifted out, the master and slave have exchanged register values. Then each device takes that value and does something with it, such as writing it to memory. If there is more data to exchange, the shift registers are loaded with new data and the process repeats. Transmissions may involve any number of clock cycles. When there is no more data to be transmitted, the master stops toggling its clock. Normally, it then deselects the slave. Transmissions often consist of 8-bit words, and a master can initiate multiple such transmissions if it wishes/needs. However, other word sizes are also common, such as 16-bit words for touchscreen controllers or audio codecs, like the TSC2101 from Texas Instruments; or 12-bit words for many digital-to-analog or analog-to-digital converters.

Every slave on the bus that hasnt been activated using its slave select line must disregard the input clock and MOSI signals, and must not drive MISO. The master must select only one slave at a time.