Design of Millimeter-wave SiGe Frequency Doubler and

Output Buffer for Automotive Radar Applications

Master thesis performed at Acreo AB

in collaboration with Division of Electronic Devices,
Dept. of Electrical Engineering, Linkping University

by

Amjad Altaf




Report number: LiTH-ISY-EX--07/3978--SE
February 2007























































ii






Title
Design of Millimeter-wave SiGe Frequency Doubler and
Output Buffer for Automotive Radar Applications


Master thesis in Division of Devices

Department of Electrical Engineering

Linkping University, Sweden

by

Amjad Altaf

LiTH-ISY-EX--07/3978--SE





Supervisor: Darius Jakonis (Acreo AB, Norrkping)

Examiner: Jerzy Dabrowski (ISY)


Linkping: February 2007










iii























































iv

Presentation Date Division of Electronics

2007-02-08 Systems

Publishing Date (Electronic

version) Department of Electrical

2007-02-15 Engineering



Language Type of Publication ISBN (Licentiate thesis)


Licentiate thesis


English



ISRN: LiTH-ISY-EX--07/3978SE


^ Degree thesis

Number of Pages
Thesis C-level Title of series (Licentiate thesis)


Thesis D-level

88



Report



Other (specify below)

Series number/ISSN (Licentiate thesis)







URL, Electronic Version
http://www.ep.liu.se
Publication Title
Design of millimeter-wave SiGe frequency doubler and output buffer for automotive radar applications
Author
Amjad Altaf

Abstract

Automotive Radars have introduced various functions on automobiles for drivers safety and comfort, as part of the Intelligent
Transportation System (ITS) including Adaptive Cruise Control (ACC), collision warning or avoidance, blind spot surveillance
and parking assistance. Although such radar systems with 24 GHz carrier frequency are already in use but due to some regulatory
issues, recently a permanent band has been allocated at 77-81 GHz, allowing for long-term development of the radar service. In
fact, switchover to the new band is mandatory by 2014.
A frequency multiplier will be one of the key components for such a millimeter wave automotive radar system because there are
limitations in direct implementation of low phase noise oscillators at high frequencies. A practical way to build a cost-effective and
stable source at higher frequency is to use an active multiplier preceded by a high spectral purity VCO operating at a lower
frequency. Recent improvements in the performance of SiGe technology allow the silicon microelectronics to advance into areas
previously restricted to compound semiconductor devices and make it a strong competitor for automotive radar applications at 79
GHz.
This thesis presents the design of active frequency doubler circuits at 20 GHz in a commercially available SiGe BiCMOS
technology and at 40GHz in SiGe bipolar technology (Infineon-B7h200 design). Buffer/amplifier circuits are included at output
VWDJHV WR GULYH ORDG 7KH IUHTXHQF\ GRXEOHU DW *+] LV EDVHGon an emitter-coupled pair operating in class-B
configuration
at 1.8 supply voltage. Pre-layout simulations show its conversion gain of 10 dB at -5 dBm input, fundamental suppression of
G% DQG 1) RI G% ,QSXW DQG RXWSXW LPSHGDQFH PDWFKLQJ QHWZRUNV DUH GHVLJQHG WR PDWFK DW ERWK VLGHV
The millimeter wave frequency doubler is designed for 5 V supply voltage and has the Gilbert cell-based differential architecture
where both RF and LO ports are tied together to act as a frequency doubler. Both pre-layout and post-layout simulation results are
presented and compared together. The extracted circuit has a conversion gain of 8 dB at -8 dB input, fundamental suppression of
20 dB, NF of 12 dB and it consumes 42 mA current from supply. The layout occupies an area of 0.12 mm
2
without pads and baluns
at both input and output ports. The frequency multiplier circuits have been designed using Cadence Design Tool.


Number of pages: 88

Keywords
Automotive Radar, VCO, Frequency Multiplier, SiGE, ACC, Millimeter-wave


v























































vi
Abstract

Automotive Radars have introduced various functions on automobiles for
drivers safety and comfort, as part of the Intelligent Transportation
System (ITS) including Adaptive Cruise Control (ACC), collision
warning or avoidance, blind spot surveillance and parking assistance.
Although such radar systems with 24 GHz carrier frequency are already
in use but due to some regulatory issues, recently a permanent band has
been allocated at 77-81 GHz, allowing for long-term development of the
radar service. In fact, switchover to the new band is mandatory by 2014.

A frequency multiplier will be one of the key components for such a
millimeter wave automotive radar system because there are limitations in
direct implementation of low phase noise oscillators at high frequencies.
A practical way to build a cost-effective and stable source at higher
frequency is to use an active multiplier preceded by a high spectral purity
VCO operating at a lower frequency. Recent improvements in the
performance of SiGe technology allow the silicon microelectronics to
advance into areas previously restricted to compound semiconductor
devices and make it a strong competitor for automotive radar applications
at 79 GHz.

This thesis presents the design of active frequency doubler circuits at 20
GHz in a commercially available SiGe BiCMOS technology and at
40GHz in SiGe bipolar technology (Infineon-B7h200 design). Buffer/amplLILHU
FLUFXLWV DUH LQFOXGHG DW RXWSXW VWDJHV WR GULYH ORDG
The frequency doubler at 20 GHz is based on an emitter-coupled pair
operating in class-B configuration at 1.8 V supply voltage. Pre-layout
simulations show its conversion gain of 10 dB at -5 dBm input,
fundamental suppression of 25dB and NF of 12dB. Input and output
LPSHGDQFH PDWFKLQJ QHWZRUNV DUH GHVLJQHG WR PDWFK
DW ERWK VLGHV


The millimeter wave frequency doubler is designed for 5 V supply
voltage and has the Gilbert cell-based differential architecture where both
RF and LO ports are tied together to act as a frequency doubler. Both pre-
layout and post-layout simulation results are presented and compared
together. The extracted circuit has a conversion gain of 8 dB at -8 dB
input, fundamental suppression of 20 dB, NF of 12 dB and it consumes
42 mA current from supply. The layout occupies an area of 0.12 mm
2



vii
without pads and baluns at both input and output ports. The frequency
multiplier circuits have been designed using Cadence Design Tool.






















































viii
Acknowledgments

I am thankful to my God for providing me health and energy for this
thesis work and other uncountable blessings throughout my life. I would
like to express my gratitude to all those who helped me in completing this
thesis work. I am deeply indebted to my academic supervisor Prof. Jerzy
from Electronic Devices division of Linkping University whose
technical help, valuable suggestions and encouragement assisted me
through out the entire thesis work and writing this report.

I am obliged to Acreo AB, Norrkping for giving me chance to use their
technical resources required for this thesis work. I am deeply grateful to
Dr. Darius Jakonis, my supervisor at Acreo, for his detailed and
constructive comments, and for his important support throughout this
work at Acreo. I warmly thank Joacim Olsson and Berthold Panznerthe
for their valuable advices and friendly assistance. I wish to thank Patrick
Blomqvist for his administrative help in keeping my stay at Acreo more
comfortable.

I am grateful to my parents for their constant encouragement and prays
on which I have relied throughout my life. I have been much supported
by my wife Beenish and daughter Maham for accommodating my busy
schedule in my study program.

My parents and my family, it is to them that I dedicate this work.





















ix























































x
Preface

This master thesis work describes the design of frequency doubler
circuits at 20 GHz and 40 GHz for automotive radar application.
Frequency multiplier circuits facilitate building a cost-effective and
stable source at higher frequency. Low-frequency, high spectral purity
VCOs are followed by frequency multiplier circuits because there are
limitations to achieve low phase noise oscillator directly at high
frequencies. SiGe BiCMOS technology is used for design of the
frequency doubler at 20 GHz and SiGe bipolar technology for the
frequency doubler at 40 GHz.

Chapter-1 starts with an introduction to automotive radar systems, their
working principle and current development status. Low-cost stable signal
source for automotive radars at 77 GHz can be built using VCO at low
frequency followed by some frequency multiplier circuit. This
architecture has a few attractions over direct implementation of VCO at
higher frequency and is the motivation to this thesis work.

Chapter-2 is an introduction to frequency multipliers, their types and
working principle. Theory of some basic cells used in common frequency
multiplier circuits have been discussed followed by an overview of
research work carried on frequency multiplier circuits.

Chapter-3 describes design of frequency doubler circuits at 20 GHz in
the commercially avaialable SiGe BiCMOS technology. Schematic
design of single-ended and differential circuit is provided followed by
simulation results of both architectures.

Chapter-4 represents design of frequency doubler at 40 GHz in
Infineons B7HF200 SiGe bipolar technology (f
T
=200GHz). Gilbert
mixer is used for frequency doubling by feeding same signal to LO and
RF ports. Schematic and layout design describing each step of balanced
circuit architecture is provided.

Chapter-5 is dedicated to the performance evaluation of 40 GHz
frequency doubler circuit designed in Chapter-4. Simulations are carried
out using Cadence Spectra RF environment tool. Circuits basic
parameters like conversion gain, fundamental suppression, dc power
consumption and NF for both schematic and layout are evaluated and
compared together.

xi
Chapter-6 concludes the work presented in this thesis report. The
chapter also summarizes the key-points learned during the whole process
followed by some recommendations for the future work.





















































xii
List of Abbreviations

Balun Balanced Unbalanced
BiCMOS Bipolar and CMOS technology on one chip
BJT Bipolar Junction Transistor
dB Decibels
dBm Power level in dB (decibels) with respect to 1 mW
DRC Design Check Rules
ETSI European Telecommunication Standards Institute
FDD Frequency Division Duplex
FCC Federal Communications Commission
FET Field Effect transistor
FM Frequency Modulation
FMCW Frequency Modulated Continuous Wave
FSK Frequency Shift Keying
CG Power / Voltage Conversion Gain
HBT Hetero Junction Bipolar Transistor
HEMT High Electron-Mobility Transistors
IF Intermediate Frequency
IIP3 Input Referred 3
rd
Order Intercept Point
I/O Input/Output
ITS Intelligent Transport System
LO Local Oscillator
LRR Long Range Radar
MMIC Monolithic Microwave Integrated Circuits
MOS Metal Oxide Semiconductor
PA Power Amplifier
PAC Periodic
PLL Phase Lock Loop
PNoise Periodic Noise
PSK Phase Shift Keying
PSP Periodic Scattering Parameters
PSS Periodic Steady State


xiii
QPAC Quasi Periodic
QPSS Quasi Periodic Steady State
RF Radio Frequency
RFIC Radio Frequency Integrated Circuit
Rx Receiver
SRR Short Range Radar
SSB NF Single Side Band Noise Figure
Tx Transmitter
VCO Voltage control Oscillator











































xiv

Table of Contents

ABSTRACT ............................................................................................. VII
ACKNOWLEDGMENTS ............................................................................IX
PREFACE ..................................................................................................XI
LIST OF ABBREVIATIONS ..................................................................... XIII
TABLE OF CONTENTS .............................................................................XV
LIST OF FIGURES ................................................................................. XVII
LIST OF TABLES ................................................................................... XIX
CHAPTER-1
OVERVIEW OF AUTOMOTIVE RADAR SYSTEMS ......................................1
1.1. INTRODUCTION ...............................................................................3
1.2. NEED FOR AUTOMOTIVE RADAR .........................................................3
1.3. CURRENT STATUS OF AUTOMOTIVE RADARS ........................................5
1.3.1. Regulatory Aspects in US ...............................................................5
1.3.2. Regulatory Aspects in Europe ..........................................................5
1.4. FUTURE CHALLENGES ......................................................................8
1.5. SIGE: COMPETITOR TECHNOLOGY FOR AUTOMOTIVE RADAR APPLICATIONS . 9
1.6. AUTOMOTIVE RADAR TYPES AND MODULATION SCHEMES .................... 10
1.6.1. FM-CW ..................................................................................... 10
1.6.2. FSK .......................................................................................... 12
1.6.3. Pulse Doppler Radar ................................................................... 13
1.7. FREQUENCY SOURCE FOR MILLIMETER-WAVE AUTOMOTIVE RADAR ....... 14

CHAPTER-2
FREQUENCY MULTIPLIER ARCHITECTURES ........................................ 17
2.1. INTRODUCTION ............................................................................. 19
2.2. PASSIVE MULTIPLIERS ..................................................................... 19
2.3. ACTIVE MULTIPLIERS ...................................................................... 20
2.3.1. Emitter Coupled Pair as Simple BJT multiplier ................................. 21
2.3.2. Gilbert Multiplier Cell ................................................................. 24
2.3.3. Common Frequency Doubler Circuits ............................................. 27

CHAPTER-3
THE DESIGN OF 20-GHZ FREQUENCY DOUBLER AND OUTPUT
AMPLIFIER CIRCUIT ............................................................................... 29
3.1. INTRODUCTION ............................................................................. 31
3.2. CIRCUIT SPECIFICATIONS ................................................................ 31
3.3. PROPOSED SINGLE-ENDED CIRCUIT ................................................... 32
3.3.1. Design Methodology .................................................................... 33
3.3.2. Improvement by Second Harmonic Reflector .................................... 34

xv
3.3.3. Simulation Results ....................................................................... 35
3.4. PROPOSED DIFFERENTIAL CIRCUIT .................................................... 38
3.4.1. Circuit Description ..................................................................... 39
3.4.2. Optimum value of size ratio K ....................................................... 41
3.4.3. Simulation Results ....................................................................... 42

CHAPTER-4
THE DESIGN OF 40-GHZ FREQUENCY DOUBLER AND OUTPUT
AMPLIFIER CIRCUIT ............................................................................... 45
4.1. INTRODUCTION ............................................................................. 47
4.2. TECHNOLOGY DETAILS ................................................................... 47
4.3. CIRCUIT SPECIFICATIONS ................................................................ 48
4.4. DESIGN CONSIDERATIONS ............................................................... 48
4.5. PROPOSED ARCHITECTURE .............................................................. 50
4.6. DESIGN DESCRIPTION ..................................................................... 50
4.6.1. Input Buffer Stage ....................................................................... 50
4.6.2. Gilbert Cell................................................................................ 52
4.6.3. Filter ........................................................................................ 55
4.6.4. Differential Amplifier................................................................... 56
4.6.5. Integrated Circuit ....................................................................... 58
4.7. LAYOUT OF THE FREQUENCY DOUBLER CIRCUIT ................................. 60
4.7.1. Layout Design Considerations ....................................................... 60
4.7.2. Pad Frame ................................................................................ 61
4.7.3. Emitter-Follower Layout .............................................................. 62
4.7.4. Gilbert Cell and Filter Layout ....................................................... 63
4.7.5. Frequency Doubler Core Layout .................................................... 64
4.7.6. Complete Layout ......................................................................... 65
4.7.7. Layout Verification...................................................................... 65

CHAPTER-5
SCHEMATIC AND LAYOUT SIMULATION RESULTS OF 40-GHZ
FREQUENCY DOUBLER CIRCUIT ............................................................ 67
5.1. INTRODUCTION ............................................................................. 69
5.2. CONVERSION GAIN AND NF ............................................................. 69
5.3. OUTPUT SPECTRUM AND FUNDAMENTAL SUPPRESSION ......................... 71
5.4. S11 AND S22 ................................................................................ 72
5.5. CORNER ANALYSIS ........................................................................ 74

CHAPTER-6
CONCLUSION AND FUTURE WORK ......................................................... 77
6.1. INTRODUCTION ............................................................................. 79
6.2. KEY POINTS LEARNED .................................................................... 79
6.3. FUTURE WORK ............................................................................. 80

REFERENCES ........................................................................................... 83




xvi
List of Figures

Figure 1: Installation of Automotive Radar and its different kind of
applications [9] .......................................................................................... 4
Figure 2: The Package Solution [9] ........................................................ 7
Figure 3: Time schedule for the development and rollout of 79 GHz SRR
sensors [9].................................................................................................. 7
Figure 4: Prediction of the evaluation of automotive radar application
[11] ............................................................................................................ 8
Figure 5: Typical FMCW Radar [17]...................................................... 11
Figure 6: Typical FSK Radar [17]........................................................... 12
Figure 7: Typical Pulse Radar [17] ......................................................... 13
Figure 8: RF-front end of FMCW automotive radar............................... 15
Figure 9: Emitter-Coupled pair [26]........................................................ 21
Figure 10 : The dc transfer characteristics of emitter-coupled pair [26]. 22
Figure 11: Two quadrant analog multiplier [26] ..................................... 23
Figure 12: Gilbert multiplier circuit ........................................................ 25
Figure 13: Frequency doubler based on class-B configuration and output
amplifier [37]........................................................................................... 32
Figure 14: Collector current modelled as a train of rectified cosine pulses
[38] .......................................................................................................... 33
Figure 15: Plot of Conversion Gain and NF versus input power ........... 36
Figure 16: Plot of Conversion Gain and NF versus frequency .............. 36
Figure 17: Output frequency spectrum for input signal of -8dBm at 20
GHz ................................................................................. ........................ 37
Figure 18: Input impedance matching.................................................... 37
Figure 19: Output impedance matching ................................................. 38
Figure 20: Frequency doubler consists of two identical unbalanced
emitter-coupled pairs with emitter area ratio K and differential amplifier
................................................................................................................. 39
Figure 21: DC transfer curves of frequency doubler [43] ....................... 41
Figure 22: Relative size ratio K versus gain............................................ 41
Figure 23: Plot of Conversion Gain and NF versus input power ........... 42
Figure 24: Output frequency spectrum for input power -8dBm at 20 GHz
................................................................................................................. 43
Figure 25: Pseudo-differential output signals ........................................ 43
Figure 26: Use of active mixer as frequency doubler ............................ 49
Figure 27: Proposed architecture for frequency doubler at 40 GHz ...... 50
Figure 28: Emitter-follower circuit (common-collector configuration)
[26] .......................................................................................................... 51

xvii
Figure 29: Small-signal equivalent circuit of emitter-follower circuit [26]
51
Figure 30 Gilbert mixer .......................................................................... 53
Figure 31: Variable gain of Gilbert mixer in frequency doubler circuit 54
Figure 32: Effective inductance of a lossless transmission line for l< /4

56
Figure 33: Differential Amplifier............................................................ 57
Figure 34: Detailed circuit diagram for frequency doubler at 40 GHz .. 59
Figure 35: Pad Frame .............................................................................. 61
Figure 36: Layout of emitter-follower stage ........................................... 62
Figure 37: Layout of Gilbert cell and filter ............................................. 63
Figure 38: Layout of frequency doubler core ......................................... 64
Figure 39: Layout of complete chip ........................................................ 65
Figure 40: Layout verification process ................................................... 66
Figure 41: Test Bench ............................................................................. 69
Figure 42: Conversion gain versus input power ..................................... 70
Figure 43: NF versus input power .......................................................... 70
Figure 44: Output spectrum of the schematic ......................................... 71
Figure 45: Output spectrum of the layout ............................................... 72
Figure 46: S11 plotted on Smith chart .................................................... 73
Figure 47: S22 plotted on Smith chart .................................................... 73
Figure 48: Conversion gain versus frequency at different temperatures 74
Figure 49: NF versus frequency at different temperatures ..................... 75

























xviii
List of Tables

Table-1: Specifications of LRR and SRR ................................................. 9
Table-2: Specifications of 20 GHz frequency doubler circuit ................ 31
Table-3: Design Parameters of 20 GHz frequency doubler circuit......... 35
Table-4: Summary of simulation results for20 GHz frequency doubler
circuits ..................................................................................................... 44
Table-5: Specifications of 40 GHz frequency doubler circuit ................ 48
Table-6: Design parameter values for 40 GHz frequency doubler circuit
58
Table-7: Circuit performance at different temperatures ......................... 76
Table-8: Comparison of frequency doubler circuits ............................... 79






































xix























































xx













Chapter-1


Overview of Automotive Radar Systems



































1























































2
1.1. Introduction

Automotive radar, as the name indicates, is any radar that has an
application in automobiles and other autonomous ground vehicles. As a
result, it represents a large and heterogeneous class of radars that are
based on different technologies (e.g., laser, ultrasonic, microwave),
perform different functions (e.g., obstacle and curb detection, collision
anticipation, adaptive cruise control), and employ different operating
principles (e.g., pulse radar, frequency-modulated continuous-wave
[FMCW] radar, microwave impulse radar) [1]. The discussion here is
limited to microwave radars that form a commercially significant subset
of automotive radars and is a key technology especially due to its
inherent advantages like weather independence and direct acquisition of
range and velocity when compared to alternative sensors like video, laser,
and ultrasonic [2]. Additionally radar offers the vehicle manufacturers the
stylistic advantage of mounting behind a plastic bumper.


1.2. Need for Automotive Radar

The need for automotive radars can be understood at three different
levels.
National level: The statistics on traffic fatalities, injuries, and
property loss due to vehicle accidents, and estimates of their
fractions that are preventable with technological aids, has
encouraged the development of automotive radar. The economic
value of those losses, when compared with the dropping cost of
automotive radar, leads to a cost-benefit analysis that favours their
widespread deployment.

Automotive manufacturer level: Radar is another feature for
the consumer to purchase that could be a possible source of
revenue and competitive advantage. It is also a possible response
to regulatory and public demands for safer vehicles.

Vehicle owners level: Automotive radar has an appeal as a safety
device, and as a convenient, affordable gadget. Of greater practical
importance is the potential for radar to lower the stress in


3
driving and decrease the sensory workload of the driver by taking
over some of the tasks requiring attentiveness, judgment, and skill.

As a conclusion, automotive radar facilitates various functions that
increase the drivers safety and comfort. Some of significant functions
are
Adaptive Cruise Control (ACC) support with stop and go

functionality

Collision warning or avoidance

Blind spot surveillance

Parking assistance (forward and reverse)

Lane change assistance

Rear crash collision warning

Fig. 1 shows the installation of automotive radar on front bumper of
vehicle and the basic applications of automotive radar.






























Figure 1: Installation of Automotive Radar and its different kind of applications [9]



4
1.3. Current Status of Automotive Radars

Today many car manufacturers use 77 GHz radar for autonomous cruise
control (ACC) and more recently for pre-crash or collision mitigation
also. In 1999, ACC was first introduced to the market in the Mercedes S-
Class under the name of Distronic [3]. In addition to 77 GHz long
range ACC sensors short-range radar (SRR), operating at 24 GHz has
been developed and is a key enabling technology for a number of novel
driver assistance and safety systems[4].

The prediction of a possible collision requires reliable object tracking
capability which means that SRR has to have sufficiently high resolution
to detect smaller objects such as motor cyclists or pedestrians in vicinity
of large objects [5]. Therefore, the range resolution has to be in the
centimeter range, resulting in a required bandwidth of up to 5 GHz
around the 24 GHz center frequency, which in fact is a so-called UWB
application (Ultra Wide Band). Short-range radar emits low power
signals within a typical detection range up to 30 m.

The use of the 24 GHz band has been proposed worldwide to be very
suitable for SRR [6] Compatibility studies with other services in this
frequency band - Fixed Services, Radio Astronomy Services and Earth
Exploration Satellites Services were carried out successfully.


1.3.1. Regulatory Aspects in US

In summer 2002 the FCC adopted the 24 GHz radar sensor approach for
the operation of vehicular radar in the 22-29 GHz band using directional
antennas on terrestrial transportation vehicles. The center frequency of
the emission and the frequency at which the highest radiated emission
occurs are higher than 24.075 GHz. A corresponding approach would be
favourable also for Region 3 countries [6].


1.3.2. Regulatory Aspects in Europe

The SRR concept has been strongly supported by the European
Commission within its e-Safety initiative. In order to allow an early

5
introduction of the SRR approach in Europe and to meet some of the
requirements of the e-Safety initiative a temporary solution was
developed accordingly. The implementation of SRR in Europe is based
on the following frequency management considerations, adapted in a
decision of the European Commission on January 17, 2005:

Possible temporary use of 21.65-26.65 GHz (24 GHz) frequency

band with limited number of equipment in the market place and

only applicable for a limited time frame; from 07/2005 to
06/2013. Technical conditions on SRR implementation should be
established in order to ensure protection of the existing services in
the 24 GHz band, thus, the SSR system penetration rate is
restricted to 7 percent of all cars in each country of the European
Community.

A permanent frequency band at 77-81 GHz range for short-range

radar applications in Europe was established in parallel. This 79

GHz band has been made available reliably within EU member
states and other CEPT countries in order to encourage industry
development of components and technology for this frequency
band.


According the output of the compatibility study [7] the introduction of
Short Range Radars in Europe should be in accordance with the 2-phase
plan shown in Fig. 2, the so-called package solution. To accomplish the
long-term requirement, a new frequency band with 4 GHz bandwidth for
automotive short range radars was designated around 79 GHz, in the
band 77 to 81 GHz. This band was designated to be a stable and
permanent frequency band for SRR employment only [8]. Such a reliable
designation is important for the automotive components industry to
provide the substantial investments necessary for the deployment of the
79 GHz equipment [9].

The most important obstacle today is that the necessary components for
SRR, using the 77 or 79 GHz band, are not yet commercially available.
The development will take at least 5-6 years. Thus, the automotive
industry has fostered this two-fold approach using 24 GHz with a fixed
deadline of 8 years to later migrate to a long-term frequency band. This
will limit the number of vehicles on the road and thus prevent any
aggregate interference potential, while allowing time for the development
of the necessary components for exploitation of the technology at the


6
higher frequency and for an early contribution to the enhancement of
road safety.



















Figure 2: The Package Solution [9]

Already in the year 2009, a report has to be made about the development
status of 79 GHz SRR technology [10]. The ECC frequency regulation
forces the development of 79 GHz SRR sensors within a time frame of
only 8.5 years. Considering the development cycles of automobiles this is
a very short time period. The transition from 24 GHz to 79 GHz causes
an increase in frequency and a reduction of wavelength by the factor 3.3.
7KH VPDOOHU ZDYHOHQJWK HQDEOHV UHGXFHG DQWHQQD VL]H DQG VSDFLQJ a

and lower effective antenna DUHD a
2
). The higher frequency yields
increased atmospheric and bumper losses. With higher frequencies
semiconductor power output decreases (roughly 20 dB per decade),
parasitic effects are more stringent, and packaging and testing are more
difficult. The development plan towards the introduction of 79 GHz SRR
sensors is shown in Fig. 3.










Figure 3: Time schedule for the development and rollout of 79 GHz SRR sensors [9]



7
1.4. Future Challenges

Some of the most important challenges for the future in the development
of automotive radar include

Development of automotive radars at permanent allocated band

(77-81 GHz) with multiple functions like long-range, short-range and precision
ranging.

Combined radar for ACC, pre-cash sensing and parking support

Implementation of 77-81 GHz automotive radar at low cost to

make it affordable for most of customers. The use of vehicle radar

will become more widespread as prices drop and the technology
proves its worth. As that happens, various technologies will
compete to serve as vehicles' "eyes." and technology with low
cost will have dominant edge over others.

Development of more advanced human interface and meeting

user expectations which are increasing with time as predicted in

Fig. 4 and they will keep their stress in evaluation of technology
that will eventually capable of providing a complete driving
support with automated throttle, break and steering controls of
vehicle.

























Figure 4: Prediction of the evaluation of automotive radar application [11]

8
1.5. SiGe: competitor technology for automotive radar
applications

The historical path in the electronics industry for reducing cost, and
improving and increasing functionality, has been to migrate toward IC-
based solutions. Therefore, in the first phase an effective and powerful
chip technology has to be developed. With the funding of the German
Ministry of Education and Research (BMBF) the joint research project
Automotive high frequency electronics KOKON [12] was started in
September 2004. The KOKON consortium consists of two semiconductor
companies (Atmel and Infineon), two automotive radar sensor
manufacturers (Bosch and Continental Temic), and one automobile
company (DaimlerChrysler) supported by institutes and universities.
Silicon Germanium (SiGe) has been identified as the chip technology
which may fulfil the technological requirements and the cost constraints
and which might be an alternative to GaAs [13]. Within the KOKON
project the development of both 77 GHz LRR and 79 GHz SRR radar
chip technology is investigated. As spin-off cost reduction and
performance improvement of 77 GHz LRR (long-range radar) sensors are
expected. The specifications of the 76.5 GHz LRR and 79 GHz SRR
systems are listed in Table-1.

Table-1: Specifications of LRR and SRR
Parameter LRR SRR
No of sensors Single-sensor Multiple-sensors
Frequency 76.5 GHZ 79 GHz
Bandwidth 200 MHz 4000 MHz
Maximum field of view 6.5-10 160
Range 200m 30 m
Range Accuracy 0.75 m 5 cm
Angular Resolution 3 5
Bearing Accuracy 0.1-0.4 1

With the allowed bandwidth B of 4 GHz in 79 GHZ SRR, the achievable UDQJH
UHVROXWLRQ 5 LV 3.75 cm according to the range resolution equation

R
c
(1)

= 2B



In Equation (1) the factor is due to the two-way travel time and c is
the speed of light.

9
With Silicon Germanium heterobipolar transistors (SiGe HBT) nowadays
transit frequencies f
T
of 300 GHz and f
max
of 350 GHz have been
reported by an IBM research group [14]. Infineon which is partner of the
KOKON consortium has achieved up to now f
T
of 225 GHz and f
max
of
300 GHz [15]. Therefore, even very high frequency applications like
wireless LANs at 60 GHz and 79 GHz radar MMICs, which can now
only be realized in expensive 111-V technologies, seem to become
feasible in a low cost silicon based technology in a highly integrated
manner.

One severe drawback of progress in SiGe technology is the avalanche
breakdown voltages (BV
CEO
BV
CBO
) which are further and further
reduced [16]. These technologies are not suitable for ICs with high output
power, where the transistor output voltage must substantially exceed the
supply. Still, for automotive radars application, SiGe HBT technology
has the potential to realize cost effective radar on chip solutions.


1.6. Automotive Radar Types and Modulation Schemes

Most forward-looking automotive radar systems are being developed at
77 GHz frequency using FM-CW, Frequency Shift Keying (FSK), or
Pulse Doppler modulation [17]. The operation principle of these types is
briefly described below.

1.6.1. FM-CW

The operation of the FMCW can be explained using the block diagram in
Fig. 5. The radar transmits a CW signal whose frequency is modulated as
a function of time with a triangular waveform. For typical FM-CW radars
the frequency deviation is on the order of 150 to 300 MHz with a period
of approximately 1 millisecond. The typical automotive radar will
transmit three to five beams (approximately 3" beamwidth), or use beam
scanning, to illuminate the center lane and the traffic lanes to both the left
and to the right of the automobile. Some radars will transmit a single
wide beam (approximately 12" beamwidth) and use the monopulse
receive techniques to locate vehicles off of boresight on the left and right
of the automobile. The signal reflected by the target (radar echo) in the
beam of the radar will be delayed by a time T
d
. Both the transmitted

10
signal and the radar echo are demodulated in a mixer. If the target is
moving relative to the radar transmitter, the demodulated I.F. frequency
is as shown in figure. If the target is stationary (no Doppler) the I.F.
frequency is constant and proportional to the range to the target. The I.F.
output is sampled by an A/D converter and a Fourier Transform is
applied. The average frequency (df) determines the range to the target,
and the Doppler frequency contains the relative velocity information.
This information is processed by the on board microprocessor used to
control the ACC radar function.

FM Mod

Antennas

Duplexer

76 GHz VCO LO

IF Output

A/D FFT

Mixer

c df Td

Transmitted Range
=
2

2

F1)
RF Freq
(F

wave Target Echo





F2

F1 df


TD Td

time

IF Freq


df+f
Dop


df-f
Dop


time


Figure 5: Typical FMCW Radar [17]

11
1.6.2. FSK

A second type of ACC radar utilizes a FSK mode of operation. This type
of radar is a variant of the FM-CW radar. The radar transmits a CW
signal whose frequency is changed by typically 150 to 500 KHz every
microsecond as shown in Fig. 6. The I.F. output is processed in a similar
manner to the FM-CW radar. The phase difference between the transmit
and receive signals will contain the range information, and the Doppler
information is contained in the I.F. Frequency. Due to the type of
processing performed, FSK radars usually only respond to Doppler-
shifted return signals (i.e. signals from targets moving relative to the
radar).
Transmitter Duplexer


LO Antenna




Mixer

Frequency
Transmitted signal



Radar return


f1


f2


Signal at mixer
time


Two radar signals with a difference frequency will have different phase delay

depending upon the range to the target. The phase difference = X-R.nge/C
Magnitude
-








Frequency f1
Range or time



Frequency f2
Phase difference gives range
1 degree = 1.5 meters


Figure 6: Typical FSK Radar [17]

12

1.6.3. Pulse Doppler Radar

The third type of radar used in the ACC application is the classic pulse
Doppler radar shown in Fig. 7. A simplified version of the block diagram
for five-beam radar is shown. The radar signal source alternates between
two frequencies separated by 200 MHz (the I.F. frequency). At time t = 0
the radar is at frequency F1. At time t = z, the transmit frequency changes
to F2 where it remains for a time period that is much greater than the
twice the propagation time to the furthest potential target. The delayed
echo from the target is demodulated in the mixer. The time delay between
the transmitted pulse and the pulse echo determines the range to the
target. The velocity can be determined from the rate of change of the
target position or by using coherent pulse Doppler techniques.

Antennas
76.5, 76.7 GHz


Mixer
Phase Lock
Circuits

IF Output
F1 F1

time
F2 F2

Delayed
Td Echo

time
F2-F1 F2-F1

time

Figure 7: Typical Pulse Radar [17]

13
1.7. Frequency Source for Millimeter-wave Automotive
Radar

For automotive radar sensor applications in a FMCW system, a low cost
wide-band voltage controlled oscillators (VCO) with a moderate tuning
range and low phase noise are needed. Typically a tuning range of l GHz
from 76-77 GHz with a phase noise of -80 dBc/Hz at the 100 kHz offset
is required for a VCO used [18].

For a stable millimeter-wave signal source, the signal generation can be
realized either directly by a voltage-controlled oscillator (VCO) or by
multiplication from a lower frequency. For 77 GHz automotive radar
systems, signals in the 77 GHz band must be stabilized with low phase
noise. The first approach has poor phase noise, so a phase locked loop
(PLL) is required. However, by using a PLL, usually the whole system
becomes too complex. Nevertheless, Infineon has recently demonstrated
encouraging results, by producing fully integrated SiGe VCOs with
powerful output buffer for 77 GHz automotive radar system [16]. This
VCO has the following features:

Chip size: 0.8 x 1.2 mm
2
,

Center frequency: 77 GHz,

Tuning range: 6.7 GHz,

Phase noise: -97dBc/Hz at 1 MHz offset frequency,

Output power (2 outputs): 18.5 dBm

Single power supply: -5.5 V

Power consumption: 1.2 W

However, for achieving maximum output power, the output transistors
have been driven near to their practical limits, given by high-current
effects and avalanche breakdown. This design was possible with
deployment of adequate transistor models, which were capable of
detecting potential worsening of circuit performance by avalanche
breakdown.

The second approach, which is based on frequency multiplication,
increases the flexibility of the system design by using a low phase noise
technology in realizing oscillators of high spectral purity at lower
frequencies [19]. Frequency multipliers have been used in the past as
well and still they have attraction in building cost-effective and stable

14
sources at higher frequencies as long as technology allows comparable or
better results using direct realization of oscillators at higher frequencies.
Unfortunately, the phase noise performance is degraded during frequency
multiplication at the rate of 20 log(N) where N is the multiplication
factor. A doubler will degrade the phase noise by 6 dB, a tripler about 10
dB and 10-times multiplication will degrade phase noise by 20 dB
equating to about 6 dB per octave.
This thesis work is focused on design of frequency doubler circuits in
SiGe technology at 20 GHz and 40 GHz frequencies targeting automotive
radar application.


































Figure 8: RF-front end of FMCW automotive radar

For a FM-CW modulation, a typical RF front-end of automotive radar is
shown in Fig. 8. In the block diagram, VCO at 40 GHz followed by a
frequency doubler is used to achieve the frequency source of 80 GHz.


15
The frequency doubler and the following buffer are marked in the block
diagram to emphasize scope of the presented thesis work

In fact, other frequency multiplier circuits e.g; frequency tripler or
frequency quadrupler can also be used with corresponding low frequency
oscillators. However, the use of frequency multiplier circuits with even
higher multiplication factors is rare due to their low conversion gain and
poor efficiency.

The following chapter includes discussion on basics of frequency
multipliers and their common architectures.










































16














Chapter-2



Frequency Multiplier Architectures

































17























































18
2.1. Introduction

Nonlinear operations on continuous-valued analog signals are often
required in instrumentation, communication, and control-system design.
These operations include rectification, modulation, demodulation,
frequency translation, multiplication and division. RF frequency
multipliers are nonlinear devices that produce an output signal with a
frequency that is larger than the frequency of a corresponding input
signal by a predetermined factor. RF frequency multipliers operate over a
specific input frequency range and are able to suppress or reduce
unwanted harmonics from the output signal. There are two basic types of
devices: active and passive. Passive RF multipliers produce an output
signal with a power level that is smaller than that of the input signal. The
difference in power levels between the output signal and the input signal
is called conversion loss, an amount that is expressed in decibels.
Conversion loss is a negative number, but usually specified as an
absolute value. Active RF multipliers may produce an output signal with
a power level that is larger than that of the input signal. The power level
difference between the output signal and the input signal is called
conversion gain, an amount that is measured in decibels (dB) and
expressed as a positive number.

Performance specifications for RF frequency multipliers include
multiplying factor, input power, output power and spurious rejection.
Frequency doublers, triplers, quadruplers and quintuplers are commonly
available. The input power is the amount of RF power that must be
applied to a device in order to multiply the frequency of the input signal.
It is also the specified power range for the conversion loss. Both output
power and input power are expressed in decibels relative to one milliwatt
(dBm). Spurious rejection is the difference between the desired output
harmonic and any other harmonic which can be seen at the RF
multipliers output. It is usually expressed as a positive ratio in decibels
relative to the carrier power (dBc).

2.2. Passive multipliers

Passive multipliers are popular for the simplicity of their structure
(usually a diode), for the reliability of the nonlinear frequency-
multiplying element, and for the very high maximum frequency of

19
operations. Quite naturally, the frequency multiplication cannot yield any
conversion gain, but only losses; which is partly compensated by the low
or zero DC power consumption. The cascading of an amplification stage
can balance the power budget, but requires two circuits for the complete
treatment of the signal. Both the circuits are reasonably well established
now, and a reliable design can be performed. However, compared to an
active implementation, it adds complication to the circuitry.

Passive multipliers can be classified as resistive or capacitive (or reactive,
in general) types [20]. In the first case, the frequency-multiplying
mechanism is the strong nonlinearity of the conduction current in the
diode. In the second case, the frequency-multiplying mechanism is the
nonlinear nature of the reactance of the diode, typically the junction
capacitance. In this latter case, the depletion capacitance in reverse bias is
used as nonlinear reactance in order to avoid the conduction current
present when the diffusion capacitance is not negligible. However,
especially at high frequency, both mechanisms are found to contribute to
frequency multiplication [21]. A semiconductor junction device which
has a nonlinear capacitance is known as a varactor. Such varactor-based
frequency multiplier circuits are widely used in parametric amplification,
mixing, detection, and voltage variable tuning. A great variety of diode
structures have been developed, especially for very high frequencies, that
can reach the THz range [2223]. Many structures have a back-to-back
arrangement and a symmetric C-V characteristic that allow zero-bias
operations and efficient frequency tripling. Resistive multipliers, in
principle, have infinite bandwidth, given the nonfrequency- dependent
nature of resistive nonlinearities. However, the associated junction
reactance and the reactive parasitic elements of the diode imply a
frequency-dependent behaviour of the element. Moreover, matching
networks will further limit the bandwidth.

2.3. Active multipliers

Active frequency multipliers are attracting a lot of attention as an
alternative to gain more signal power at a desired frequency and as a way
to implement frequency multipliers in integrated circuits. Frequency
multiplication is usually performed by generation of upper harmonics of
a fundamental frequency input signal. This is obtained by excitation of
strong nonlinearities within the semiconductor device. Classical active
frequency multipliers exploit the square-law characteristics of a FET or

20
the exponential I
C
-versus-V
BE
law of a bipolar by driving it into
compression and generating vast number of harmonics. In terms of
design issues for active frequency multipliers, the choice of the bias point
is critical for the efficiency and performance of the devices. While the
input is matched to the fundamental frequency, the output is matched to
the desired harmonic (e.g. 2nd harmonic for a doubler) with a short
circuit for the fundamental frequency (e.g. an open /2-stub). [24, 25]. A
simple emitter coupled pair of bipolar transistors can also act as
frequency multiplier.

2.3.1. Emitter Coupled Pair as Simple BJT multiplier

Emitter coupled pair as shown in Fig. 9 can be used as a simple
multiplier.





















Figure 9: Emitter-Coupled pair [26]


The output currents I
C1
and I
C2
depend on the input differential voltage
V
id
and their following relation can be proven [26]:
I
C1
=

I
EE

(2) V


1 + exp(

id
)

V

T

21

I
C 2
=


I
EE


1 exp(
V
id
)

+
V
T

where V
T
is the thermal voltage and I
EE

currents have been neglected.


(3)


is tail current, while the base

Equations (2) and (3) can be combined to give the difference current.
I

I I I

tanh(
V
id
) (4)

C 2
=
EE

C = C1 2V

T

The above relationship shows that the emitter-coupled pair by itself can
be used as a simple multiplier (Fig. 10 ).



















Figure 10 : The dc transfer characteristics of emitter-coupled pair [26]


With the assumption that the differential input voltage V
id
is much less
than V
T
we can utilize the following approximation
tanh(
V
id
)
V
id

V
id
1 (5)

2V

2V 2V <<

T T T

and equation (4) becomes
I

I (
V
id
) (6)
C EE

2V

T
22

The current I
EE
is the bias current of emitter-coupled pair. With the
addition of more circuitry, we can make I
EE
proportional to second input
voltage V
i2
as shown in Fig. 11.
































Figure 11: Two quadrant analog multiplier [26]


Thus, we have
I
EE
=

K
o
(V
i 2

V
BE (on )
)

(7)
Putting equation (7) in (6)

I

K (V V

) (
V
id
) (8)
C


o i 2 BE (on ) 2V

T




23
Under the assumption V
id
is small and V
i2
is greater than V
BE(on)
we
have come up to a relation that shows the multiplier function. The latter
restriction means that the multiplier functions in two quadrants of the V
id
-
V
i2
plane and this type of circuit is known as two-quadrant multiplier.

The restriction to two quadrants of operation is a severe one for many
communications applications, and most practical multipliers allow four-
quadrant operation. The Gilbert multiplier cell is a modification of the
emitter-coupled cell, which allows four-quadrant multiplication. It is the
basis for most integrated-circuit balanced multiplier systems. The series
connection of an emitter-coupled pair with two cross-coupled, emitter
coupled pairs produces a useful transfer function as shown in the next
section.

2.3.2. Gilbert Multiplier Cell

For the Gilbert cell shown in Fig. 12, we assume that all transistors are
identical and output resistances of transistors and that of biasing current
source can be neglected. The collector currents using equation (2) and (3)
are as follows
I
C 3

I
C1

(9)

=
1

V


exp(
1
)



V


+

T

I
C 4
=

I
C1
(10)

1 exp(
V
1


)



+ V
T


Similarly for Q
5
and Q
6


I
C 5
=

I
C 2

(11)

1 exp(
V
1


)




+ V
T


I
C 6

I
C 2
(12)

=
1

V


exp(
1
)



V


+

T

24





























Figure 12: Gilbert multiplier circuit

Similarly, I
C1
and I
C2
are related to V
2

I
C1
=


I
EE


1

exp(

V 2
) + V

T

I
C 2
=


I
EE

1 exp(
V
2

)

+
V
T


Putting values of I
C1
and I
C2
into equations (9)-(12)
I
C 3
=


I
EE


[1 exp(
V
1

)][1 exp(
V
2

)]


V


+
V
+

T T

25



































(13)



(14)








(15)
I
C 4
=

I
EE

(16)
[1 exp(

V
2

)][1 exp(

V
1
)]




V


+ + V

T T

I
C 5
=

I
EE

(17)
[1 exp(

V
1

)][1 exp(
V
2

)]



+ V
T
+ V
T


I
C 6
=

I
EE

(18)
[1 exp(

V
2


)][1 exp(

V
1

)]



+ V +
V


T T


The differential output current is then given by

I =

I
C 35

I
C 46
=

I
C 3
+

I
C 5

(I
C 4
+

I
C 6
)


I =

(I
C 3

I
C 6
)

(I
C 4

I
C 5
)

(19)
I I tanh(
V
1

) tanh(
V
2

) (20)
EE

2V

= 2V

T T


The dc transfer characteristics, then, is the product of the hyperbolic
tangent of the two input voltages. There are three main applications of the
Gilbert cell depending of the V
1
and V
2
range compared to V
T.


If V1<VT and V2 < VT, the hyperbolic tangent function can be

approximated as linear and the circuit behaves as a multiplier developing the

product of V
1
and V
2
.

If one of the inputs of a signal that is large compared to V
T
. This

effectively multiplies the applied small signal by a square wave, and acts as a
modulator.

If both inputs are large compared to V
T
, and all six transistors in

the circuit behave as non-saturating switches. This is useful for

the detection of phase differences between two amplitude-limited
signals, as it is required in phase-locked loops, and is sometimes
called the phase-detector mode.



26
Thus, for small-amplitude signals, the circuit performs an analog
multiplication. Unfortunately, the amplitudes of the input signals are
often much larger than V
T
. An alternate approach is to introduce a
nonlinearity that predicts the input signals to compensate for the
hyperbolic tangent transfer characteristic of the basic cell. The required
nonlinearity is an inverse hyperbolic tangent characteristic [26]. This
technique is used in so-called four-quadrant analog multipliers.

2.3.3. Common Frequency Doubler Circuits

After describing some basics of active frequency multipliers, the
following discussion will be focused on frequency doubler circuits
(multiplication factor =2 for frequency multiplier). It is important to
discuss research work, which has been carried out on frequency doublers
by now.

Bipolar frequency doublers often use a push-pull design, where both
outputs of a balanced input buffer are connected together to drive a single
common emitter HBT operated in class-B mode, where the output match
again is optimized for the 2nd harmonic [27]. These designs provide a
single ended output and good efficiency.

The research presented in [28][32] all takes the same approach of using
the nonlinearities of a transistor biased to operate in a class-B
configuration. This generates an output current rich in harmonic content.
The research in [31] is an unbalanced design that uses only a matching
network at the second harmonic and has an output power of 3 dBm and a
low fundamental suppression of 11 dB. In [28][30], the fundamental
suppression is improved despite the unbalanced design with the use of an
output resonant stub. A class-E unbalanced doubler was also presented in
[33] with high conversion efficiency, but it was not a monolithic-
microwave integrated-circuit (MMIC) or RF integrated-circuit (RFIC)
design.

In a balanced design, a higher output power can be obtained because of
the additional swing that differential operation allows. However,
differential operation requires a 3-dB increase in the input drive level and
the dc power. The balanced topology also has the advantage of achieving
broad-band fundamental suppression without the use of a resonator
structure at the output [34] and it is easily integrated with a differential
oscillator. An example of balanced operation is [35], where linear

27
multiplication is used to achieve doubling by connecting the local
oscillator (LO) and RF ports of a Gilbert cell together. The research in
[32] is also a balanced design, but operates in a class-B configuration and
good fundamental suppression is achieved due to the balanced topology.

The performance of a doubler can be further improved by using a second
harmonic reflector at the input of the transistors. This increases the
conversion gain at the expense of a decrease in bandwidth and increase in
circuit area. For this reason, input reflectors are seldom used in
monolithic designs. However, with accurate electromagnetic design to
account for parasitic coupling paths, miniaturized input reflectors can be
used to improve the performance of a monolithic doubler without a
significant increase in area.

Depending on the topology used, there are tradeoffs between area,
bandwidth, efficiency, and output power. Although the active doublers
referenced above all achieve conversion gain, their power-added
efficiencies (PAEs) are generally quite low. Frequency doublers have
been implemented using field-effect transistor (FET) devices such as
GaAs high electron-mobility transistors (HEMTs) [28], pseudomorphic
high electron-mobility transistors (pHEMTs) [29], InP HEMTs [30] or
silicon-on-insulator (SOI) CMOS [31], while some designs are realized
using HBT devices like InGaP [32] or SiGe [35]. SiGe HBT devices are
more nonlinear than HEMT devices and result in excellent conversion
gain and low-cost designs.






















28











Chapter-3



The Design of 20-GHz Frequency Doubler
and Output Amplifier Circuit


































29




.

















































30
3.1. Introduction

The frequency doubler circuits at 20 GHz have been designed using SiGe
BiCMOS process that allows CMOS logic to be highly integrated with
ultra high performance hetero-junction bipolar transistors (HBJT) on
silicon germanium base making it optimal for mixed-signal and RF
circuits. Hetero-junction bipolar transistors have significantly higher
forward gain and lower reverse gain which translates into better high
frequency performance than typically available from homo-junction or
traditional bipolar transistors. With a hetero-junction technology, the
opportunity for band gap tuning exists which has normally been available
only to compound semiconductors. SiGe processes achieve costs that are
similar to silicon CMOS manufacturing versus other more expensive
hetero-junction technologies such as GaAs.

3.2. Circuit Specifications

Specifications for the frequency doubler and amplifier circuit at 20 GHz
are given in Table-2. Parameters that have priority are conversion gain,
fundamental suppression and NF. Input and output impedances should
PDWFK WR

Table-2: Specifications of 20 GHz frequency doubler circuit
Parameter Min Typ Max Unit
Supply voltage 1.8 V
Power supply current 50 mA
Conversion gain 5 dB
Fundamental suppression 20 dBc
Noise figure 8 dB
IIP3 6 dBm
RF input power -8 -5 -2 dBm
RF input frequency 19.25 20.25 GHz
RF output power -3 0 3 dBm
RF output frequency 38.5 40.5 GHz
Input and output impedances 50
S11, S22 -15 dB
Temperature range -40 27 85 C
o





31
3.3. Proposed Single-ended Circuit

The 1.8 V supply voltage was one of the driving factor to select an
appropriate architecture for frequency doubler. For example, Gilbert
multiplier cell cannot be implemented here due to low supply voltage as
it is not possible to stack more than two transistors. The proposed circuit
has the classical approach of using the nonlinearities of a transistor pair
biased to operate in a class-B configuration. As already discussed,
biasing of transistors in such a case is very critical. The circuit shown in
Fig. 13 is driven by a differential signal and produces single-ended
output. A common-emitter amplifier is used at output stage, which will
drive the load. Input and output impedance matching networks are also
shown. Both CMOS and bipolar transistors have been used to take
advantage of SiGe BiCMOS process.




























Figure 13: Frequency doubler based on class-B configuration and output amplifier [37]








32

3.3.1. Design Methodology

Q1 and Q2 operating closed to class-B configuration are serving as the
doubling stage while Q3 is used to build common-emitter circuit required
for amplification of the 2
nd
harmonic signal generated in previous stage.
The use of a cascode amplifier as the output stage could have helped in
reducing the Miller effect along with amplification of the signal from the
doubling stage [37]. But the low supply voltage limits the number of
transistors to be stacked precluding thereby a cascode amplifier from this
design.

M1, M2 and M3 are CMOS transistors used as active loads and they are
controlling base currents of Q1, Q2 and Q3 respectively. M4, M5 and
M6, M7 build current mirror circuits required for controlling currents
I
CM1
and I
CM2
in doubling and amplification stages respectively. For dc
biasing and dc current control, CMOS transistors are used due to their
superior behavior over bipolar transistors in terms of power consumption.
The doubling stage is biased close to class-B (V
BE
= 0.8 V). The size of
the transistors can be determined by considering the relationship between
the output power and dc power consumption. The harmonic component
of collector current is a function of conduction angle, which can be
controlled by the input driving power and the base bias point [37].














Figure 14: Collector current modelled as a train of rectified cosine pulses [38]


The collector current can be modelled as a train of rectified cosine pulses
as shown in Fig. 14 and using the Fourier series expansion, it can be
represented as [34]


33

I
c
(t )
=
I
o

+
I
1
cos (w
1
t )
+
I
2
cos (w
2
t )
+
....

where I
n
is the nth harmonic current component ()


I
o
=

I
max
4t
o


T

I
n

=
0, for odd n



cos
n t




8t
o

o

T
, for even n

I
n =
I
max T
2




1
2nt
o





T


(21)





(22)







(23)
and I
max
is the maximum current, t
o
is the length of the pulse, T and is
the period corresponding to the fundamental frequency. To maximize the
amplitude of the second harmonic, the conduction duty cycle for each
transistor was chosen to be t
o
/T = 0.32.
All bipolar transistors were initially sized for optimum collector current
density and their optimum size was used throughout the design with
Cadence tools.

3.3.2. Improvement by Second Harmonic Reflector

The performance of a doubler is further improved by using a second
harmonic reflector at the input of the transistors. This increases the
conversion gain at the expense of a reduced bandwidth and larger circuit
area [38]. For this reason, the input reflectors are seldom used in
monolithic designs. However, when the parasitic coupling paths are
carefully account for, miniaturized input reflectors can be used to
improve the performance of a monolithic doubler without a significant
increase in area. Parasitic feedback at the second harmonic is important
to the doubler performance because the position of the reflector
determines the phase of the reflected signal, which interferes either
constructively or destructively with the desired output signal [39].




34
For the current design, passive elements L
r
and C
r
have been used to act
as a second harmonic reflector. Simulation shows an improvement of
about 3dBm in conversion gain when second harmonic reflector circuit is
optimized over L
r
keeping C
r
constant. Impedance matching at the input
and output ports is also carried out using passive elements. The design
values of all passive elements are given in Table-3.

Table-3: Design Parameters of 20 GHz frequency doubler circuit
Parameter Value Unit
Lp1 476 pH
Ls1 125 pH
Cs1 400 pF
Cs2 400 pF
Cs3 400 pF
Ls3 42 pH
Lchoke 100 pH
Lr 46 pH
Cr 125 fF

Physical sizes and shapes of inductors have been investigated using a
built-in inductor modelling tool available with the process design kit. The
MIM capacitors provided are between consecutive metal layers.

3.3.3. Simulation Results

For conversion gain (S21) and NF measurement, a combination of PSS
(periodic steady-state) and PSP (periodic scattering parameters) analysis
was used. Fig. 15 shows that the conversion gain varies with the input
power and its maximum value is around 14 dB for -9 dBm at the input.
Practically, the optimum operating input power would be between -10
dBm to -8 dBm. This operating range also ensures minimum NF, which
is around 12 dB.

PSS and PSP analysis were also used to estimate the conversion gain and
NF at fixed input power = -8 dBm over the whole input frequency band
(19.25 GHz 20.25 GHz). The result shown in Fig. 16 indicates that NF
remains almost constant throughout the band while conversion gain at the
maximum frequency degrades by 1 dB as compared to the gain at
minimum frequency.



35
The output frequency spectrum is plotted in Fig. 17 by taking DFT of the
signal. The fundamental suppression is around 32 dBc (the vertical scale
of the plot is logarithmic. Another strong harmonic is the 4
th
harmonic at
80 GHz which is separated by 16 dBc.


S21 and NF Versus Input Power

Input Frequency = 20 GHz

18

S21 (dB)
15



NF (dB)
12


9

6

3

0

-15 -12 -9 -6 -3 0
Input Power (dB)



Figure 15: Plot of Conversion Gain and NF versus input power


6 DQG 1) 9H UVXV ,QSXW ) UHTXH Q

,QSXW 3RZH U
G%P
18.00
15.00
S21 (dB)
NF (dB)
12.00
9.00
6.00
19.00 19.30 19.60 19.90 20.20 20.50
Frequency (GHz)


Figure 16: Plot of Conversion Gain and NF versus frequency

36





Output Frequency Spectrum
Input = 20 GHz @ -8 dBm
1.00E+00
1.00E-01
1.00E-02
DFT
1.00E-03
1.00E-04
1.00E-05
1.00E-06
0 20 40 60 80 100
Frequency (GHz)


Figure 17: Output frequency spectrum for input signal of -8dBm at 20 GHz


S11 and S22 are plotted in Fig.18 and 19, respectively.



Input Impedance Matching
Input Power = -8 dBm
-20.00


-25.00


(
d
B
)

-30.00


-35.00


S
1
1


-40.00




-45.00



-50.00


19.00 19.30 19.60 19.90 20.20 20.50

Frequency (GHz)


Figure 18: Input impedance matching

37


Output Impedance Matching
Input Power = -8 dBm
-20.00

-30.00

(
d
B
)

-40.00


S
2
2

-50.00


-60.00

-70.00

38.00 38.60 39.20 39.80 40.40 41.00

Frequency (GHz)


Figure 19: Output impedance matching

To summarize, the circuit consumes 54 mA average DC current at 1.8 V
supply voltage, it has 14 dB conversion gain at -9 dBm input and keeps
the fundamental tone 32 dBc apart from the desired harmonic.

3.4. Proposed Differential Circuit

The differential frequency doubler circuit as shown in Fig. 20 utilizes an
emitter-coupled pair as its basic cell. This doubler circuit was first
introduced by Ogawa and Kusakabe in 1978 [40]. This circuit consists of
two identical unbalanced emitter-coupled pairs with emitter area ratio K.
A differential amplifier formed by Q5 and Q6 is used at the output stage
to amplify the 2
nd
harmonic tone.

One of emitter-coupled pairs is formed by Q1 and Q4 having unity size
while Q2 and Q3 have larger size with relative ratio K and act as second
emitter-coupled pair. M1 and M2 are active CMOS loads for biasing the
bipolar transistors. There are three current control circuits placed at the
bottom of the circuit to control current in two-emitter coupled pairs and
the differential amplifier. For simplicity, impedance matching networks
used at the input and output ports are not shown in the schematic.



38
























Figure 20: Frequency doubler consists of two identical unbalanced emitter-coupled pairs with emitter
area ratio K and differential amplifier

3.4.1. Circuit Description

Assuming bipolar devices are matched and that the base-width
modulation is ignored, the differential output current of the frequency
doubler can be expressed as [42, 43].

I

I

tanh
V
in
V
K

tanh

V
in
V
K

(24)
FD

F O


+








=



2V
T
2V
T




2
F
I
o
sinh
V

K



V
T
(25)
I
FD
=
cosh


V in
+
cosh
V
K




V
T
V
T


2
F
I
o
K

1






K



(26) I
FD

=
2 cosh
V in
K
1



V
T
+
+
K



39

where
VT is thermal voltage equal to kT/q, k is Boltzmann's constant, T

is absolute temperature in degrees Kelvin, q is charge of an electron,

a
F
is dc common-base current gain factor

V
k
is offset voltage deriving from the unbalanced constitution and

defined as V
K
= V
T
ln ( K ) .



V
in
is the differential input voltage


Using
1
1 X .....( | X |

| 1 ) , expanding (26)



1 X =

<<


K
1


cosh(
V

in
)







K



2


V
T




I
FD

F
I
o





1

1


1

1
...
=


K

+ K



K




2 + K



Using

cosh(x )
=
1
x
2
x
4

+
.....(x
2


<
)



+ 2 + 12

I

2

I
K
2

1

1
2K
1


V
in
2

V
in
2
... ...
FD

F o


=

( K
2
1)
K

2
1 + 2
V
T

2
+ 12V
T

4
+



+ +


K
2
1

2

4




2
V
in
V
in

I

2

I

K

1 K

K

...



(
K

2


FD
=
F
o
1 )
2

(

)
V
T

2
6V
T

4


+









(27)








(28)




(29)

The differential output current is expressed as a function of the square of
the differential input voltage. Fig. 21 shows dc transfer curves of the
frequency doubler, calculated using (24) with various values of parameter
K. For a small input voltage the transfer curve is approximately a
parabola. Therefore, the input frequency is doubled by this circuit.










40























Figure 21: DC transfer curves of frequency doubler [43]

3.4.2. Optimum value of size ratio K

Size of Q1 and Q4 was selected as 1 m. The optimum value of size ratio K
was found by simulations. The value

selected for K is 6 as shown in Fig.

22 and the doubler conversion gain is maximum at that point. This
determines the size of Q2 and Q3 as 6 m.


Size ratio versus gain
Frequency = 20 GHz, Pin = -10dBm


12



10


S
2
1
(
d
B
)

8


6




4



2


0 2 4 6 8 10

K (re lativ e size ratio)



Figure 22: Relative size ratio K versus gain

41

3.4.3. Simulation Results

Again, PSS and PSP analysis were used to estimate the conversion gain
(S21) and NF. Fig. 23 shows that conversion gain varies and its
maximum value is around 11.5 dB when the input power reaches -6 dBm.
So practically, the optimum operating input power would be between -8
dBm to -5 dBm. This operating range also ensures minimum NF, which
is around 13 dB.

The output frequency spectrum is plotted in Fig. 24 by taking DFT of the
output signal. The fundamental suppression is at the lower side equal to
15 dBc (the vertical scale of the plot is logarithmic). Another strong
harmonic is the 4
th
harmonic at 80 GHz which is separated by 13.5 dBc.



S21 and NF Versus Input Power

Input Frequency = 20 GHz


18


S21 (dB)
15




NF (dB)
12



9



6


3

0

-15 -12 -9 -6 -3 0

Input Power (dB)




Figure 23: Plot of Conversion Gain and NF versus input power










42
Output Frequency Spectram
Input = 20 GHz @ -6 dBm

1.00E+00

1.00E-01

1.00E-02

D
F
T

1.00E-03

1.00E-04



1.00E-05

1.00E-06

1.00E-07
0

20 40 60 80 100
Frequency (GHz)


Figure 24: Output frequency spectrum for input power -8dBm at 20 GHz


Another limitation of the differential circuit is that its output is pseudo-
differential so it is not truly balanced. Fig. 25 indicates an offset present
between differential output signals.


Differential Output Signals

2.1

2.0

(
V
)

1.9


V
o
l
t
a
g
e

1.8

1.7


1.6

1.5

0.00 100.00 200.00 300.00 400.00
Time (psec)



Figure 25: Pseudo-differential output signals



43
Table-4 represents a summary of the simulation results for single-ended
and differential frequency doubler circuit. As indicated, the differential
architecture does not show promising results as compared to the single-
ended. In fact, the reason for using the differential architecture is the
requirement for the doubler circuit to be differential so that it can be
connected to the output of a differential VCO directly.

Table-4: Summary of simulation results for20 GHz frequency doubler circuits
Input Conversion Fundamental
NF
DC


Range Gain Suppression Current


Circuit

dBm dB dBc dB mA





Single-ended -10 to -8 14 32 12 54


Differential -8 to -5 11.5 15 13 75





































44














Chapter-4



The Design of 40-GHz Frequency Doubler
and Output Amplifier Circuit































45























































46
4.1. Introduction

With modern silicon technology, it is possible to build complete front-
ends including antenna arrays in monolithic integrated silicon
technology. The SiGe hetero-junction bipolar transistor enables the
break-through in Si based MMIC (Monolithic Millimeter-Wave
Integrated Circuit) technology. The SiGe hetero-junction bipolar
transistor technology with transit frequencies beyond 200 GHz allows
realization of oscillators, mixers, modulators and demodulator circuits for
80 GHz operating frequencies [44]. The short wavelength allows
integrating complete antenna arrays on one silicon substrate together with
antenna feed, mixer and oscillator circuits. The complete front-end
integration reduces costs and the requirements for fabrication tolerances.
MMICs can be fabricated with high precision concerning geometric
dimensions and material parameters. This minimizes phase errors and
allows a precise beam forming in antenna arrays.

Monolithic integration of solid-state devices provides the possibility of
low-cost production, improved reliability, small size, light weight, and
easy assembly. A broader application of millimeter-waves in sensors and
communications has been hampered until now due to the high costs of
millimeter-wave components. This situation may change in the future due
to the availability of low-cost monolithic integrated components based on
a silicon and SiGe technology.

The frequency doubler circuit at 40 GHz has been designed using
Infineons B7HF200 SiGe bipolar technology. Some technical details of
this process are discussed below.


4.2. Technology Details

B7H200 is a SiGe bipolar process with copper metallization for mixed
analog/digital HF applications which provides high performance at low
power consumption. The process provides high speed HBT (f
T
=200GHz)
as well as standard NPNs with a 4 metal (copper) layer interconnect. The
maximum supply voltage is set by the open-base collector-emitter
breakdown voltage and short-base collector-emitter breakdown voltage.
The collector-emitter voltage over any transistor should observe this

47
limitation. Compared with GaAs, power consumption in SiGe will be
considerably smaller. This seems advantageous for mobile/automotive
applications but also limits the maximum output power capability.

4.3. Circuit Specifications

Design specifications for the 40 GHz frequency doubler and amplifier
circuit are tabulated in Table 5.

Table-5: Specifications of 40 GHz frequency doubler circuit
Parameter Min Typ Max Unit
Chip area (doubler + amplifier) 1 mm
2

Supply voltage 5 V
Power supply current 30 mA
Conversion gain 8 dB
Fundamental suppression 20 dBc
Noise figure 8 dB
RF input power -10 -8 -5 dBm
RF input frequency 38.5 40.5 GHz
RF output power -2 0 3 dBm
RF output frequency 77 81 GHz
Input and output impedances 100
S11, S22 -15 dB
Temperature range -40 27 85 C
o


The frequency doubler should
differential input and differential should
be 100 HTXLYDOHQW WR
ground).

have balanced architecture with
output. The differential impedance
EHWZHHQ VLQJOH-ended circuit and

4.4. Design Considerations

From the design point of view, there are three major changes in
Infineons B7hF200 technology compared to SiGe BiCMOS process.
First, the supply voltage rather than 1.8V is equal to 5V which
facilitates to explore other architectures whose implementation was
not possible with low supply voltage. Second, as of a pure bipolar
process, CMOS transistors are no more available and third, with this
process the inductors are not available which puts some restriction on
using excess number of inductors in a design. However, the process

48
supports design of transmission line implemented as a micro-strip line
with the ground plane as a lower metallization layer.
For designing a frequency doubler circuit at 40 GHz, let us first
consider possibility of employing the same architectures which were
used for 20 GHz circuit.

The emitter-coupled pair followed by a common-emitter

amplifier circuit (single-ended architecture) demonstrated

promising results and with availability of 5V supply voltage.
The common-emitter amplifier can be replaced by a cascode
amplifier in order to reduce Millers effect and improve the
performance further. However, the 40 GHz frequency doubler
circuit needs to be balanced, so the single-ended circuit should
be modified to make it differential. The most decisive factor is
the presence of a few inductors which makes realization of
this architecture difficult in B7HF200 process.

The performance of the differential architecture is not as good

as that of the single-ended circuit. The pseudo-differential output

also does not match the requirement of being truly balanced.


The above factors give rise to explore some other balanced
architectures suitable for a frequency doubler circuit at 40 GHz.
One possible approach is in using an up-convertion active mixer,
with the RF and LO ports fed by the same signal, i.e. the ports
should be tied together [45]. If the undesired products of mixing
are filtered out, the output provides the input frequency doubled.
Gilbert active mixer, which is a balanced architecture is a suitable
candidate for this application (Fig. 26).


LQ /2
$FWLYH 0L[HU


)LOWHU


H J *LOEHUW &HOO


5)


Figure 26: Use of active mixer as frequency doubler

49
4.5. Proposed Architecture

The proposed architecture for the frequency doubler at 40 GHz uses
Gilbert cell with an additional buffer stage at the input and a differential
amplifier at the output as shown in Fig. 25. The emitter-followers at the
input stage act as buffer and will avoid loading of VCO which will drive
this circuit.
(PLWWHU
/2
*LOEHUW &HOO
)LOWHU
4:9
'LIIUQWLDO

)ROORZHU $PSOLILHU


(PLWWHU
5)



)ROORZHU




Figure 27: Proposed architecture for frequency doubler at 40 GHz

The signal to RF port is connected through an extra emitter-follower
stage as the arrangement helps controlling signal level at the RF port. The
voltage gain of the emitter-follower being less than unity keeps the signal
at RF port smaller than the signal at LO port for proper mixing operation.

4.6. Design Description

The circuit can be divided into four parts, input buffer stage, Gilbert
mixer cell, filter and the output amplifier stage. The description of each
part is as follows:

4.6.1. Input Buffer Stage

The purpose of this stage is to avoid loading of VCO. Emitter-follower
(common-collector configuration) is well renowned circuit that has high
input impedance, low output impedance and near-unity gain. It is most
widely used as an impedance transformer to reduce loading effect
between a signal source and a load.

Characterization of the emitter follower circuit by the corresponding
equivalent two-port network is not particularly useful for intuitive

50
understanding as input resistance depends on the load resistance and
output resistance depends on the source resistance [26].

An emitter-follower circuit that includes source resistance R
S
and load
resistance R
L
is shown in Fig.27. From a large-signal point of view, the
output voltage is equal to input voltage minus the base-emitter voltage.





















Figure 28: Emitter-follower circuit (common-collector configuration) [26]

For small-signal analysis, hybrid- WUDQVLVWRU PRGHO LV VKRZQ LQ )LJ 29.


















Figure 29: Small-signal equivalent circuit of emitter-follower circuit [26]


Small-signal gain of this circuit is given by following relation [26]:

51

v
o
=
1
(30)



v
s
R
s

r



1
+

o
+

1
+

R
L
+

r
o


If r R , 1 and rR then (30) can be approximated as

S

0

0

L


v
o
g
m
R
L

(31)


v
s
1
+
g
m
R
L







From (31) we infer that the emitter-follower gain is slightly less than
unity. In the current design, two identical emitter-followers have been
used one in each path for differential architecture. The RF port of Gilbert
mixer is buffered by an additional emitter-follower stage that has one
extra resistor between collector and supply voltage to control signal level
at the RF port. Minimum transistor sizing for the emitter-follower circuit
has been used to keep the input impedance high. R
L
has been selected to
match the optimum density of the collector current and thereby to boost
the Gilbert cell performance.

4.6.2. Gilbert Cell

A circuit representing the Gilbert bipolar mixer cell is shown is Fig. 30.
Its application as the frequency multiplier has already been discussed in
Chapter 2.

The following relation for the differential output current holds:
I I
EE

tanh(
V
LO
) tanh(
V
RF
) (32)

= 2V
T
2V
T




Here, both RF and LO ports are fed by the same signal except for the
additional emitter-follower stage in RF path. For simplicity, we assume
the gain of the emitter-followers as unity and take V
LO
=V
RF
=V
in








52




























Figure 30 Gilbert mixer


I I tanh
2
(
V
in
) (33)

2V

= EE

T




and the differential voltage across load R
L
is


2
V
) (34) V =

I
EE
R
L

tanh

(
in
2V
T


Hence, the circuit gain is given by

I

R
L

tanh
2
(
V
in
)

EE

V 2V
T
(35)

=

V
in

V
in





53

I
EE
R
L

tanh
2
(
V
in
)



2V
T


G = 20 log


(36)

V


in












For simplicity, we take

I
EE
R
L
= 1 and V
T
= 26 mV (at room temperature)

tanh
2
(
V
in
)



0.052

G 20 log

(37)

=
V
in




The simplified gain expression can be plotted against the input voltage as
shown in Fig. 31. We see that the Gilbert cell gain is nowhere constant
but it has partly parabolic and partly hyperbolic shape. When this circuit
is used in frequency doubler application, the parameters that define
linearity of the circuit like 1dB compression point or IIP3 do not apply
because the gain varies with the input signal level. The input voltage
range over which circuit performance is optimum can be defined.






















Figure 31: Variable gain of Gilbert mixer in frequency doubler circuit



54
If we denote gain of the two emitter-follower stages as A
1

the differential output voltage across load R
L
is

AV
in
A A V

V R I
EE

tanh(
1
) tanh(
1 2 in
)
2V

2V

= L

T T



and A
2
then



(38)

4.6.3. Filter

To filter out undesired harmonics, a first order resonant circuit can be
placed at the output of the Gilbert mixer. Its resonant frequency is
matched to 2
nd
harmonic which is 80 GHz for the current design. The
resonant frequency of LC tank is given by


f
1
(39)



= 2 LC

If we take C=50fF and L=80pH, approximate value of resonant
frequency is 80 GHz.


Due to non-availability of inductors in B7HF200 technology, the required
inductive reactances can be realized by short microstrip lines with the
signal line in the fourth metallization layer and the ground plane in the
first or second layer. For lossless transmission lines with a real or virtual
short at its end, the effective inductance is given by [46]
L

Z
O
tan(2
l
) (40)
eff
= 2 f



where l is the line length, is the wavelength, Z
O
the characteristic line
impedance, and f the frequency. A high value of Z
o
(i.e., a thick dielectric
layer between the upper and lower metallization layers) is favourable due
to the reduced line length at given L
eff
. Consequently, the parasitic series
resistance is reduced, resulting in an increased quality factor of the
inductance.
The plot of the effective inductance of a lossless transmission line versus
its length (keeping l ) for different frequencies is shown in Fig. 32.
<< 4


55
Obviously, for l
<<

, L
eff
becomes independent of frequency and
proportional to l .


Transmission Line Effective Inductance

300.00

250.00
20 GHz



L
e
f
f
(
p
H
)

200.00
40 GHz


150.00

60 GHz

100.00

80 GHz



50.00
100 GHz



0.00


0 50 100 150 200 250 300 350


Length (um)



Figure 32: Effective inductance of a lossless transmission line for l< /4


For the current design, differential transmission line used is formed by
top metal (metal-4) and ground metal (metal-2) with Z
o
$s a starting
point, an approximate value for the length of transmission line was
determined equal to 202 um using (41). Each capacitor in the resonant
circuit has a value of 50 fF. The length of differential transmission line
was varied and filtering effect of corresponding resonant circuit was
observed with the help of CAD tool (Cadence). The transmission line
length at which the maximum conversion gain for the
current design was observed is 125 m.

4.6.4. Differential Amplifier

At the output stage, a differential amplifier has been used which is
probably the most often used type of an amplifier in integrated circuits.
The large signal analysis of this circuit (emitter-coupled pair) has been
discussed in Chapter 2. Here, our interest is in small signal behaviour
when the DC differential input voltage is zero. In this case, V
diff

represents the AC signal. In analyzing this circuit, we make the following
assumptions:



56
The magnitude of the input signal Vdiff is small enough that the

amplifier operates in the linear region.

The equivalent resistance of the biasing circuitry is finite.

r
o
for the transistors is much larger than R
C
and can be ignored in

our analysis.


It is convenient to define the input signal as a sum of two components, a
DC common-mode voltage and an AC differential-mode voltage. We are
interested in differential mode gain given by
A
d

v
od
g
m
R
C
(41)

= v


id
=



Ideally, the differential gain is high while the common-mode gain is zero.
We can get a feel for how close a practical circuit is to the ideal by
evaluating the common-mode rejection ratio.





























Figure 33: Differential Amplifier

The differential amplifier circuit used is shown in Fig. 33. A current
mirror circuit is placed at the bottom for biasing. The current of this
circuit is controlled by a limiting resistor R
CM
. Transistor sizes have been

57
selected to match optimum collector current density. The capacitors at the
input are a part of the preceding filter circuit. Due to AC coupling, the
transistor bases are biased through R
B
.

4.6.5. Integrated Circuit

Fig. 34 shows the integrated circuit by connecting together all parts of the
circuit and values of resistors and capacitors are given in Table 6.

Table-6: Design parameter values for 40 GHz frequency doubler circuit

Parameter Value Unit

RB1 300

RC1 200

RE1 100

RE2 200

RB2 10K

RC2 200

RCM1 400

RCM2 400

C
1
, C
2
600 fF

C
3
, C
4
50 fF

C
5
, C
6
300 fF

















58



















































Figure 34: Detailed circuit diagram for frequency doubler at 40 GHz



59
4.7. Layout of the Frequency Doubler Circuit

The layout of the circuit shown in Fig.33 was drawn in Cadence Layout
Editor using Infineons B7HF200 technology with some modifications.
The following modifications to the frequency doubler schematic were
performed.

Resistors RE1, RE2, RCM1 and RCM2 were first realized as poly

resistors (tolerance 20%). Their poor performance was noted

while running the corner analysis. For this reason each poly
resistor was replaced by a combination of TAN resistor
(tolerance 8%) and diode connected transistors.

The both current mirror circuits would be externally controlled

by implementing limiting resistor partly on-chip and partly by

external variable resistor. Two pads per current-mirror circuit
would be required for this arrangement.

Recommended external variable resistor value is 0-500 ohm,

(1% Tolerance); typical design value to be used is 200 ohm.

4.7.1. Layout Design Considerations

Following are some points which were considered while designing the
circuit layout.

Symmetry for differential design.
Power supply and ground paths routing in top metals (metal-03
and metal-04)).
Metal-01,metal-03 routing in one direction and metal-02,metal-04
in other direction.
Sizing of interconnects calculated depending upon current
densities of corresponding paths and maximum current flowing
through them.
Keeping RF interconnects as small as possible to reduce
attenuation.
Keeping minimum overlapping of consecutive metal layers to
reduce parasitic capacitances.
Used substrate connections on convenient places for isolation
(Guard-Ring).
Using decoupling capacitors at blank chip areas.

60
For testability of the frequency doubler circuit, the corresponding
baluns at the input and output are required for conversion of
differential signals into single-ended. The design of baluns is not a
part of thesis work however; some silicon area is left on chip for
addition of baluns later on.

4.7.2. Pad Frame

The area used by chip is 728 X 928 um
2
(0.68 mm
2
) including input and
output baluns. Following is the detailed description of different pads
used.
Area used = 0.68 mm
2

Total number of pads = 16, RF pads = 06, DC pads = 10

VCC Pads =02, GND pads = 04

Each pad size = 68 um 92 um

Pitch (center to the center distance between two consecutive pads) for RF
and DC pads used is 150 um. This pitch is required for connectivity of
RF-Probe on the chip at input and output RF pads. RF probe to be used
has standard GSG (Ground-Signal-Ground) configuration. The
arrangement of the pads is shown in Fig.35.

























Figure 35: Pad Frame

61
4.7.3. Emitter-Follower Layout

The layout of the input buffer stage is shown in Fig. 36. The length of
R
B1
(TAN resistor) is divided into three equivalent parts for efficient use
of the chip area. For differential architecture, symmetry has been
maintained.












































Figure 36: Layout of emitter-follower stage



62
4.7.4. Gilbert Cell and Filter Layout

The layout of the Gilbert cell and filter is shown in Fig. 37. The
transmission line occupies a significant area of the chip. The L-shape of
the transmission line is used for maintaining symmetry between
differential RF signals.














































Figure 37: Layout of Gilbert cell and filter

63
4.7.5. Frequency Doubler Core Layout

The layout of the frequency doubler core is given in Fig. 38. This layout
occupies 300 X 400 um
2
(0.12 mm
2
) of the chip area without baluns and
pads.













































Figure 38: Layout of frequency doubler core


64
4.7.6. Complete Layout

Fig. 39 displays the complete layout after adding substrate connections
and decoupling capacitors. The blank area is left for the input and output
baluns.





























Figure 39: Layout of complete chip

4.7.7. Layout Verification

The layout was verified using Diva design rule checker (DRC) and layout
versus schematic (LVS) tools provided in B7HF200 technology. The
layout performance is evaluated by simulating its extracted analog model
which includes all resistive and capacitive parasitics. The layout
verification process is shown in Fig. 40.







65
Layout

Diva-Design Rule Check

No


DRC


Yes
Results not


satisfactory



Parasitic Extraction Extraction

Simulation

No

Diva-Layout Versus Schematic Check LVS

Yes

Build Analog Extracted View
Meet

Specifications

Build Configuration View for Test Bench


Figure 40: Layout verification process



































66















Chapter-5



Schematic and Layout Simulation Results of
40-GHz Frequency Doubler Circuit






























67























































68
5.1. Introduction

In this chapter, the performance of 40 GHz frequency doubler circuit
discussed in Chapter 4 is evaluated. The test bench shown in Fig. 41
includes two external resistors to control current in the corresponding
current-mirror circuits. With a little change the same test bench can be
used for simulation of both schematic and layout. In case of layout, the
schematic block is replaced by the analog extracted view.





























Figure 41: Test Bench


5.2. Conversion Gain and NF

The analysis used a combination of PSS and PSP in Cadence Analog
Environment. As already discussed, the gain of the circuit is variable and
to determine the optimum operating input power range, the conversion
gain and NF were plotted against input power for center frequency at



69
room temperature. Plot for comparison of conversion gain for schematic
and layout is presented in Fig. 42.


S21 Versus Input Power

Fin=39.5 GHz

14.00

12.00

(
d
B
)
10.00

8.00


Schematic
S
2
1

6.00



4.00

Layout


2.00

0.00

-15 -12 -9 -6

Pin (dB)



Figure 42: Conversion gain versus input power


Fig. 43 shows comparison of NF for schematic and layout.


NF Versus Input Power

Fin=39.5 GHz

18

16

14

(
d
B
)

12

10


Schematic
N
F

8



6

Layout



4

2

0

-15 -12 -9 -6

Pin (dB)



Figure 43: NF versus input power

70
The conversion gain of layout achieves maximum (about 8 dB) when the
input power is around -8 dBm, while the conversion gain of schematic
has maximum (aboutt 12 dB) at -12 dBm input power.

NF for schematic and layout is plotted in Fig. 42. The degradation of
performance in gain and NF for layout is due to attenuation introduced by
interconnects and other parasitic effects.

5.3. Output Spectrum and Fundamental Suppression

An important figure of merit for a frequency doubler is its fundamental
suppression, usually expressed in dBc. A larger fundamental suppression
indicates a better spectral purity at the output. Discrete Fourier Transform
(DFT) analysis of the output signals for schematic and layout is presented
in Fig. 44 and Fig. 45, respectively. Vertical scale used in these plots is
logarithmic and the relative value at this axis between two components at
different frequencies may be taken as dBc. As seen the fundamental
suppression for schematic is 30 dBc which gets degraded to 25 dBc in
layout due to coupling effects through interconnects and parasitic
components.


Schematic Output Spectrum
Input 40 GHz@-8dBm
1.00E+00

1.00E-01

1.00E-02

1.00E-03

1.00E-04

1.00E-05

1.00E-06

0.00 40.00 80.00 120.00 160.00 200.00
Frequency (GHz)


Figure 44: Output spectrum of the schematic

71

Layout Output Spectrum
Input 40 GHz@-8dBm
1.00E+00

1.00E-01

1.00E-02

1.00E-03

1.00E-04

1.00E-05

1.00E-06

1.00E-07

0.00 40.00 80.00 120.00 160.00 200.00

Frequency (GHz)


Figure 45: Output spectrum of the layout


5.4. S11 and S22

Impedance matching networks at the input and output are not
implemented for the current design. Baluns (which will be added later
RQ PD\ EH GHVLJQHG WR PDWFK LPSHGDQFH RU
EHWZHHQ differential signals) at the input and output ports of the
frequency doubler circuit.

S11 and S22 are plotted in Fig. 46 and Fig. 47 as a reference for future
work on impedance matching.













72

























Figure 46: S11 plotted on Smith chart



























Figure 47: S22 plotted on Smith chart

73
5.5. Corner Analysis

Corner analysis is usually performed for integrated circuits to estimate
sensitivity of the circuit performance with regards to process variation. At
present, B7HF200 technology does not provide support for corner
analysis. However, the circuit was also analyzed at extreme temperatures
(-40C and 85C) other than room temperature (27C).

The conversion gain and NF are also plotted in whole frequency band at
different temperatures while keeping the input power constant at -8 dBm.
The results are displayed in Fig. 48 and Fig. 49.



S21 Versus Frequency

Pin = -8 dBm)

(

10.00

9.00


8.00



7.00
Schematic T=-40C

Schematic T=27C
S
2
1
(
d
B
)

6.00 Schematic T=85C
5.00

(
Layout T=-40C



Layout T=27C



4.00


Layout T=85C


3.00



2.00


1.00

0.00

78.00 79.00 80.00 81.00

Frequency (GHz)



Figure 48: Conversion gain versus frequency at different temperatures

The circuit performances (conversion gain and NF) degrade both when
temperature goes high (85C) and very low (-40C), i.e. they are non-
monotonic. However, the simulations performed on schematic only show

74
a monotonic performance decrease with temperature. This deviation may
be due to some parasitic effects.


NF Versus Frequency

(Pin = -8 dBm)

18.00

15.00
Schematic T=-40C

Schematic T=27C
N
F
(
d
B
)

Schematic T=85C
12.00
Layout T=-40C


Layout T=27C




Layout T=85C

9.00


6.00


78.00 79.00 80.00 81.00

Frequency (GHz)



Figure 49: NF versus frequency at different temperatures


Table 7 represents a summary of the performance for schematic and
layout circuits at different temperatures. The maximum variations of
conversion gain, NF and dc current within temperature range (-40C to
85C, as per specification) are also given. At normal room temperature the
schematic draws 34 mA DC average current while the layout circuit
draws 42 mA of DC average current.










75

Table-7: Circuit performance at different temperatures
Nominal Resistances

VCC = 5.0V


Frequency = 40 GHz



Parameter
Circuit Input power = -8 dBm


Temperature (degree)




-40 27

85
Maximum


Variation




S21 (dB)
Schematic 9.8 10.5 6.2 4.3 dB

Layout 6.3 7

2.7

4.3 dB



NF (dB)
Schematic 14.4 13.2 13.5 0.9 dB

Layout 13 11.7

14

2.3 dB



Current Schematic 33.2 34 35.1 1.9 mA

(mA)
Layout 43.1 42.2

45.5

3.3 mA

































76














Chapter-6



Conclusion and Future Work

































77























































78
6.1. Introduction

In this thesis work design of 20 GHz and 40 GHz frequency doubler
circuits was presented. For the latter circuit, post-layout simulations were
also provided. Table 8 represents comparison of this thesis work with
other reported frequency doubler circuits.

Table-8: Comparison of frequency doubler circuits

Fout
Pin
Pout C.G. PDC PAE F.S.
Chip Size


(dB without pads Ref

Device /f
T
(GHz) (dB) (dB) (mW) (%) (dB)

) (mm
2
)
(GHz)

SiGe HBT
38.5 -
-9 5 14 97 3.26 32
Schematic This

40.5 Results Work

/ 150



SiGe HBT
77-81 -8 2.5 10.5 210 0.85 25
0.4 0.3 This

(0.12) Work

/ 200



SiGe HBT
15.4-18 1.5 5-6 3.5-4.6 22-28 8-9.2 25
0.7 0.35
[37]

(0.245)

/ 80



SiGe HBT
34.6-
6 9-10.5 3-4.5 95-114
4.2-
35
0.7 0.5
[37]

37.6 6.4 (0.35)

/ 80



SiGe HBT
30 -12 -3.4 8.6 185 0.2 22
0.45 0.55
[35]

(0.248)

/ 85



GaAs
1.6 1.2


HEMT / 56 5 6 1 275 0.3 23 [28]

(1.92)

95


GaAs
1.4 0.64


PHEMT / 56 0 4 4 70 2.2 29 [29]

(0.9)

95


Inp
26.5
-
-2.5 5 26.5 1.7 16

- [30]

7.5

HEMT



InGaP
16 -5 5 10 200 1.4 25
0.7 0.4
[32]

(0.28)

HBT / 60



SOI
-

0.37 0.27


CMOS/ 27 -3 1.5 10 7.4 11 [31]

4.5 (0.1)

150




6.2. Key Points Learned

Following are some key points which describe the outcome of the
presented thesis work.

Automotive radar facilitates various functions that increase the

drivers safety and comfort. Although, few modern vehicles are

already equipped with this type of radar but once their production
cost gets down, such automotive radars will be very common.


79
Due to regulatory issues, the shift of frequency band from 24

GHz to 77 GHz for automotive radars is due until 2014.

Promising results in high frequency performance of SiGe
technology may lead to the development of low-cost automotive
radars at 77 GHz.

The frequency multiplier circuit will be one of the key

components used in combination with low a frequency oscillator for

generating cost-effective and stable signal source having low phase
noise.

Frequency multiplier circuits fall in the category of non-linear

circuits. Active devices should further be investigated for their non-

linear behavior for efficient implementation of the frequency
multiplier circuits.

A frequency multiplier is usually characterized by its conversion

gain, input power, fundamental suppression and dc power consumption.

Emitter-coupled pair is a basic cell often used in a frequency

doubler circuit. More often, class-B configuration has been used

in many designs. Gilbert mixer cell can also be used as frequency
doubler when both RF and LO ports of the mixer are tied together
and fed by the same signal.

For high frequency designs, special attention should be given to

symmetry of layout, interconnects, optimum current densities of

active devices, unnecessary crossing of metal lines carrying RF
signal lines to avoid coupling, use of guard-rings (formed by
substrate connections), impedance matching and grounding (EM
shielding) of the circuit.


6.3. Future Work

Following are some recommendations for the future work.

Single-ended circuit at 20 GHz (based on class-B configuration)

is efficient but it involves a few inductors. This limits the use of

this circuit in a technology where inductors are not supported.
This design needs some modification to keep the use of passive
elements at minimum.

Differential circuit at 20 GHz has poor fundamental suppression.

The circuit needs some filtering to keep the fundamental tone at the output as
small as possible.


80
The gain of the Gilbert mixer when used in the frequency doubler

application has strong dependence on thermal voltage when input

signal level is low. The performance of the circuit degrades at
high temperatures. The gain at two extreme temperatures (-40C
and 85C) varies around 3-4 dB. The circuit needs an extra
circuitry for temperature compensation to stabilize the circuit
performance against temperature.

As a high frequency design, the layout of frequency doubler

circuits should be verified using a reliable 3-D planer EM simulator tool.

For the testability purpose for frequency doubler circuits at 40

GHz, the design of baluns and impedance matching networks is required.

The symmetry of layout in the frequency doubler circuit at 40

GHz is affected by presence of the differential transmission line.

Some alternate routing plan may maintain symmetry and hence, it
can minimize risk of amplitude and phase mismatch between two
differential signals at the output.

Once the frequency doubler circuit is integrated with a

corresponding VCO (which makes a complete signal source) its

performance should be evaluated by measuring the phase noise at the
doubler circuit output.



























81























































82
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87





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88