WhitePaper

Avoiding PCB Design Mistakes in FPGA-Based Systems

SystemdesignusingFPGAsissignificantlydifferentfromtheregularASICandprocessorbasedsystemdesign. Inthiswhitepaper,wewillexaminesomeofthecontributingfactors,andmoreimportantly,provideyouwith thekeycriteriatodesignFPGAbasedsystemssuccessfully. FPGAshavecomealongwaysincetheywereintroducedinthe1980s.Initially,FPGAswereusedtocreate gluelogic,anessentialfunctionnotperformedbyothercomponentsontheboard.Today,FPGAshavethe densityandfunctionalitytoimplementanentiresystemonchip,asshowninFigure1.

Figure1FPGAGrowthandUsageTrends

ThisincreaseinFPGAcapability,combinedwiththefactthatsystemshavebecomemorecomplex,has introducedseveralFPGAboarddesignchallenges.ThereasonforthisaddedcomplexityinFPGAbasedboards isthatthecurrentboardtoolshavenotkeptpacewiththegrowthinFPGAs.Thesegenerictoolsareusedfor designingPCBscontainingcomponentswithnonprogrammablepinssuchasprocessorsandASICs.

Designing High-Quality FPGA-Based Systems

Whenyourgoalisfirsttimesuccess,highquality,andminimaldebugeffort,itmeansalaundrylistofitems thatshouldbeconsideredalistthatisespeciallylongforFPGAbasedsystems!Today,thismeansalotof busyworkandattentiontominutedetails.

WP011061.0March2009ver.1.0 2008TarayInc.Allrightsreserved.Alltrademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.Allspecificationsaresubject tochangewithoutnotice.NOTICEOFDISCLAIMER:Tarayisprovidingthisdesign,code,orotherinformationasis.Byprovidingthedesign,code,or informationaspossibleimplementationofthisfeature,application,orstandard,Taraymakesnorepresentationthatthisimplementationisfreefromany claimsofinfringement.Youareresponsibleforobtaininganyrightsyoumayrequireforyourimplementation.Tarayexpresslydisclaimsanywarranty whatsoeverwithrespecttotheadequacyoftheimplementation,includingbutnotlimitedtoanywarrantiesorrepresentationsthatthisimplementation isfreefromclaimsofinfringementandanyimpliedwarrantiesofmerchantabilityorfitnessforaparticularpurpose.

 Systemleveldesignproblemscanbeclassifiedintothefollowingcategories: FunctionalPhysicalissuesthatcausethedesigntonotwork.Forexample,ifaclocktotheFPGAisnot cominginthroughaclockpin,theclockcannotbedistributedwithareasonableskew,andhencethe designwillfailtofunction. ElectricalElectricalissuesthatcausetheboardtonotwork.Forexample,ifa3.3VLVTTLsignalis connectedtoanFPGAbankwitha1.8Vvoltagerail,thesignalwillnotelectricallyfunction,andsothe designwillfail. MarginalIssuesthatallowtheboardtoworkmostofthetime,butnotallofthetime.Forexample,ifa clockisconnectedtoanonclockpinintheFPGA,itcannotbedistributedcorrectlywithintheFPGA.When thishappens,thedesignmaynotworkatsomefrequencies,thoughitmayworkatcertainother frequencies. SomeoftheelectricalandfunctionalissuesrequirearespinofthefinalPCB.Thesemayberectifiedwith "greenwires"(orwiresofyourfavoritecolor!),butmaymakethePCBlessrobust.Suchfixestypicallyrequirea respinbeforetheboardisproductionworthy.Marginalissuesarenotonlyhardertofind,butareharderto debugandfixaswell.Moreimportantly,themarginalissuesaretheonesthatcouldshowupatacustomer sitewhichmeanstheseissuesshouldbeavoidedatallcosts!

Power Supplies and Power Distribution Systems

FPGAshaveahighnumberofpowersupplies.Forexample,asimpledesignwithaPCIExpress(PCIe)interface andaDDR2DIMMrequiresthepowersuppliesshowninTable1. Voltagerailvalue Need 1.2V SerialI/Opower 0.9V ReferencevoltageforDDR2 3.3V LVTTLcontrolsignalsforPCIeinterface 1.8V I/OvoltageforFPGAbanksconnectedtoDDR2 1.0V FPGAinternalvoltage GND Ground
Table1PowerSuppliesforaSimpleDesign

EverybankofanFPGAcanrequiretwoormorepowersupplies.Moreover,thelogicalconnectionstothebank determinethevoltageandcurrentrequirementsforthepowerrailvoltageandthecurrentrequirementfor thatbank.Thismeansthatyoushouldpayattentiontoyourvoltageconnectionseverytimethereisevena seeminglyminorchangeinthepinsconnectedtothebank. Forexample,ifaDDR2SDRAMisconnectedtoaparticularbank,a1.8Vand0.9V(referencevoltage)power supplyisrequiredforthatbank.Ontheotherhand,ifanLVDSbusisconnectedtothebank,a2.5Vpower supplyisrequiredtobeconnectedinsteadof1.8V.IfyouconsideraDDR2DIMM,mostpinsintheDIMMuse 1.8VSSTL.However,someI2Csignalscanbeanystandard.Variousdecouplingmethodsarerecommendedfor eachofthesedifferentpowersupplies. Tosummarize,thepowersupplyconnectionsrequirethefollowingconsiderations:

www.tarayinc.com

Createapowerbudgetforeachpowersupplyvoltageinyoursystem.Thisensuresthatthepowersupplies canadequatelysupplythecurrentrequiredbytheFPGAandtheinterface. Reviewtoensurethepowerrailsareoftherightvalue.Thismayseemanobviousstatement,butitis importantbecauselastminutelogicchangesandpinoptimizationsmaychangethepowerrail requirements. AdddecouplingcapsrecommendedbyAltera. EnsurethatpowersupplysensorsarelocatedclosetotheFPGApowerpinstoensurethepowersupply candrivethedynamiccurrentrequiredbytheFPGA. FollowtherecommendationsofAlteraandthepowersupplyvendors.

Clocks
FPGAshavedifferenttypesofclockpins.Forexample,globalclockpinsdistributetheclockthroughoutthe FPGA,whileotherclockpinsdistributeclockswithinacertainregionoftheFPGA.InFigure2,globalclocksare highlightedinredinthedieview,inblueinthepackageview,andareboldedinthepinlisting.

Dieviewof thepart

Packageview ofthepart

Figure2IllustrationofGlobalandRegionalClockPinsinaStratixIVFPGA

Selectinganincorrectpinforaclockcancreateamarginaldesign,whichwillworkforsomeconditions,butnot forothers. Selectingclockpinsforyourdesignrequiresthefollowingconsiderations: FrequencyoftheclockThefrequencydeterminesifyoushoulduseasingleendedclockoradifferential clock. LocalversusGlobalIfyourclockisgoingtobeusedthroughouttheFPGA,youwillneedtouseaglobal clock.Ifyouareusingtheclockforlocaldatacapture,youmaywanttouseoneoftheregionalorlocal clockpins.

www.tarayinc.com

Source-Synchronous Buses
Sourcesynchronousbusesarerelatedtoclocks,inthattheycontainclocksandanassociatedsetofdata signals.MostFPGAsrequirecertaingroupsofpinstobeusedforsourcesynchronousbuses,soonlyby selectingthecorrectFPGApinscanyouensuretheclockswillreachtheassociateddatasignals.Figure3shows anillustrationofdifferentclockregionsinanAlteraStratixIVFPGAwithdifferentcolorsinthedieandpackage. Inthisview,theclock(phaselockedloop(PLL))pinsarerepresentedwiththeletterLinagraycircleinsidea greensquare.

Figure3IllustratingDifferentClockRegionsWithDifferentColors

Yoursimulationsandverificationwillnotbeabletodetermineaproblemwithyourpinselections.For example,anunreportedproblemisadatapinoutsidethesourcesynchronousgroupsotheassociatedclock cannotcaptureit.TheFPGAtoolsreportproblemsassociatedwithclockanddatagroupswhenyouplaceand routethecorrespondingregistertransferlevel(RTL).

High-Speed Serial Buses

TodaysFPGAsprovidepinswithhighspeedtransceiversforyoutodesigninterfaceswithspeedsupto 10Gbps.DesigningwithhighspeedserialI/Osrequiresyoutofollowtheguidelinesrelatedtoboardlayout, powersupplydesigns,terminations,etc.,verycarefully.SomeFPGAsrequireisolatingthetransceiverpower supplypinsfromanyoftheregularorsingleendedI/Os.Notfollowingtheseguidelinesmaycausemarginal designsoradesignthatfailsinthelab.

www.tarayinc.com

Achieving High Quality

TheprogrammablenatureofFPGAsmakesthemverydifferentcomparedtoASICsandICs.FPGAshaveavery highnumberofI/Opins,certainlyhigherthanthetypicalIContheboard.HighernumbersofI/Osmakeitmore complextodesignthePCboard,andrequirespecialconsiderationstoachievehighquality. Letustrytodefinehighquality: Theboardworksconsistentlywitha20%margininfrequency,requiredbothbelowandabovethe operatingfrequency. Theboardworkswhentestedwithkeypartsfromdifferentprocesscorners. Theboardworkswitha5%or10%marginonvoltageandtemperature. Herearesomewaystoachievehighquality: ReducethenumberofPCBlayerstoimprovetheelectricalqualityofthesignals. Ensuregoodreturncurrentpathsforallthesignaltransmissionpaths,achievedbyensuringanadjacent power/groundplaneforallthesignalplanes. Reducethenumberofviasinthedesigntoreducesignalinductance,thustransmittingandreceivingthe signalatahigherquality. Keepthetracelengthofsignalstoaminimumtoreducetransmissionlinelosses,thusimprovingsignal quality. Budgetyourpowersuppliesandensuretheyaresufficienttohandleyoursystemneeds. Ensuresufficientdecouplingcapacitorsoftheappropriatevaluesareplacedonthepowersupply. TerminateyourhighspeedsignalsbasedonAlterasrecommendations. Performsignalintegrity(SI)simulationsonyourcriticalsignals. FollowAlterasguidelinesforhighspeedserialI/Odesigns. Mostimportantly: EnsureyouhaveahighlyexperiencedboarddesignerfamiliarwiththeuniquenatureofFPGAsandreview yourdesignthoroughlyateverystep. ReviewthefinallayoutandtheschematicstobesuretheyareconsistentwiththeFPGAdesignandpin outs. EnsuregoodcommunicationbetweenthePCBdesignteamandFPGAdesignteam.

7Circuits
7Circuits,anEDAtoolfromTaray,addressestheissueslistedinthiswhitepaper.7Circuitshasbeenusedvery successfullybylargeOEMstodesignFPGAbasedboards.Formoreinformation,pleasevisitwww.tarayinc.com andrequestafreedownloadof7Circuits.Youalsocanviewashortdemonstrationof7Circuits.

Taray, Inc., founded in 2002, provides industryleading solutions for complex FPGAs used in system design. Their flagship product, 7Circuits, utilizes unique and patented I/O synthesis technology that optimizes and assigns the exploding programmable I/O complexity associated with FPGAs in system design. Taray's I/O synthesis automation enables faster timetomarket and better quality of system resultsforFPGAsusedinsystemdesign.

www.tarayinc.com