I. None 15.28 (contd) II.

(4, 7) (6, 7) (2, 4) (2, 6) Assignment: S0 = 000, S2 = 100, S4 = 111, S6 = 110, S7 = 101
B C

00 01 11 10

S0

S2 S7 S4 S6

Present State S0 S2 S4 S6 S7

Next State W =0 1 S0 S0 S4 S7 S7 S6 S2 S4 S6 S2

Output 0 1 0 0 1 0 0 0 0 0 0 0

Present State 000 100 111 110 101

Next State W =0 1 000 000 111 101 101 110 100 111 110 100

Output 0 1 0 0 1 0 0 0 0 0 0 0

T input equations derived from the transition table using Karnaugh maps: TA = 0; TB = W'A; TC = WB + AB'; Z = W'AB'C' 15.29
X'Y' 0

S0
0 XY S

X'Y

Y'

S1
0 Y S XY'

S2
X'Y 0 X X'Y' P

By inspecting incoming arrows, we get: D0 = Q0+ = X'Y'Q0 + XYQ3 D1 = Q1+ = XQ0 + Y'Q1 + XY'Q3 D2 = Q2+ = X'YQ0 + X'Q2 + X'YQ3 D3 = Q3+ = YQ1 + XQ2 + X'Y'Q3 S = YQ1 + XQ2 P = X'Y'Q3
X' 0

S3

15.30

By inspecting incoming arrows, we get: Q0+ = D0 = X'YQ0 + Y'Q1 + X'YQ2 Q1+ = D1 = XY'Q0 + XYQ1 + Y'Q2 Q2+ = D2 = XYQ0 + X'Y'Q0 +X'YQ1 + XYQ2 Z = X'YQ1 + XYQ2 + X'YQ2 = X'YQ1 + YQ2

Unit 16 Problem Solutions

16.116.14 See Lab Solutions in this manual. 16.15 See FLD p. 662 for solution. 16.16 See FLD p. 662 for solution.
1

16.17 (a) The state meanings are given in the following table: Name S0 S1 S2 S3 Meaning No 1s have occurred One 1 has occurred (an odd number < 2) Two 1s or an even number of 1s > 2 have occurred An odd number of 1s > 2 has occurred. S0 0 0
1

S1 0 0

S2 0 0
1

S3 1

130

16.17 (b)

Next State State X = 0 X = 1 S0 S0 S1 S1 S1 S2 S2 S2 S3 S3 S3 S2 I: (1, 3) II: (0, 1) (1, 2) (2, 3)Z

ai bi
0 1 0 1

Z 0 0 0 1

ai b i

xi 00 01 11 10

0 0 0 1 1

1 1 1 0 0

xi ai' ai+1 x i' ai

ai+1 = xia' + x'a i i i

ai+1 = xi'ai + xi ai'

S0 S2

S1 S3

ai b i

xi 00 01

0 0 1 1 0

1 0 1 1 1

xi ai

bi'

bi+1

State S0 S1 S2 S3

aibi 00 10 01 11

ai+1bi+1 X=0 X=1 00 10 10 01 01 11 11 01

11

bi+1 = b' + xiai i

Z 0 0 0 1

10

bi+1 = bi + xi ai

ai+1 bi+1

Z
z = an+1bn+1

Note: Solution on FLD p. 622 uses state assignment S0 = 00, S1 = 01, S2 = 10, S3 = 11.

16.17 (c) Since no 1s have occurred, a0 and b0 are the same as S0 or, a0 = 0; b0 = 0; ai = x0a0' + x0'a0 = x0; first cell bi = b0 + x0a0 = 0

16.17 (d)

x0 a1 0 b1

x1 a2 b2

x2 a3 Cell 2 b3 an bn

xn an+1 bn+1
Output Circuit

Cell 1

Cell n

16.18 (a) Ni = Qi+ = (Qi + FBi + CALLi )Ri' = QiRi' + FBiRi' + CALLiRi'

Call i FBi Ri Clock Di Qi Ni

131

16.18 (b)

FS'2

UP

N1'N2DC R1DO, N1'N2 DC' 0, N1'N2' 0 N1

S1

UP

FS2

R2DO
S2

N2

Name S0 S1 S2 S3

Meaning Staying on first floor Moving from first to second floor Staying on second floor Moving from second to first floor

S0

FS1

R1DO FS'1

S3

N1N2'DC

R2DO, N1N2'DC' N1'N2' 0, 0

DOWN

DOWN

16.18 (c) With the state assignment S0 = 00, S1 = 01, S2 = 10, S3 = 11, we have: D1 = FS2Q1'Q2 + FS1'Q1 + Q1Q2'; D2 = FS2'Q1'Q2 + FS1'Q1Q2 + N1'N2DCQ1'Q2' + N1N2'DCQ1Q2' R1 = FS1Q1Q2 + N1Q1'Q2'; R2 = FS2Q1'Q2 + N2Q1Q2'; UP =FS2'Q1'Q2 + N1'N2DCQ1'Q2' DOWN = FS1'Q1Q2 + N1N2'DCQ1Q2'; DO = FS2Q1'Q2 + FS1Q1Q2 + N1Q1'Q2' + N2Q1Q2' 16.19 (a)
H' L'H'
111000

L'R'H'
S0 000000

H' L'RH' R'H'

000100

LR'H'
001000

R'H'
S4

S3

LH'

011000

S2

S1

L'H' H H -

LH'

RH'

000110

S5

RH'

000111

S6

H H

111111

S7

Outputs: LC, LB, LA, RA, RB, RC 16.19 (b) First, assign LC = Q1, LB = Q2, LA = Q3, RA = Q4, RB = Q5, RC = Q6. So S0 = 000000, S1 = 001000, S2 = 011000, etc. This state machine has too many state variables to use Karnaugh maps. Instead, we will write down equations for each flip-flop by inspection. First consider Q1. Q1 = 1 in states S3 or S7 only. S7 is reached whenever H = 1 and we are not already in S7: H(Q1Q2Q3Q4Q5Q6)'. But S7 is the only state in which both Q3 = 1 and Q4 = 1, so assuming we are always in a valid state, we can use H(Q3Q4)' = HQ3' + HQ4'. Note: Any combination of one left light and one right light will also work, i.e. HQ1' + HQ5'. S3 is reached whenever we are in S2 and L = 1 while H = 0: LH'Q1'Q2Q3Q4'Q5'Q6'. But Q3 = 1 whenever Q2 = 1, and Q4 = Q5 = Q6 = 0 whenever Q1 = 0. So we can use LH'Q1'Q2.

132

16.19 (b) (contd)

So D1 = LH'Q1'Q2 + HQ3' + HQ4' = LQ1'Q2 + HQ3' + HQ4' (using X + X'Y = X + Y) Similarly Q2 = 1 in states S3, S2, and S7 only. S3 and S2 are reached whenever we are in S2 or S1 and L = 1 while H = 0. LH'Q1'Q2Q3Q4'Q5'Q6' + LH'Q1'Q2'Q3Q4'Q5'Q6' = LH'Q1'Q3Q4'Q5'Q6' But again, Q4 = Q5 = Q6 = 0 whenever Q1 = 0, so D2 = LQ1'Q3 + HQ3' + HQ4' We can also get by inspection: D3 = LQ1'Q4' + HQ3' + HQ4'; D4 = RQ3'Q6' + HQ3' + HQ4'; D5 = RQ4Q6' + HQ3' + HQ4'; D6 = RQ5Q6' + HQ3' + HQ4' 001 S7 S7 S7 S7 S7 S7 S7 S0 010 S4 S0 S0 S0 S5 S6 S0 S0 011 S7 S7 S7 S7 S7 S7 S7 S0 100 S1 S2 S3 S0 S0 S0 S0 S0 101 110 111 S7 S7 S7 S7 S7 S7 S7 S0 LC 0 0 0 1 0 0 0 1 LB 0 0 1 1 0 0 0 1 LA RA 0 0 1 0 1 0 1 0 0 1 0 1 0 1 1 1 RB 0 0 0 0 0 1 1 1 RC 0 0 0 0 0 0 1 1
1
S7 S3 S5 S4

16.19 (c) State LRH = 000 S0 S0 S1 S0 S2 S0 S3 S0 S4 S0 S5 S0 S6 S0 S7 S0

I. (S0, S1, S2, S3, S4, S5, S6) for S7 in LRH = 001, 011, 101 Q1 Q2 Q 3 0 (S1, S2, S3, S6, S7) for S0 in LRH = 010 (S3, S4, S5, S6, S7) for S0 in LRH = 100 00 S0 II. Every state matches S0 and S7. But S0 and S7 match the best, so (S0, S7)(many times) 01 S2 III. (S1, S2, S3, S7) (S4, S5, S6, S7) etc. From LogicAid: So D1 = HQ2 + RQ1Q2Q3' + HQ3 + LQ1'Q2'Q3 + HQ1' + RQ1'Q2'Q3' D2 = RH'Q1'Q2'Q3' + RH'Q1Q2 + LH'Q1'Q2'Q3' D3 = LH'Q1'Q2Q3' + LH'Q1'Q2'Q3 + RH'Q1Q2 LC = Q1Q2'; LB = Q1Q2' + Q2'Q3 ; LA = Q1Q2' + Q2'Q3 + Q1'Q2Q3' RC = Q1Q2'Q3' + Q1'Q2Q3; RB = Q1Q2'Q3' + Q2Q3; RA = Q1Q3' + Q2Q3 Other minimum solutions can be found for D2 and D3 with this assignment.
11 10
S6 S1

133

16.20

RE' FF' PL'

IDLE 0
FF ST, FF RE PL ST, FF, RE ST, RE PL PL FF

Note: This state graph assumes that only one of the buttons ST, PL, RE, and FF can be pressed at any given time. The graph is incompletely specified and must be augmented before using LogicAid. For example, the arc from REW to PLAY should be labeled PL ST' FF'.
ST

ST

REW R
ST' FF' PL'

PL PL RE

PLAY P
ST' RE' FF'

FFWD F
ST' RE' PL'

ST' M'

ST' M' ST' M

SBACK R

ST' M

SFWD F

P ST RE FF PL M

Q1

Q1

CK

PLA

Q2+

Q2

CK
Q3+

D1 = ST' FF PS Q1' Q2' Q3 + ST' RE PL Q1' Q2' Q3 + ST' M Q1 D2 = ST' FF Q1' Q2' Q3' + ST' RE Q1' Q2' Q3' + ST' RE' PL' Q2 Q3 + ST' FF' PL' Q2 Q3' D3 = ST' RE' FF Q1' Q2' Q3' + ST' RE' FF' Q3 + ST' FF' PL Q2 Q3' + ST' RE' Q2 Q3 + ST' M' Q1 + ST' Q1 Q3 + ST' RE' PL Q1' Q2' P = Q1'Q2'Q3; R = Q2Q3' + Q1Q3'; F = Q2Q3 + Q1Q3

Q3

CK Clock

16.21 (a) 0 0 S0 0
1

S2 1
1

S1 1
1

S3 0

0,1

134

16.21 (b)

Next State State xi = 0 xi = 1 S0 S0 S1 S1 S2 S3 S2 S2 S1 S3 S3 S3 aibi 00 11 10 01 ai+1bi+1 xi = 0 xi = 1 00 11 10 01 10 11 01 01

Z 0 1 1 0

ai bi
0 1

S0 S3
xi 00 01 11 10

S2 S1
xi 00 01 11 10

ai b i

0 0 0 1 1

1 1 0 0 1

ai b i

0 0 1 0 0

1 1 1 1 1

an+1 bn+1 0
0 1

1 1

Z 0 1 1 0

Z = an+1

ai+1 = (xi + ai ) (xi'+ bi')

bi+1 = (xi + bi ) (xi + ai')

16.21 (c) a0 = b0 = 0 a1 = (x0 + 0) (x0' + 1) = x0 b1 = (x0 + 1) (x0 + 0) = x0 16.21 (d) a1 b1 x1 x0 Cell 1 a2 b2 x2 a3 Cell 2 b3 an bn xn Cell n an+1 bn+1 Z

Unit 17 Problem Solutions

17.1 See FLD p. 664 for solution. 17.2 See FLD p. 665 for solution.

17.3 (a, b)

Q(7) Q(6) Q(5) Q(4)

CO CLK CO CLRn LOAD ENP UP CO1 CLK

Q(3) Q(2) Q(1) Q(0)

CO CLRn LOAD ENT ENP UP

ENT

Up/Down D(7) D(6) D(5) D(4)

Up/Down D(3) D(2) D(1) D(0)

See FLD p. 665-666 for solutions. 17.4 See FLD p. 666-667 for solution. 17.5 See FLD p. 667 for solution.

135

17.6 (a, b) See FLD p. 667-668 for solutions.

X1 X2 Q1 Q2

2 X4 ROM

Q1+

Z1 Z2
D Q CLK

Q2+
CLK

D Q

17.7 (a) See FLD p. 668 for solution.

Q(1) Q CE
LdA LdB CLK

Q(2) Q CE
CLK

LdA A(1) LdA' LdB B(1) LdA A(2) LdA' LdB B(2) 17.7 (b)

Q(1) Q CE
LdA LdB CLK 1 A(1) 0 B(1) LdA

Q(2) Q CE
CLK 1 A(2) 0 B(2) LdA

17.8

See FLD p. 668 for solution.

136

17.9

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity srff is port (clk, s, r : in std_logic; q, qn : out std_logic); end srff; architecture Behavioral of srff is signal qint : std_logic:='0'; begin q <= qint; qn <= not qint; process(clk) begin if clk'event and clk='1' then if (not s and r)='1' then qint <= '0'; elsif (s and not r)='1' then qint<='1'; elsif (s and r)='1' then qint<='X'; end if; end if; end process; end Behavioral;

17.10

17.11

A rising edge triggered D-CE flip flop with asynchronous clear and preset.

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- D-G Latch entity dglatch is port (d, g : in bit; q : out bit); end dglatch; architecture Behavioral of dglatch is begin process(g, d) begin if g='1' then q <= d; end if; end process; end Behavioral; -- D flip flop using D-G latches library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity dff is port (d, clk : in bit; q : out bit); end dff; architecture Behavioral of dff is component dglatch is port (d, g: in bit; q : out bit); end component; signal p, clkn : bit; begin clkn <= not clk; dg1 : dglatch port map(d, clkn, p); dg2 : dglatch port map(p, clk, q); end Behavioral;

17.12

8
En Qint Ld Clk D

8-bit Register
8

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity myreg is port(en, ld, clk : in std_logic; d : in std_logic_vector(7 downto 0); q : out std_logic_vector(7 downto 0)); end myreg; architecture Behavioral of myreg is signal qint : std_logic_vector(7 downto 0):="00000000"; begin q <= qint when en ='1' else "ZZZZZZZZ"; process(clk) begin if clk' event and clk='1' then if ld='1' then qint <= d; end if; end if; end process; end Behavioral;

137

17.13

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity encoder is port (y0, y1, y2, y3 : in bit; a, b, c : out bit); end encoder; architecture Behavioral of encoder is begin process(y0, y1, y2, y3) begin if y3='1' then a <= '1'; b <= '1'; c <= '1'; -- y3 has highest priority elsif y2='1' then a <= '1'; b <= '0'; c <= '1'; elsif y1='1' then a <= '0'; b <= '1'; c <= '1'; elsif y0='1' then a <= '0'; b <= '0'; c <= '1'; else a <= '0'; b <= '0'; c <= '0'; end if; end process; end Behavioral;

17.14

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity comparator is port (a, b : in std_logic_vector(3 downto 0); agb, alb, aeb : out std_logic); end comparator; architecture Behavioral of comparator is begin process(a, b) begin if a > b then agb <= '1'; alb <= '0'; aeb <= '0'; elsif a < b then agb <= '0'; alb <= '1'; aeb <= '0'; else agb <= '0'; alb <= '0'; aeb <= '1'; end if; end process; end Behavioral;

17.15

library IEEE; 17.16 use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity super is port (a: in std_logic_vector(2 downto 0); d : in std_logic_vector(5 downto 0); rsi, lsi, clk : in std_logic; q : out std_logic_vector(5 downto 0)); end super; architecture Behavioral of super is signal qint: std_logic_vector(5 downto 0); begin q <= qint; process(clk) begin if clk' event and clk='1' then case a is when "111"=> qint <= d; when "110"=> qint <= qint-1; when "101"=> qint <= qint+1; when "100"=> qint <= "111111"; when "011"=> qint <= "000000"; when "010"=> qint <= rsi&qint(5 downto 1); when "001"=> qint <= qint(4 downto 0)&lsi; when others=> NULL; end case; end if; end process; end Behavioral;

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity bcd_seven is port (bcd : in bit_vector(3 downto 0); seven : out bit_vector(7 downto 1)); end bcd_seven; architecture Behavioral of bcd_seven is begin process(bcd) begin case bcd is when "0000"=> seven <= "0111111"; when "0001"=> seven <= "0000110"; when "0010"=> seven <= "1011011"; when "0011"=> seven <= "1001111"; when "0100"=> seven <= "1100110"; when "0101"=> seven <= "1101101"; when "0110"=> seven <= "1111101"; when "0111"=> seven <= "0000111"; when "1000"=> seven <= "1111111"; when "1001"=> seven <= "1101111"; end case; end process; end Behavioral;

138

17.17

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity sm1 is port (x, clk : in std_logic; z : out std_logic); end sm1; architecture Behavioral of sm1 is type rom8_3 is array(0 to 7) of std_logic_vector(0 to 2); constant myrom: rom8_3 :=("001","100","111","000","000","010", "110","101"); signal index, romout: std_logic_vector(0 to 2); signal q, d: std_logic_vector(1 to 2):="00"; begin index <= x&q; romout <= myrom(conv_integer(index)); z <= romout(0); d <= romout(1 to 2); process(clk) begin if clk' event and clk='1' then q <= d; end if; end process; end Behavioral;

17.18 X 0 X'

S0
X

X' 0 X' Z Z

S1
X

S3

X' Z

S2

X Z

--The state assignment is as follows (q0q1q2q3)--S0 - 1000; S1 - 0100; S2 - 0010; S3 - 0001 --VHDL code using equations derived by inspection from state graph entity sm1 is port (x, clk : in bit; z : out bit); end sm1; architecture equations of sm1 is signal q0 : bit := '1'; signal q1, q2, q3 : bit:='0'; begin process(clk) begin if clk'event and clk='1' then q0 <= (x and q0) or (not x and q1) or (not x and q3); q1 <= (not x and q0) or (x and q3); q2 <= (x and q2) or (x and q1); q3 <= not x and q2; end if; end process; z <= (not x and q1) or (x and q3) or q2; end equations;

17.19

Next State State X = 0 X = 1 S0 S0 S1 S1 S1 S2 S2 S2 S3 S3 S0 S0

Output X=0 X=1 10 00 01 01 01 01 00 10

17.20

Next State State X = 0 X = 1 S0 S0 S1 S1 S3 S2 S2 S1 S0 S3 S0 S1

Output 1 0 0 0

139

17.21 State S0 S1 S2 17.22

Next State X1X2 = 00 01 10 S0 S1 S2 S0 S1 S2 S0 S1 S2

11 S0 S1 S2
Z

Z 0 0 1
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity mask_8 is port (X : in std_logic_vector(7 downto 0); Store, Set, Clk : in std_logic; Z : out std_logic_vector(7 downto 0)); end mask_8; architecture Behavioral of mask_8 is signal M : std_logic_vector(7 downto 0); begin process(Set, Clk) begin if Set='1' then M <= "11111111"; elsif Clk'event and Clk='1' then if Store='1' then M<=X; end if; end if; end process; Z <= M and X; end Behavioral;

M Store Set Clk

Mask Register
8
X

17.23

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity Seq_143 is port (Clk, X : in std_logic; Z : out std_logic); end Seq_143; architecture Moore of Seq_143 is signal State : integer := 0; signal NextState : integer range 0 to 3; begin process(State, X) begin case State is when 0 => Z <= '0'; if X = '0' then NextState <= 0; else NextState <= 1; end if; when 1 => Z <= '0'; if X = '0' then NextState <= 2; else NextState <= 1; end if; when 2 => Z <= '0'; if X = '0' then NextState <= 0; else NextState <= 3; end if; when 3 => Z <= '1'; if X = '0' then NextState <= 2; else NextState <= 1; end if; end case; end process; process(Clk) begin if Clk'event and Clk='1' then State <= NextState; end if; end process; end Moore;

140

Unit 18 Problem Solutions

18.3 See FLD p. 669 for circuit. Notice that the Q output of the flip-flop is bin , while the D input is bout . St' 0 St' 0 St 18.4 See FLD p. 670. AND-ing with xi is like M/Ad if xi is 1. Shifting is like moving from AND gates involving x1 to those involving x2, or from x2 to x3. See FLD p. 670. Compare to divider state graph of FLD Figure 18-11. See FLD p. 670.

18.5 St 18.6 Sh

S0

S5
0 Sh

S1
Sh

18.7 (a) Overflow occurs only on division by 0, so V = y0'y1'y2'y3'y4' = (y0 + y1 + y2 + y3 + y4)' 18.7 (b) - (d) See FLD p. 671. 18.8 See FLD p. 671.

S4
Sh

S2 S3
Sh

18.9

The ONE ADDER is similar to a serial adder, except that there is only one input. This means that the carry will be added to X. Thus, if the carry flip-flop is initially set to 1, 1 will be added to the input. The signal I can be used to preset the carry flip-flop to 1. Let S0 represent Carry = 0, and let S1 represent Carry = 1. The state graph is as follows: X' , X 0 Z I X Sh 0

, Sh'

S0
X' Sh Z

S1

X Sh

Q 00 01 11 10

0 0 0 0 0

1 1 0 1 1

X Sh

Q 00 01 11 10

0 0 0 1 1

1 0 1 0 0

I X Sh' Clk Q X Q' X' X or Q' Sh D

PreN

Q+= Q (Sh' + X )

Z = (Q + X) (Q'+X') (X + Sh) Z = (Q + X) (Q'+X') (Q'+ Sh)

Q'

141

18.10 (a)

product ACC
5

C O N T R O L

Load Sh Ad Clk Done St M

C4

4-BIT ADDER

multiplier

multiplicand
St'/0

18.10 (b)
- /Done S7 S9 - /Sh S6 M/Ad S5 - /Sh M'/Sh

18.10 (c) 0 0 0 0 0 1 0 1 add

St/Load S1 M/Ad M'/Sh S2 - /Sh S3 M/Ad

S0

1 0 1 0 1 0 1 0 0 1 0 0 0 0 1 1 0 1 0 1 1 0 0 0 1 1

1 1 1 0 1 1 0

1 0 1 shift 1 1 0 shift 1 1 1 add 1 1 1 shift 1 1 1

M'/Sh

S4

18.10 (d)

Present State S0 S1 S2 S3 S4 S5 S6 S7

Next State StM: 00 01 10 11 S0 S0 S1 S1 S3 S2 S3 S2 S3 S3 S3 S3 S5 S4 S5 S4 S5 S5 S5 S5 S7 S6 S7 S6 S7 S7 S7 S7 S0 S0 S0 S0

Ad Sh Load Done 00 01 10 11 0000 0000 0010 0010 0100 1000 0100 1000 0100 0100 0100 0100 0100 1000 0100 1000 0100 0100 0100 0100 0100 1000 0100 1000 0100 0100 0100 0100 0001 0001 0001 0001

I. (S0, S7) (S1, S2) (S3, S4) (S5, S6) II. (S0, S1) (S2, S3) (S4, S5) (S6, S7) III. (S1, S3, S5) (S2, S4, S6) etc.
A 00 01 11 10

B C

0
S0 S3 S5 S7

1
S1 S2 S4 S6

(Other assignments are possible.)

142

18.10 (d) For this assignment, from LogicAid: (contd) JA = StB'C' + MC; KA = M' + B + C; JB = A'C; KB = A'C'; JC = AB'; Sh = M'A + M'C + AB + AC; Load = StA'B'C'; Done = A'BC'

KC = A'B;

Ad = MAB'C' + MA'C;

3 M

Sh

SI Sh Ld Clk

Q7 D7

Q6 D6

Q5 D5 5

Q4 D4 Ld 5

Q3 D3

Q2 D2

Q1 D1 3

Q0 D0 Ld 3

Ld Ad

0
5 4
adder

1
0 4

0
3

1
multiplier

4 St M Ad Sh Ld Done
J
Clk

multiplicand

OR gates, AND gates, & inverters implement the equations from 18.10 (d)

K J
Clk

K J
Clk

18.11 (a)

product
Load Sh Ad
Clk

C O N T R O L

ACC
6

Done

C5

5-BIT ADDER

multiplier

St
M

multiplicand

143

18.11 (b) See solution to 18.10 (b). 18.11 (d) Graph is same as 18.10, so from LogicAid, using the same state assignment: DA = StA'B'C' + MAB'C' + MA'C DB = A'C + AB DC = AB' + B'C + AC Ad, Sh, Ld, Done: See solution to 18.10 (d) St 1 M 1 1 0 0 A 0 1 0 0 1 1 1 1 0 B 0 0 1 0 0 1 C 0 0 1 1 1 1 1 0 DA 1 1 1 0 0 0 0 0 0 0 0 DB DC 0 0 0 0 0 0 1 0 1 0 0 1 0 1 0 1 0 0 0 0 0 0 Ad Sh Ld Done 0 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 1

18.11 (c) 0 0 0 0 0 0 1 1 0 shift

0 0 1 0 1 0 0 1 0 1 0 0

0 0 0 1 0 1 1

0 1 1 0 1 1 1

0 0 0 1 0 1 1

0 0 0 0 0 0 1

0 1 1 add

0 1 1 shift 0 0 1 add 0 0 1 shift 0 0 0

St M
Clk

A B

PLA
Clk

Ad Sh Ld Done
D Q

D Q
Clk

D Q
Clk

3 M
Sh

SI Sh Ld Clk

Q8 D8
0 1 0

Q7 D7
0 1 0 FA

Q6 D6
0 1 0 FA

Q5 D5
0 1 0 FA

Q4 D4
0 1 0 FA

Q3 D3
0 1 0 FA

Q2 D2

Q1 D1 3

Q0 D0

Ld Ad

0
0

1
3 3
multiplier

Ld

multiplicand

144

18.12 (a)

St'

S0
K Sh

St M Ad

M'K Sh

St M' Sh

S1

K' M

Sh

S2

M'K' Sh

18.12 (b) State S0 S1 S2 S1 S2 S1 S0

Counter 00 00 01 01 10 10 00

X 000000111 011001111 001100111 100101111 010010111 101011111 010101111

St 1 0 0 0 0 0 0

M 1 1 1 1 1 1 1

K 0 0 0 0 1 1 0

Ad Sh 1 0 0 1 1 0 0 1 1 0 0 1 0 0

Ad

18.13 (a)

(alternate solution)

C C

d7 b8
Full Subtracter

b7 Full x6

d6

Subtracter

b6 Full x5

d5

Subtracter

b5 = 0

x7

y2

y1

divisor 18.13 (b)

x7

x6

x5

x4

x3

x2

x1

x0

Sh Ld Su Sh

SubtracterComparator 0 Divisor

Control Clk

St V

18.13 (d) 0 1 0 1 0 0 1 1

18.13 (c)

1 0 1 0 0 1 0 1 0

1 0 1 1 0 1 0 1 1 0 1 1 0 1 1

1 1 1 0 0 1 1 0 1 1 1 0 1 1 0

0 0 1 1 0 0 0 1 1 0 1 1 1 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 0 1 1 0 1 1 1 0 1
quotient

shift C = 0
C Su

St' 0

St

Ld

sub. C = 1 1 shift C = 0 0 sub. C = 1 1 shift C = 0 0 shift C = 0 0 sub. C = 1 1 shift C = 0 0 sub. C = 1 1 C=0

, 0

C'

S0
C V

S1

C' Sh

S6
C' Sh C Su

S2
C' Sh

Su

S5

C' Sh

C' Sh

S3

Su

S4

Su

remainder

145

18.14 (a)

x7

x6

x5

x4

x3

x2

x1

Sh Ld Su Sh

18.14 (b)

St' 0 St' 0

SubtracterComparator 0

Control Clk

St V St 0 C' 0

S0
C V

St

Ld

y4

y3

y2

y1

S4
, Su
C

S1
C' Sh C Su

S3
18.14 (c) alternate solution Comparator C Comparator C

C'

Sh

S2

d7 F.A.

d6 F.A.

d5 F.A.

d4 F.A.

d3 F.A.
1

x7
18.14 (d) 0 1 0 1 1 0 1

x6

y4

x5

y3

x4

y2

x3
K'B' Sh

y1
K'B' Sh

1 0 1 0

1 0 1 1 1 0 1 0

1 1 1 0 1 0 1 1

0 1 0 0 0 1 0 1

1 0 1 1 1 1 1 0

1 0 1 1 1 0 1 1
quotient

shift C = 0 sub. C = 1 shift C = 0 sub. C = 1

18.15 (a) St' 0

St

R K X

K'B X Sh K'B X Sh

S0

S1
K 0

S2

remainder

18.15 (b) D0 = St'Q0 + KQ1 + KQ2; D1 = StQ0 + K'B'Q1 + K'BQ2; D2 = K'BQ1 + K'B'Q2; R = StQ0 Sh = K'B'Q1 + K'BQ1 + K'BQ2 + K'B'Q2 = K'Q1 + K'Q2; X = KQ1 + K'BQ1 + K'BQ2 = KQ1 + BQ1 + K'BQ2 18.16 (a)
SI Sh Clk

So

St

Clr K

Counter

Controller
18.16 (b) St' 0 Clk K S'o Sh K So

Clk Er

Er

S0

St

Clr

S1

K' S o

K' S o Sh SI Sh

K'S'o Sh , Sh SI

K' S'o

S2

146

18.16 (c) D0 = St'Q0 + KQ1 + KQ2; D1 = K'X0'Q1 + StQ0; D2 = K'X0Q1 + K'Q2; Clr= StQ0 Sh = K'X0'Q1 + KX0'Q1 + K'X0Q1 + K'Q2; Er= KX0Q1; SI = K'X0Q1 + K'X0'Q2 18.17 (a) St

Control
Clk

Sh

SI Sh Clk

Shift Register A

a b

SI

Counter
Clk

SI Sh Clk

Shift Register B

Logic Network

18.17 (b)

St'

St' St

S0
K

St

Sh

Present State S0 S1 S2

00 S0 S0

StK 01 11 S0 S1 - S2 S0 S2

10 S1 S1 S2

00 0 0

Sh 01 11 0 1 - 1 0 0

10 1 1 0

S2

S1
Sh

K' Sh

18.17 (c) I. (S0, S2)2 (S1, S2) (S0, S1) II. (S0, S2)2 (S1, S2) (S0, S1)2 From Karnaugh maps: D0 = Q0+ = StQ0 + KQ0'Q1 D1 = Q1+ = St; Sh = StQ0' Alternative: Q0+ = StQ0 + StKQ1 St 1 1 1 K 1 Q0 1 0 0 Q1 1 D0 1 1 0 0 D1 0 0 1 0 Sh 0 0 0 1

0 1

S0 S1

18.17 (d) SI = C'ab + Cab' + Ca'b

S2

18.18 (a) St C

Control
Clk

Sh

SI Sh Clk

Shift Register A

a b

SI

Counter
Clk

SI Sh Clk

Shift Register B

Logic Network

18.18 (b)

St' 0

St C

Sh D

S0
St C' Sh K K Sh

S1
Sh D

K'

Sh D

State Meaning S0 Reset S1 Find AND of A & B S2 Find XOR of A & B

S2
K' Sh

147

18.18 (c) Q0+ = St'Q0 + KQ1 + KQ2; Q1+ = StCQ0 + K'Q1; Q2+ = StC'Q0 + K'Q2; Sh = StCQ0 + StC'Q0 + K'Q1 + KQ1 + K'Q2 + KQ2 D = StCQ0 + K'Q1 + KQ1 St 0 1 1 18.19 (a)
SI Sh

18.18 (d) Change C' to D' in 18.17 (d) SI = D'ab + Dab' + Da'b 18.19 (b)
St'

C 1 0 -

K 1 1 0 0

Q0 Q1 Q2 Q Q Q Sh D 1 - 1 0 0 0 0 - 1 1 0 0 1 1 - - 1 1 0 0 1 0 1 - 0 1 0 1 1 - 1 0 1 0 1 1 1 - 0 0 1 1 0 - - 1 0 0 1 1 0
+ 1 + 2 + 3

S0
Sh St Sh

S3
Sh Sh

S1

S2

Note: M can be determined independently of the state of the system, so it is not included in the state graph. X0 St 18.20 (a)
A B SI

Clk

Sh M

Control C1 C2

18.19 (c) JA = B; KA = B; JB = St + A; KB = 1; Sh = St + A + B; M = C1'C2 + X0'C1C2

Clk

Ld

Counter K

Controller
St Clk

Clk

18.20 (b) St' 0

K'

S0

St

18.20 (c) K K' Ld

Ld

S1
K 0

S2

StK State 00 01 11 S0 S0 S0 S1 S1 S1 S2 S2 S2 S0 -

10 S1 -

00 000 010 100

ABLd 01 11 000 001 001 000 -

10 001 A = K'Q1;

D1 = KQ2 + K'Q1; D2 = St + K'Q2; B = K'Q2; Ld = St + KQ2

18.21 St' 0 St

S0
St' 0 St

LdAc, EnIn

S1

S2

EnIn, LdAd

S3
EnAd, LdAc

St Control Clk

S6

S5
Done, EnAd, LdAc

EnIn, LdAd

S4

EnAd LdAd EnIn LdAc Done

Done

148

18.22 (a) St' 0 ZER1 ZER2

ZER1 ZER2'

S0

Done

St

S1
ZER1'

18.22 (b) J = ST; K = ZER1 ZER2; Done = ZER1 ZER2 Q; CLR = STQ'; CT2 LD1 LD2 = STQ'; LD1 = STQ' + ZER1 ZER2' Q; CT1 = ZER1' Q; CT2 = ZER1 ZER2' Q 18.22 (c) (N1 + 1)N2 cycles

LD2 LD1 CLR

CT1 18.23 (b) D = EZERO' Q + StQ'; Done = EZERO Q; CLR = StQ'; LOAD = StQ' + IZERO EZERO' Q DOWN = IZERO' EZERO' Q UP = IZERO EZERO' Q

18.23 (a) St' 0 EZERO

IZERO' EZERO' DOWN Done

S0

St

S1

CLR LOAD 18.23 (d) The quotient counter reaches 1111, and UP = 1 IZERO EZERO' again. UP LOAD 18.23 (e) The quotient will count upward forever, and Done will never be 1. N
8 Ld Su

18.23 (c) N1 + (N1/N2) cycles (round down)

18.24

8-bit register
8 B 8

St - start Ld - load N into register and clear counter Su - load subtracter output into register Inc - increment counter B - borrow

Ld St

Su

Clk

Control Circuit
Clk

8-bit subtracter
8

"000"
Clr Inc Clk

4-bit counter

odd integer When the done signal comes on, square root is in the 4-bit counter St St' 0

S0

Ld

S1

B'

Su Inc

Done

149