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E1/2.
048 Mbit/s Technology Overview

This application note will introduce you to the basic concepts in 2.048 Mbit/s technology, including sampling a signal, line coding, framing, and basic alarms/errors. This note can be used as an introduction to the technology as well as a field reference guide for everyday use.
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I N C O R P O R A T E D
Application Note
Table of Contents PDH Structure Converting a Voice Signal - Sampling/Nyquist Theorem Pulses Line Coding - AMI - HDB3 Framing - FAS - MFAS
Page # 2 3 3 4 5 5 5 6 7 8
Page # CRC Error Checking E-bit Performance Monitoring Errors and Alarms 64 kbit/s Interfaces - Codirectional Interface - Contradirectional Interface ITU-T Recommendations 9 11 12 14 14 14 14
22 Great Oaks Blvd, San Jose CA 95119 USA Tel: 1 408 363 8000 Fax: 1 408 363 8313 Internet: http://www.sunrisetelecom.com
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E1/2.048 Mbit/s Technology Overview

PDH Structure
x4 E3 x4 E2 x4 E1 E1 Channel 00 Channel 01 Channel 02 E1 E2 E2 E3 E3
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MUX 140 Mbit/s
MUX
E3
MUX
E2
MUX
E1
Channel n nx64 kbit/s E1 2.048 Mbit/s E2 8.448 Mbit/s E3 34.368 Mbit/s E4 139.264 Mbit/s
Figure 1 PDH Hierarchy
PDH: Plesiochronous Digital Hierarchy See Figure 1. Numerous signals, almost synchronous, are received at a mux, where they are multiplexed into a single signal. The entire signal must be demultiplexed in order to switch one lower-order signal. No standards exist for optical transmission equipment, meaning different manufacturers make equipment to different standards, so the equipment may not interface. The E1 or 2.048 Mbit/s line is the basic component of the PDH system. The 2.048 Mbit/s signal (bitstream) is achieved by multiplexing 32 individual 64 kbit/s bitstreams.
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Converting a Voice Signal
To transmit voice in a digital medium such as a 2.048 Mbit/s line, the analog voice signal needs to be transformed into a binary format, then converted into a bitstream suitable for digital transmission.
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Voice Signal Volts Sampling
Pulse Amplitude Modulation Volts Quantization 00101101

Time
Time
10110110
11000100
Figure 2 Converting a Voice Signal
To Remember:
Sample Voltage A-law Binary Code A B C D 2.08V 2.01V 1.57V -0.48V 11101101 11100000 10101001 00010001
8 bits = 1 byte 1 byte = 1 sample Signal Rate = 64 kbit/s = Digital Signal Level 0 (DS0) Sample at 8000 Hz
Figure 3 Pulse Code Modulation (PCM)
Sampling/ Nyquist Theorem A signal must be sampled at a minimum of twice its maximum frequency in order to be reconstructed in an analog format without a loss of information. For voice signals, a maximum frequency of 4000 Hz provides adequate clarity and contains the majority of the information, while conserving transmission bandwidth. Thus, a 4000 Hz voice signal must be sampled at a frequency of 8000 Hz (8000 samples/second). Each amplitude value is expressed as an 8-bit code "word", or byte (after A-law conversion). Each byte represents a single sample. See Figure 3. These 8-bit bytes occurring 8000 times per second form a 64 kbit/s digital bit stream. The 8-bit byte is formed by comparing the amplitude of the analog sample to a "companding characteristic", which is a formula translating the amplitudes of the samples into bytes. Internationally, a companding characteristic known as "A-law" is used, intended to provide optimum signal to noise performance over a wide range of transmission levels. In North America, the encoding is done according to the -law.
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Pulses
The quality of the E1 pulse is an important factor in clear transmission. See Figure 4.
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Ideal Pulse
Actual Pulse
G.703 Mask
Figure 4 E1 Pulse
The G.703 standard defines the E1 wave form. - Superimposing this pulse mask over a received pulse allows you to see the quality of the pulse. See Figure 5 for the specifications for an E1 pulse, as specified in ITU-T G.703, Table 6.
Pulse Shape (nominally rectangular) Pair(s) in each direction Test load impedance Nominal peak voltage of a mark (pulse) Peak voltage of a space (no pulse) Nominal pulse width Ratio of the widths of positive & negative pulses at the centre of the pulse interval Ratio of the widths of positive & negative pulses at the nominal half amplitude Maximum peak-to-peak jitter at an output port
All marks of a valid signal must conform with the mask (see Figure 15/G.703) irrespective of the sign. The value V corresponds to the nominal peak value. One coaxial pair (see G.703,6.4) 74 ohms resistive 2.37 V 0+/-0.237 V One symmetrical pair (See G.703, 6.4) 120 ohms resistive 3V 0+/-0.3V 244 ns 0.95 to 1.05
0.95 to 1.05
Refer to section 2 of Recommendation G.823
Figure 5 G.703/Table 6, 2.048 Mbit/s Pulse Mask Specifications
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Line Coding
Two types of line coding are used in a typical E1 2.048 Mbit/s network: AMI (top of following figure) and HDB3 (bottom of figure). HDB3 is the coding used most commonly for 2M, 8M, and 34M.
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AMI Line Coding
2.37V
0V
time
-2.37V 1 2.37V 1 0 1 0 0 0 0 0
0V
time
-2.37V
HDB3 Line Coding
Note: This voltage is over a 75 unbalanced connection
Figure 6 AMI and HDB3 Line Coding
AMI AMI: Alternate Mark Inversion. AMI is used to represent successive 1's values in a bitstream with alternating positive and negative pulses. AMI is not used in most 2.048 Mbit/s transmission because synchronization loss may occur during long strings of data zeros. HDB3 HDB3: High Density Bipolar 3; there will be no more than 3 consecutive zeroes on the line. The HDB3 line coding format was adopted in order to eliminate these synchronization problems, by increasing the number of transitions even during a long string of zeros. A string of four consecutive zeros is substituted with a string of pulses containing an intentional bipolar violation. As the far end equipment receives the E1 signal, it examines the bit stream for these intentional bipolar code violations. It will then extract the code and reconstruct the original data. See Figure 7. The HDB3 code substitutions provide high pulse density so that the receiving equipment is able to maintain synchronization with the received signal.
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Polarity of Previous Pulse # of Pulses Since Last Substitu tion
Data
0 0 0 0 0 0 0 0
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Even
Pulses
Data
Odd
Pulses
Figure 7
HDB3 Encoding
The particular substitution made is governed by the polarity of the last inserted bit, as well as by the number of pulses following the previous violation bit. - Odd number of pulses: 000V substituted - Even number of pulses: B00V substituted; where B is opposite polarity of the bit immediately preceding it, and V is the same as B.
Framing
Framing is necessary so any equipment receiving the E1 signal can identify and extract the individual channels. 2M transmission utilizes two main types of framing: - Frame Alignment Signal (FAS) - MultiFrame Alignment Signal (MFAS) PCM-30 transmission systems use MFAS framing along with the FAS framing. - In PCM-30 framing, time slots 1 through 15 correspond to channels 1 through 15, and time slots 17 through 31 correspond to channels 16 through 30. - Time slot 16 is used for the multiframe alignment signal also. PCM-31 transmission systems use only FAS framing. - In PCM-31 framing, time slots 1 through 31 correspond to channels 1 through 31. Fractional E1 is not offered with unframed signals, because framing is required to determine the location of time slots.
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Frame Alignment Signal (FAS) The 2.048 Mbit/s frame consists of 32 individual time slots (numbered 0-31). Each time slot consists of an individual 64 Kbit/s channel of data. See Figure 8.
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One 2.048 Mbit/s Frame Time Slot 0 1 ... 31
BITS Even Frame: Contains Frame Alignment Signal (FAS) Odd Frame: Does Not Contain Frame Alignment Signal (NFAS) 1 E E 2 0 1 3 0 A 4 1 5 1 6 0 7 1 8 1
Sa Sa Sa Sa Sa
Sa = Bit reserved for National use - ISDN Applications E = Error Indication Bit A = Remote Alarm (FAS Remote Alarm Indication) Frame Alignment Signal =0011011 8 bits per time slot x 32 time slots per frame x 8000 frames per second = 2.048 Mbit/s transmission rate
Figure 8 FAS Framing Format
Time slot 0 of every even frame is reserved for the frame alignment signal (FAS); in odd frames it is reserved for non frame alignments patterns. Alternate frames contain the FAS Distant Alarm indication bit and other bits reserved for National and International use. 31 time slots remain for bearer channels, into which customer data can be placed.
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MultiFrame Alignment Signal (MFAS) MFAS framing uses Channel-Associated Signalling (CAS) to transmit A/B/C/D bit signalling information for each of the 30 channels. - This method uses the 32 time slot frame format with time slot 0 for the FAS and time slot 16 for the MultiFrame Alignment Signal and the Channel Associated Signalling. 16 frames make up a MultiFrame. When a PCM-30 multiframe is transmitted, 16 FAS frames are assembled together, time slot 16 of the first frame is dedicated to MFAS bits, then time slot 16 of the remaining 15 frames is dedicated to A/B/C/D bits. Refer to Figure 9.
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Frame 0
Frame 1
Frame 2
Frame 3
-----
Frame 15
TS0 ----TS 16 ---- TS31 TS0 ---- TS 16 ---- TS 31 Bits 1 2 3 4 5 6 7 8 0 0 0 0 X Y X X Bits 1 2 3 4 5 6 7 8 AB CDA B C D
Channel 1 (TS-1) Channel 16 (TS-17)
TS0 ---- TS 16 ---- TS31 Bits 1 2 3 4 5 6 7 8 AB CD A BC D

Channel 15 Channel 30 (TS-31) (TS-15)
Frame 0 TS 16 bits: MFAS=0000XYXX X=spare bits (=1, if not used) Y= MFAS Remote Alarm (=1, if MFAS synchronization is lost) Notes: 1) Frames are transmitted with 30 voice channels on time slots 1-16 and 17-31. 2) Timeslot 16 (TS 16) contains A/B/C/D bits for signalling (CAS). 3) MFAS framing still includes the original FAS frames and FAS framing information.
Figure 9 MFAS Framing Format
Frame 0, time slot 16: 8-bit MFAS signal. Frames 1-15, time slot 16: (4 signalling bits/channel) x (30 channels) / (8 signalling bits/frame time slot 16) = 15 frames of time slot 16 signalling.
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CRC Error Checking
A Cyclic Redundancy Check-4 (CRC-4) is often used in 2M transmission to identify possible bit errors during in-service error monitoring. CRC-4 is a checksum calculation where the transmitted bits are compared to the received bits. A discrepancy indicates at least one bit error in the received signal. CRC-4 allows for the detection of errors within the 2.048 Mbit/s signal while it is in service. The equipment which originates the 2M data calculates the CRC-4 bits for one sub-multiframe. It inserts the CRC-4 bits in the CRC-4 positions in the next sub-multiframe. The receiving equipment performs the reverse mathematical computation on the sub-multiframe. It examines the CRC-4 bits which were transmitted in the next sub-multiframe, then it compares the transmitted CRC-4 bits to the calculated value. If there is a discrepancy in the two values, a CRC4 error is reported. Each individual CRC-4 error does not necessarily correspond to a single bit error, which is a drawback. Multiple bit errors within the same sub-multiframe will lead to only one CRC-4 error for the block. Errors could occur such that the new CRC-4 bits are calculated to be the same as the original CRC4 bits. CRC-4 error checking provides a most convenient method of identifying bit errors within an in-service system, but provides only an approximate measure (93.75% accuracy) of the circuit's true performance. Consider the MFAS framing, illustrated in Figure 10. Each MFAS frame can be divided into "submultiframes". These are labeled SMF#1 and SMF#2 and consist of 8 frames apiece. We associate 4 bits of CRC information with each sub-multiframe. The CRC-4 bits are calculated for each sub-multiframe, buffered, then inserted into the following sub-multiframe to be transmitted.
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TIME SLOT 0 Bits Multiframe Sub-Multiframe Frame# bit1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 c1 0 c2 0 c3 1 c4 0 c1 1 c2 1 c3 E c4 E bit2 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 bit3 0 A 0 A 0 A 0 A 0 A 0 A 0 A 0 A bit4 1 Sa4 1 Sa4 1 Sa4 1 Sa4 1 Sa4 1 Sa4 1 Sa4 1 Sa4 bit5 1 Sa5 1 Sa5 1 Sa5 1 Sa5 1 Sa5 1 Sa5 1 Sa5 1 Sa5 bit6 0 Sa6 0 Sa6 0 Sa6 0 Sa6 0 Sa6 0 Sa6 0 Sa6 0 Sa6 bit7 bit8
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SMF #1
SMF #2
1 1 Sa7 Sa8 1 1 Sa7 Sa8 1 1 Sa7 Sa8 1 1 Sa7 Sa8 1 1 Sa7 Sa8 1 1 Sa7 Sa8 1 1 Sa7 Sa8 1 1 Sa7 Sa8
Notes: SMF+1: Sub-Multiframe #1, Sa: Spare bit reserved for National Use A: Remote Alarm (FAS Remote Alarm Indication) Frame Alignment Signal Pattern: 0011011 CRC-4 Frame Alignment Signal: 001011 CRC multiframe is not aligned with MFAS timeslot 16 multiframe
SMF#2: Sub-Multiframe#2 E: E-bit Errors c1, c2, c3, c4: CRC bits
Figure 10 CRC-4 Multiframe Format
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E-bit Performance Monitoring
When a 2.048 Mbit/s circuit's terminal equipment is optioned for CRC-4 transmission, E-bit transmission may also be enabled and E-bit performance monitoring of the circuit is possible. Check the specifications of your network equipment. Refer to Figure 11. When this type of terminal equipment detects an incoming CRC-4 error, it will respond by transmitting an E-bit error toward the other terminal. - Test set 2, shown in the diagram, will be able to see the E-bit errors by plugging into a protected monitoring point. - Note that the test set can not see the actual code errors, framing bit errors and CRC errors introduced at the trouble point. The test set can only see the E-bit errors transmitted by Terminal B. E-bit error transmission allows a 2.048 Mbit/s in-service circuit to be reliably monitored for transmission performance from any point on the circuit. Without E-bit error transmission, only a complete circuit failure can be reliably determined at any point on the circuit. - With a complete circuit failure, the test set will see either loss of signal, alarm indication signal, or remote alarm indication.
Test Equip.
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1
Protected Monitor Point Trouble Point (Error Source)
NO ERRORS
TERMINAL EQUIPMENT A CRC Error
TERMINAL EQUIPMENT B
NETWORK
E-bit Error
Test Equip.
Protected Monitor Point
E-BIT ERRORS
Figure 11 E-bit Performance Monitoring
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Errors and Alarms
Troubleshooting an E1 line often involves monitoring for errors or alarms, or intentionally injecting errors or a particular stress test pattern, to see how the system responds. Specifications covering error conditions include ITU-T G.821 and G.826. The requirements also depend on the grade of the line. A key concept for the measurements is availability. A circuit is available for use only when the bit error rate is low enough that the signal can get through and be understood. A circuit is said to be unavailable at the beginning of 10 consecutive severely errored seconds. Errors, errored seconds, and severely errored seconds are not accumulated when the circuit is unavailable. Once a circuit is unavailable, it becomes available only after 10 consecutive seconds without severe errors. Here are the definitions of some important errors and alarms: AIS : Alarm Indication Signal is an unframed all 1s signal. BBE: A Background Block Error is an errored block (a block is a set of consecutive bits associated with a path) not occurring as part of a SES. Bit Errors: Bit errors are bits which are in error. Bit errors are not counted during unavailable time. Bit Slip: A bit slip occurs when the synchronized pattern either loses a bit or has an extra bit stuffed into it. Clock Slips: Clock slips occur when the measured frequency deviates from the reference frequency by one unit interval. Code Errors: A Code Error is a violation of the coding rules; two successive pulse with the same polarity. In HDB3 coding, a Code Error is a bipolar violation that is not part of a valid HDB3 substitution. CRC Errors: CRC-4 block errors . This measurement applies to signals containing a CRC-4 check sequence. Degraded Minutes: A Degraded Minute (DM) occurs when there is a 10-6 or worse bit error rate during 60 available, non-severely bit errored seconds. Errored Block: This is a block in which one or more bits are in error. E-bit Indication: An E-bit is transmitted by the receiving equipment after detecting a CRC-4 error. ES: An errored second is any second in which one or more bits are in error. An errored second is not counted during an Unavailable Second. For G.826, an errored second contains one or more blocks with at least one defect. FALM: Frame ALarM seconds is a count of seconds that have had far end frame alarm (FAS Remote Alarm Indication, RAI), which is when a 1 is transmitted in every third bit of each time slot 0 frame that does not contain the frame alignment signal. FASE: This is a count of the bit errors in the Frame Alignment Signal words received. It applies to both PCM-30 and PCM-31 framing.
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Frequency: Any variance from 2.048 Mbit/s in the received frequency is recorded in hertz or parts per million. LOFS: Loss of Frame Seconds is a count of seconds since the beginning of the test that have experienced a loss of frame. LOSS: Loss Of Signal Seconds is a count of the number of seconds during which the signal has been lost during the test. MFAL: MultiFrame ALarm seconds is a count of seconds that have had far end multiframe alarm (MFAS Remote Alarm Indication, RAI). MFAS Distant Alarm: In this alarm, a 1 is transmitted in every sixth bit of each time slot 16 in the zero frame. SES: A Severely Errored Second has an error rate of 10-3 or higher. Severely errored seconds are not counted during unavailable time. For G.826 block measurements, a SES is a one second period containing 30% or greater errored blocks. Time slot 16 AIS: In this alarm all ones are transmitted in time slot 16 of all frames. UAS: Unavailable time begins at the onset of 10 consecutive severely errored seconds. Unavailable Seconds also begins at a loss of signal or loss of frame. Wander: This is the total positive or negative phase difference between the measured frequency and the reference frequency . The +Wander value increases whenever the measured frequency is one UI larger than the reference frequency. The -Wander increases whenever the measured frequency is one UI less than the reference frequency.
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64 kbit/s Interfaces
Data is generally transmitted at a rate of 64 Kbit/s. Recommendation G.703 provides requirements for different interfaces. For each direction of transmission, three signals can be carried across the interface: 64 kbit/s information, 64 KHz timing, and 8 KHz timing. The 8 KHz timing signal is not mandatory Codirectional Interface A codirectional interface is an interface across which the data and its timing signal are transmitted in the same direction. This interface is used for synchronized networks, or in pleisochronous network with sufficiently stable network clocks. It has a maximum tolerance of +/- 100 ppm for transmitted signals. A balanced pair is required for each direction of transmission. Contradirectional Interface A contradirectional interface is an interface across which the timing for both directions is directed towards the subordinate equipment. It has a maximum tolerance of +/- 100 ppm for transmitted signals. Each direction should have two symmetrical pairs of wires, one pair carrying the data, the other pair carrying the timing.
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ITU-T Recommendations
The following Recommendations are commonly used: G.703: Physical/electrical characteristics of hierarchical digital interfaces. G.704: Synchronous frame structures used at 1544, 6312, 2048, 8488, and 44,736 kbit/s G.706: Frame alignment and cyclic redundancy check (CRC) procedures relating to basic frame structures defined in Recommendation G.704. G.711: Pulse code modulation (PCM) of voice frequencies.
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E1/2.

048 Mbit/s Technology Overview

E1/2.048 Mbit/s Technology Overview

MUX 140 Mbit/s

Figure 1 PDH Hierarchy

E1/2.048 Mbit/s Technology Overview

Voice Signal Volts Sampling

Pulse Amplitude Modulation Volts Quantization 00101101

Figure 2 Converting a Voice Signal

Figure 3 Pulse Code Modulation (PCM)

E1/2.048 Mbit/s Technology Overview

Refer to section 2 of Recommendation G.823

Figure 5 G.703/Table 6, 2.048 Mbit/s Pulse Mask Specifications

E1/2.048 Mbit/s Technology Overview

AMI Line Coding

Note: This voltage is over a 75 unbalanced connection

Figure 6 AMI and HDB3 Line Coding

E1/2.048 Mbit/s Technology Overview

E1/2.048 Mbit/s Technology Overview

One 2.048 Mbit/s Frame Time Slot 0 1 ... 31

Figure 8 FAS Framing Format

E1/2.048 Mbit/s Technology Overview

TS0 ---- TS 16 ---- TS31 Bits 1 2 3 4 5 6 7 8 AB CD A BC D

Figure 9 MFAS Framing Format

E1/2.048 Mbit/s Technology Overview

E1/2.048 Mbit/s Technology Overview

Figure 10 CRC-4 Multiframe Format

E1/2.048 Mbit/s Technology Overview

TERMINAL EQUIPMENT A CRC Error

Protected Monitor Point

Figure 11 E-bit Performance Monitoring

E1/2.048 Mbit/s Technology Overview

E1/2.048 Mbit/s Technology Overview

E1/2.048 Mbit/s Technology Overview

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