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university of applied sciences hamburg

Prof. Dr. J. Reichardt Prof. Dr. B. Schwarz DEPARTEMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE

Synchronous FSM Design: Timing Considerations

All introduced digital circuits and systems have been described at the "Register Transfer Level" comb. logic (RTL): Signals are stored in registers and combinational logic blocks are located between the registers. All flip-flops of a synchronous system are clocked with one common triggering waveform CLK. External asynchronous reset and preset signals should be synchronised in order to avoid coincidence with the clock signals transitions. All other flip-flop resets or presets are controlled synchronously (i. e. by a FSM controller). Digital systems designed by these criteria will work stable without oscillating effects and won't be influenced seriously by any hazards:
Digital Systems
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university of applied sciences hamburg


Prof. Dr. J. Reichardt Prof. Dr. B. Schwarz DEPARTEMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE

Manufacturers will guarantee flip-flop without hazards in output transitions. All glitches which are caused by race glitches during state transitions and static hazards in output logic can be assumed to have a duration less than the clock period. Up to this chapter the main concern and emphasis was concentrated on functional design and analysis issues: so called "front end" of digital system development. Several timing considerations and problem areas were purposely avoided: 1. The designer has to insure that no shift in the triggering clock edge of one flip-flop relative to another will exist (clock skew) which can cause erroneous transitions. 2. All setup tSU and hold time tH requirements (sampling intervall tSU + tH) have to be meet especially under clock skew influence. 3. External asynchronous input signals have to be synchronised with input flip-flops in order to prevent metastable flip-flop states within the digital system. Metastable states of synchronisers have to be prevented either. Several of these activities belong to the "back end" design after having performed the RTL development.

Digital Systems
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university of applied sciences hamburg


Prof. Dr. J. Reichardt Prof. Dr. B. Schwarz DEPARTEMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE

7.1

Timing Considerations in Synchronous Systems with a Data and Control Path


Clock Control Signals FSM Controller Commands Control Signals Data Processing Data Input Data Path Input

A digital system can be partitioned into the control logic section and the data path section: processor module The control logic section consists of all the FSM logic required to generate control signals for the data path section. It receives status signals from the data path section. The data path section consists of all the logic used to store and transform data.

Control Signals

Data Path Output Data Output

Status Signals Digital Systems


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university of applied sciences hamburg


Prof. Dr. J. Reichardt Prof. Dr. B. Schwarz DEPARTEMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE

Timing example of a coupled control and data path


1. Shortly after the first positive clock edge the FSM controller has a transition to new valid state. The data path status signal registers concurrently deliver new values with a D flipflop delay. (at 360 ns) 2. FSM Moore outputs are updated after a delay by the output forming logic. These control signals will influence the data path behaviour with the next clock edge. (at 380 ns) 3. The calculation results of the data path are updated at 400 ns. 4. The next state forming logic of the FSM controller delivers new values at 430 ns. It is more convenient to assume that in most cases data path logic will cause larger delays. All signal updates have to be prepared before the sampling interval of the D flip-flops begins!
Digital Systems
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university of applied sciences hamburg


Prof. Dr. J. Reichardt Prof. Dr. B. Schwarz DEPARTEMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE

Timing example with sampling interval

clk state status signals control signals data output next state

positive slack

Flip-flop output delay is always much larger than the hold time and therefore signal feedback in sequential systems is possible.
Digital Systems
B.Schwarz

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university of applied sciences hamburg


Prof. Dr. J. Reichardt Prof. Dr. B. Schwarz DEPARTEMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE

7.2
7.2.1

Clock Distribution
Clock Skew

In synchronous VLSI designs clock signals are fed to several thousands flip-flops, registers and synchronous RAMs bytes and the wire length of clock signals may exceed several meters. To achieve high system performance the clock frequency is often maximised. This com-

CLK

CLK_D

bination of large clock load and high clock frequency is the cause of large clock delays between flip-flops relative to each other: Clock Skew.
Clock skew has to be less than the sum of all other data signal delays! Digital Systems
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university of applied sciences hamburg


Prof. Dr. J. Reichardt Prof. Dr. B. Schwarz DEPARTEMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE

Timing problem because of large clock skew The second flip-flop has an erroneous output response q2 = '1' because clock skew 20 ns is larger than 10 ns data delay: The "new" data sample will be clocked into the flip-flop by the "old" clock. Data path delays will depend on each special application therefore dedicated clock distribution networks are provided by FPGA and ASIC TSkew hardware. With "balanced clock tree" networks clock skew will be minimised and worst case values are guaranteed by manufactures.
Digital Systems
B.Schwarz

erroneous ! correct

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university of applied sciences hamburg


Prof. Dr. J. Reichardt Prof. Dr. B. Schwarz DEPARTEMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE

Balanced clock tree In the clock tree approach it is extremely important that the clock branches are equally loaded: clock interfacing has to be symmetrically and low resistive, dedicated global clock buffers (BUFG) are strong current drivers in order to ensure steep clock edges. FPGAs designs are supported by an automatic clock tree synthesis with multiple clock distribution networks. In ASIC small clock drivers are placed at the branches over the logic blocks, so they are right there where they are needed.
wrong correct

On chip Digital Systems


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university of applied sciences hamburg


Prof. Dr. J. Reichardt Prof. Dr. B. Schwarz DEPARTEMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE

7.2.2

Gated Clocks

Particularly in low-power CMOS circuits some logic blocks may often be inactive for a certain periods of time. Such a chip with different clock domains is controlled by a gated clock. In case of that no clock enable inputs are available the main clock is used as input to some function: CLK_EN2: Problem: Hazards in the enable input will generate erroneous positive clock edges during CLK = '0' . CLK_EN1: A transparent D latch avoids this malfunction but it ha s to be initialised.

Digital Systems
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university of applied sciences hamburg


Prof. Dr. J. Reichardt Prof. Dr. B. Schwarz DEPARTEMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE

7.2.3

Multiple Clock Domains

Complex VLSI designs are build up with certain logic cores which may have different clock waveforms. Therefore multiple clocks have to be generated by a main clock without relative delay (phase shift) in order to support synchronous behaviour. Reduced clock frequencies can be realised with simple clock dividers. As complex ICs require many different clock domains multiple frequencies are generated on chip with phase-locked-loops (PLLs). The PLL output frequency equals f = fin n mi (n, mi > 1) [H.V.]
Digital Systems
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university of applied sciences hamburg


Prof. Dr. J. Reichardt Prof. Dr. B. Schwarz DEPARTEMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE

7.2.4

Clock Phase Synchronisation

Because of differences in the clock arrival times at the flip-flops of different cores these delays must be compensated to allow proper communication between different cores. The first method is adaptive skew control. The clock skew in each core is made equal to the worst case clock skew by using a chain of inverters. The worst case has to be estimated by separate core timing simulations. The PLL property of locking phases of different signals can be used for compensation of clock skew. The clock phase at node B will be locked to the input reference signal which is the chips main clock [H.V.]. [H.V.] H. Veendrick: DeepSubmicron CMOS ICs. From Basics to ASICs. Kluwer academic publishers, 2nd edition 2000

Digital Systems
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university of applied sciences hamburg


Prof. Dr. J. Reichardt Prof. Dr. B. Schwarz DEPARTEMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE

7.3

Asynchronous Inputs

An asynchronous input is one that can change logic levels at any time, particularly during the sampling interval (decision window) established by the sampling signal clock (CLK): Requests of external devices like keyboard inputs and interrupts. Communication and interfacing of synchronous systems which are under operation with different clock frequencies. All external inputs to D flip-flops, registers, counters and FSMs have to be synchronised to the clock waveform by a special synchroniser circuit. The input to the digital device's flip-flop must meet the setup and hold time requirements otherwise proper transitions cannot be guaranteed and even the metastable state can be entered. The metastable state lies somewhere between a set and a reset condition at midsupply. The time the flip-flop spends in the metastable state tr is called the resolution time. It cannot be predicted which logic level will emerge following exit from the metastable state. Digital Systems
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university of applied sciences hamburg


Prof. Dr. J. Reichardt Prof. Dr. B. Schwarz DEPARTEMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE

7.3.1

Synchroniser for Long Pulses Synchroniser flip-flops setup-time violation

The preceding synchroniser is itself subject to effects of metastability caused by sampling itervall violation. The idea depicted here is that in the event of synchroniser 1 should go metastable it would exit from metastable state long before synchroniser 2 is triggered. This greatly reduces the probability that synchroniser 2 will become metastable and cause malfunction of the connected FSM. The input e will be delayed by the synchroniser up to two clock cycles. Once a metastable event is triggered the probability of the output recovering to high or low level increases exponentially with increased resolved time tr.

Digital Systems
B.Schwarz

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university of applied sciences hamburg


Prof. Dr. J. Reichardt Prof. Dr. B. Schwarz DEPARTEMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE

7.3.2

Synchroniser for Short Pulses

The narrow asynchronous pulse E is first stretched by the pulse triggered D flip-flop, then synchronised by the synchroniser. The stretcher is reset asynchronously by the fed back synchroniser output. Without influence of the input pulse duration the stretcher - synchroniser circuit always generates an output pulse Q1 which will have a high phase of one clock cycle. Output Q1 may become metastable and therefore another flip-flop should be connected to Q1.

Stretcher

Synchroniser

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university of applied sciences hamburg


Prof. Dr. J. Reichardt Prof. Dr. B. Schwarz DEPARTEMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE

7.3.3

Metastability and Mean Time Between Failure of Flip-Flops

The expected time until the output of a single flip-flop with asynchronous data has a metastable event that lasts longer than tr is characterised by the following mean time between failures (MTBF) equation: f : clock frequency of the flip-flop a: asynchronous data frequency exp( tr / ) MTBF( tr ) = T0: flip-flop constant representing the T0 f a time window during which changing Family T0/s tr/ns tSU/ns /ns data invoke a failure 4.010-1 1.5 20 74LS74 77.71 : flip-flop constant related to the set1.82 25 74HCxx 1.510-6 71.55 tling time of a metastable event. 0.17 10 XC95108-20 2.3 9.610-18 Example: An interrupt input signal to a microprocessor which operates with a clock frequency of f = 10 MHz will be synchronised with a 74LS74 type flip-flop. The asynchronous interrupts will appear with a data rate of a = 105 1/s . For an exit from metastable state there will be a resolution time of about: tr = 1/f - tSU = 80 ns . Failures will arise with MTBF(tr = 80 ns) = 3.6 1011 s, so that wrong transitions my be expected within 100 years. Digital Systems
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university of applied sciences hamburg


Prof. Dr. J. Reichardt Prof. Dr. B. Schwarz DEPARTEMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE

7.3.4

Switch Debouncing Circuit

The use of push-button switches is a common problem in digital systems. The asynchronous input signal often produce a phenomenon called switch bounce that derives from the mechanical structure of the witch and the nature of the contact surfaces: Multiple open/close transitions occur. Serious problem can result in a FSM if a high frequency clock catches the bounce signals and introduces false data. A RS latch with input pull up resistors will latch the first bouncing switch : contact noise change of signal value. Oscillating inputs are suppressed because the state with a retained output is forced. Only bounce-free switches are allowed for clock inputs.

moved contact Digital Systems


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university of applied sciences hamburg


Prof. Dr. J. Reichardt Prof. Dr. B. Schwarz DEPARTEMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE

7.4
1.

10 Recommendations for Digital System Design


(following J.F. Wakerly, Digital Design Principles; Prentice Hall 1990) All state-machine outputs shall always be registered. Use clock edge triggered registers never latches. Inputs to FSMs including resets shall be synchronous. Minimise skew of clock signals. Beware of fast paths, because of delayed clock signal waveform. Cross clock domains with the greatest caution and synchronise the interfacing signals. Have no dead states in state-machines. Have no logic with unbroken-asynchronous feedback, in order to avoid the malfunction reports from myriad of test engineers.

2. 3. 4. 5. 6. 7. 8.

9.

All decode logic must be crafted carefully - avoid asynchronicity.

10. Trust not thy simulator - it may be cheating with correct looking results. Digital Systems
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