Dissertation 1: Mohammad Nanda R Marwali

DIGITAL CONTROL OF PULSE WIDTH MODULATED
INVERTERS FOR HIGH PERFORMANCE

UNINTERRUPTIBLE POWER SUPPLIES
DISSERTATION
Presented in Partial Fulfillment of the Requirements for

the Degree Doctor of Philosophy in the
Graduate School of the Ohio State University
By
Mohammad Nanda R. Marwali, M.S.E.E

*****
The Ohio State University

2004
Approved by:
Dissertation Committee
Dr. Ali Keyhani, Adviser ____________________________________
Dr. Hooshang Hemami Adviser
Dr. Donald Kasten Graduate Program in Electrical Engineering
ABSTRACT
This PhD research discusses digital control strategies for three-phase Pulse Width
Modulated (PWM) voltage inverters used in Uninterruptible Power Supplies (UPS) for
single unit and parallel unit systems. For the single inverter system, this research
proposes a novel control strategy which utilizes the perfect Robust Servomechanism
Problem (RSP) control theory to allow elimination of specified unwanted voltage
harmonics from the output voltages under non-linear load conditions and to achieve fast
recovery performance on load transient. This technique is combined with a discrete
sliding mode current controller that provides fast current limiting capability needed for
overload or short circuit conditions. For the parallel inverter system, a combination of
two control methods is proposed: average power control method and droop control
method. The average power method is used in order to overcome the sensitivity of load
sharing to output voltage/current measurement errors and mismatch wiring impedances
between units, while the droop method allows the control to still maintain proper load
sharing in the event that inter-unit communication is lost. In addition to this, a harmonic
droop scheme for sharing of harmonic content of the load currents is introduced based on
the proposed single unit control. Control analysis, experimental and simulation studies,
using two parallel three-phase PWM inverters, are presented to show the effectiveness of
the proposed control strategies, both for single and parallel inverter systems.
ii
Dedicated to Selvy, Arfan, and Farhan
iii
VITA
October 4, 1969 …………………………Born – Medan, Indonesia
1993 ……………………………………..B. S. Electrical Engineering,
Institut Teknologi Bandung
1995-2000………………………………..Graduate Research Associate
Electrical Engineering Department
Ohio State University
1997 ……………………………………..M. S. Electrical Engineering
Ohio State University
PUBLICATIONS
Research Publication
1. M.N. Marwali and A. Keyhani, “Control of Distributed Generation Systems – Part I :
Voltages and Currents Control,” IEEE Transaction on Power Electronics, Vol. 19,
No. 6, pp. 1541-1550, November 2004
iv
2. M.N. Marwali, J.-W. Jung, and A. Keyhani, “Control of Distributed Generation
Systems – Part II : Load Sharing Control,” IEEE Transaction on Power Electronics,
Vol. 19, No. 6, pp. 1551-1561, November 2004
3. A. Keyhani, M.N. Marwali, L.E. Higuera, G. Athalye, G. Baumgartner, “An
integrated virtual learning system for the development of motor drive systems,” IEEE
Transactions on Power Systems, Vol. 17 , No. 1, pp. 1-6, Feb. 2002
4. M.N. Marwali, A. Keyhani, and W. Tjanaka, “Implementation of indirect vector
control on an integrated digital signal processor-based system,” IEEE Transactions
on Energy Conversion, Vol.14, No. 2 , pp. 139 – 146, June 1999
FIELDS OF STUDY
Major Field: Electrical Engineering
Major Area of Specialization: Electrical Machines, Power Electronics, and Control
Systems
v
TABLE OF CONTENTS
Page
Abstract ...............................................................................................................................ii
Vita .....................................................................................................................................iv
Table of Contents ............................................................................................................... vi
List of Figures ....................................................................................................................ix
List of Tables...................................................................................................................xvii
List of Abbreviations......................................................................................................xviii
Chapters
1. Introduction ................................................................................................................... 1
1.1 Background .......................................................................................................... 1

1.2 Literature review .................................................................................................. 6
1.2.1 Low THD output voltage control and inverter current control ................ 6
1.2.2 Load sharing methods .............................................................................. 8
1.3 Research outline ................................................................................................. 23
1.3.1 Development of voltage and current control for single inverter
system..................................................................................................... 23
1.3.2 Development of load sharing technique for paralleled inverters
system..................................................................................................... 25
1.4 Chapters organizations ....................................................................................... 26
2. Control of single inverter system ................................................................................ 29
2.1 Theoretical background...................................................................................... 29
vi
2.1.1 State space model of the plant................................................................ 30
2.1.2 Perfect control of robust servomechanism problem............................... 39
2.1.3 Discrete-time sliding mode control ....................................................... 43
2.2 Control system development.............................................................................. 45

2.2.1 Discrete-time sliding mode current controller ....................................... 46
2.2.2 Voltage controller design using discrete perfect RSP............................ 49
2.3. Practical considerations...................................................................................... 54
2.3.1 Balanced realization of the harmonic servo compensators .................... 54
2.3.2 Tuning the optimum stabilizing gains for desired dynamic
performance............................................................................................ 55
2.3.3 Matlab script for control gains calculations ........................................... 56
3. Analysis and simulations of the single inverter control .............................................. 63
3.1 Robust stability analysis..................................................................................... 64

3.1.1 Robust stability analysis using structured singular value (µ)................. 64
3.1.2 Uncertain open loop model .................................................................... 67
3.1.3 Using matlab to derive uncertain closed loop model ............................. 77
3.1.4 Computing individual perturbation frequency response and the
structured singular value using matlab................................................... 82
3.2 Tuning the controller performance using w p , wS , and wSH ............................... 83
3.3 Simulations of the complete system................................................................... 95
4. Experimental results of single inverter control ......................................................... 107
4.1 5 kVA experimental test bed............................................................................ 107

4.2 Experimental results......................................................................................... 111
4.2.1 Performance measures of the proposed control ................................... 111
4.2.2 Comparison with synchronous reference frame control with pi
controllers............................................................................................. 115
5. Control of parallel inverters ...................................................................................... 118
5.1 Combined droop method and average power control ...................................... 118
vii
5.2 Stability analysis of combined droop and average control method ................. 123
5.3 Generation of the reference angle θ ref ............................................................. 132
5.4 Harmonic sharing ............................................................................................. 134
6. Simulation and experimental studies of parallel inverters control............................ 138
6.1 Simulation system implementation .................................................................. 138

6.1.1 Main diagram ....................................................................................... 139
6.1.2 PWM inverter block ............................................................................. 141
6.1.3 DSP output ........................................................................................... 145
6.1.4 Load sharing control............................................................................. 149
6.1.5 Voltage controller and current controller ............................................. 154
6.2 Simulations results ........................................................................................... 160
6.2.1 Simulations conditions ............................................................................ 160
6.2.2 Steady state load sharing performance.................................................... 162
6.2.3 Transient load sharing performance........................................................ 169
6.2.4 Synchronization to bypass and free-running mode................................. 173
6.2.5 Load sharing with unequal proportion .................................................... 181
6.2.6 Lost of inter-unit communication ........................................................... 186
6.3 Experimental test bed ....................................................................................... 189
6.4 Experimental results......................................................................................... 191
7. Conclusions and future work .................................................................................... 195
7.1 Conclusions ...................................................................................................... 195

7.2 Future work ...................................................................................................... 197
Bibliography.................................................................................................................... 199
Appendices
A. Matlab script for control gains calculations ............................................................... 212
B. Matlab script for robust stability analysis of single inverter control system.............. 219
viii
LIST OF FIGURES
Figures Page
1.1 Typical single UPS system configuration .................................................................. 2
1.2 IGBT PWM Inverter system ...................................................................................... 4
1.3 A typical parallel UPS configuration ......................................................................... 5
1.4 Instantaneous Current Sharing with Master/Slave Control Type 1 [89, 90]............ 10
1.5 Instantaneous Current Sharing with Master/Slave Control Type 2 ([91]) ............... 12
1.6 Two inverters connected to a load............................................................................ 13
1.7 Difference from average power control ................................................................... 16
1.8 Frequency and Amplitude Droop Technique ........................................................... 18
1.9 Droop Characteristics............................................................................................... 19
1.10 Power Sharing using Signal Injection Method......................................................... 22
2.1 IGBT PWM Inverter Systems for UPS .................................................................... 31
2.2 Delta-Wye Transformer model ................................................................................ 31
2.3 Equivalent circuits in the DQ0 stationary reference frame ...................................... 38
2.4 Overall control system ............................................................................................. 45
2.5 Control timing diagram ............................................................................................ 46
ix
2.6 Output voltages controller using robust servomechanism controller....................... 54
3.1 Representation of a linear system with uncertainties ............................................... 65
3.2 Open loop model of the nominal plant..................................................................... 67
3.3 LFTs for 1 , 1 ,1 , and 1 ....................................................... 70

cinv linv cload ltrans
3.4 LFTs for rinv , rtrans , yrload , and yl load ........................................................................ 70
3.5 Block diagram of the nominal plant......................................................................... 72
3.6 Interconnection of the nominal open loop plant with ∆ to form uncertain open
loop model................................................................................................................ 73
3.7 Uncertain closed loop model.................................................................................... 77
3.8 The RSP and DSM controllers ................................................................................. 79
3.9 Transient response for Case 1: w p = 0.5 , wS = 5 × 105 , and wSH = wS (Top:
Output voltage and its reference, Middle: Load current, Bottom: RMS
variations of output voltage). ................................................................................... 85
3.10 Transient response for Case 4: w p = 0.005 , wS = 5 × 105 , and wSH = wS (Top:
Output voltage and its reference, Middle: Load current, Bottom: RMS
3.11 RMS output voltage variations during 0 to 100% and 100% to 0 for
different w p ,and wSH = wS ...................................................................................... 86
3.12 Upper bound of the structured singular values for different w p ,and wSH = wS ....... 87
x
3.13 Transient response for Case 6: w p = 0.5 , wS = 5 × 105 , and wSH = 0.01 × wS
(Top: Output voltage and its reference, Middle: Load current, Bottom: RMS
3.14 Transient response for Case 9: w p = 0.005 , wS = 5 × 105 , and wSH = 0.01 × wS
(Top: Output voltage and its reference, Middle: Load current, Bottom: RMS
3.15 RMS output voltage variations during 0 to 100% and 100% to 0 for
different w p ,and wSH = 0.01 × wS ............................................................................ 90
3.16 Upper bound of the structured singular values for different w p ,and
wSH = 0.01 × wS ........................................................................................................ 91
3.17 Individual-perturbation frequency response for system with controller in Case

9. (X-axis in each plot is frequency in rad/sec)........................................................ 92
3.18 Pole-zero map of closed loop uncertain system for different values of
individual-perturbation in inverter filter inductance parameter ............................... 94
3.19 Simulation results for balanced full resistive load ................................................... 97
3.20 Simulation results for unbalanced single-phase resistive load................................. 98
3.21 Simulation results for unbalanced two-phase resistive load .................................... 99
3.22 Simulation results for 0-100% resistive load transient........................................... 101
3.23 Simulation results for 0-100% resistive load transient........................................... 102
3.24 Simulation result: Tracking of fundamental references ......................................... 104
3.25 Simulation result: Fundamental with 5th harmonic references tracking................. 104
xi
3.26 Simulation result: Fundamental with 7th harmonic references tracking................. 105
3.27 Simulation result: Fundamental with 5th and 7th harmonic references tracking..... 105
3.28 Simulation result: Short circuits at the output terminals ........................................ 106
4.1 The 5 kVA Experimental Test Bed System ........................................................... 109
4.2 Three single-phase diode rectifier as non-linear load ............................................ 110
4.3 Steady state linear load (a) 100% resistive balanced (b) 100% 0.8pf load (c)
100% resistive unbalanced (phase A unloaded) (d) 100% resistive unbalanced
(phase A&B). Top: load currents; middle: load voltages; bottom: inverter
voltages. ................................................................................................................. 113
4.4 Resistive load transient: 0% to 100%. Top: three-phase load currents, bottom:
three-phase load voltages resistive load transient .................................................. 113
4.5 Resistive load transient:100% to 0% Top: three-phase load currents, bottom:

three-phase load voltages resistive load transient .................................................. 114
4.6 Three-phase short-circuit on output terminals. Top: inverter currents, middle:

load voltages, and bottom: inverter voltages.......................................................... 114
4.7 Synchronous Reference Frame Voltage and Current Control with PI controllers. 116
4.8 Steady state performance comparisons under non-liner load (a) using proposed
control (b) PI controllers. Top: three phase load currents. Bottom: Three-phase
load voltages........................................................................................................... 117
5.1 Combined droop and average power methods for load sharing control ................ 119
5.2 DQ0 model of paralleled inverters ......................................................................... 121
5.3 Two inverters connected to a load.......................................................................... 124
xii
5.4 System responses (a) Case 1, (b) Case 2 (c) Case 3............................................... 131
5.5 Generation of reference angle for the case when bypass source is available......... 132
5.6 Generation of reference angle for the case when bypass source is available......... 133
5.7 Harmonic Drooping thru the harmonics compensators pole shifting .................... 135
5.8 Output voltages controller using robust servomechanism controller with

harmonic drooping ................................................................................................. 137
6.1 Simulink main diagram of the system.................................................................... 140
6.2 PWM Inverter block............................................................................................... 142
6.3 Power circuitries..................................................................................................... 143
6.4 DSP Output block diagrams................................................................................... 146
6.5 DQ Transformations & States Calculations ........................................................... 147
6.6 DQ Power Calculation ........................................................................................... 148
6.7 Load Sharing Control Block Implementation ........................................................ 149
6.8 P and Q Sharing Blocks ......................................................................................... 150
6.9 Individual axis P and Q Sharing Implementation .................................................. 152
6.10 Masked-subsystems of P-Sharing and Q-Sharing for initializing load sharing

control gains ........................................................................................................... 153
6.11 Reference Angle Generation implementation ........................................................ 154
6.12 Voltage Controller Implementation ....................................................................... 155
xiii
6.13 Vq (Vd) Control Implementation........................................................................... 157
6.14 Variable Frequency Harmonic Control Implementation........................................ 158
6.15 Sliding Mode Current Controller Implementation ................................................. 159
6.16 Output Currents of Unit 1 and Unit 2 under linear balanced resistive load ........... 164
6.17 Output Currents of Unit 1 and Unit 2 under 0.8 lagging balanced load ................ 165
6.18 Output Currents of Unit 1 and Unit 2 under 0.9 lagging balanced load ................ 166
6.19 Output Currents of Unit 1 and Unit 2 under single-phase resistive load ............... 167
6.20 Output Currents of Unit 1 and Unit 2 with harmonic drooping enabled................ 168
6.21 Output Currents of Unit 1 and Unit 2 with harmonic drooping disabled (gains
set to zero) .............................................................................................................. 169
6.22 DQ real (top) and reactive (bottom) powers of Unit 1 and Unit 2 ......................... 170
6.23 Output currents of Unit 1 and Unit 2...................................................................... 170
6.24 Phases and Amplitude Adjustments of Unit 1 and Unit 2 ..................................... 171
6.25 RMS load voltages during simulation.................................................................... 171
6.26 Load transient from Balanced resistive to no-load................................................. 172
6.27 Load transient from no-load to balanced 0.8 pf lagging ........................................ 172
6.28 Load transient from balanced 0.8 pf lagging to single-phase resistive .................. 173
6.29 Unit and Bypass phase synchronization error ........................................................ 174
xiv
6.30 Units Output Frequency ......................................................................................... 174
6.31 Units DQ real (top) and (reactive) powers ............................................................. 175
6.32 Units Output Currents ............................................................................................ 175
6.33 Modifying the Reference Angle Generator Block for simulating mismatched
crystal clock frequencies ........................................................................................ 177
6.34 DQ real (top) and reactive (bottom) powers during free-run with mismatched
frequency and frequency locking disabled............................................................. 178
6.35 Units phases adjustments during free-run with mismatched frequency and
frequency locking disabled .................................................................................... 178
6.36 Frequency locking adjustments during free-run with mismatched frequency ....... 179
6.37 DQ real (top) and reactive (bottom) powers during free-run with mismatched
frequency and frequency locking enabled.............................................................. 180
6.38 Units phases adjustments during free-run with mismatched frequency and
frequency locking enabled ..................................................................................... 180
6.39 Setting up the control gains for unlike units sharing simulations .......................... 182
6.40 Steady state performance of load sharing with unequal proportion....................... 183
6.41 DQ real (top) and reactive (bottom) powers of Unit 1 and Unit 2 for unequal
load sharing proportion .......................................................................................... 184
6.42 Phases and Amplitude Adjustments of Unit 1 and Unit 2 for unequal load
sharing proportion .................................................................................................. 185
6.43 Units Output Currents during transient for unequal load sharing proportion ........ 185
6.44 COMM_OK flag was cleared at t=4 sec to simulate lost of communication ........ 186
xv
6.45 Units output DQ real (top) and reactive (bottom) powers when communication
was lost at t=4 sec .................................................................................................. 187
6.46 Units’ output currents when communication was lost at t= 4 sec.......................... 187
6.47 Units output currents transient from 8kW to 4 kW after communication was
lost .......................................................................................................................... 188
6.48 Units output currents transient from 4kW to 8 kW after communication was
lost .......................................................................................................................... 188
6.49 Experimental Test Bed for Parallel Inverters ......................................................... 190
6.50 Steady state load sharing performance for balanced resistive load........................ 192
6.51 Steady state load sharing performance for unbalanced resistive load.................... 192
6.52 Steady state load sharing performance for balanced non-linear rectifier load....... 193
6.53 Dynamic performance: l00% to 0% and 0% to 100% load changes. Each trace
box shows the two units output currents for phase a, b, and c (from top to
bottom) ................................................................................................................... 193
6.54 Dynamic performance 0% to 100% load acquire (zoom in of Fig. 6.53). ............ 194
6.55 Unit 2 is reconnected with different load applied on each phase. Phase a and
phase b: linear resistive load. Phase c: single-phase non-linear load..................... 194
xvi
LIST OF TABLES
Tables Page
3.1 Output voltages regulation .......................................................................................... 96
4.1 Output voltages regulation ........................................................................................ 112
4.2 Output voltages THD ................................................................................................ 112
6.1 Components Mismatches .......................................................................................... 160
6.2 Steady state results: Resistive Balanced Load (2 x 0.8 x 5.0 kW= 8.0 kW)............. 164
6.3 Steady state results: 0.8 lagging Balanced Load (2 x 5kVA 0.8 pf lag) ................... 165
6.4 Steady state results: 0.9 leading Balanced Load (2 x 5kVA 0.9 pf lead).................. 166
6.5 Steady state results: Single-phase Loaded (2 x 4.0 kW/3=2.666 kW on phase A .... 167
xvii
LIST OF ABBREVIATIONS
A/D : Analog/Digital
AC : Alternating Current
CSI : Current Source Inverter
DC : Direct Current
DQ/DQ0 : Direct Quadrature/ Direct Quadrature Zero
DSM : Discete Sliding Mode Controller
DSP : Digital Signal Processor
IGBT : Insulated Gate Bipolar Transistor
LFT : Linear Fractional Transformation
MIMO : Multi Input Multi Output
PWM : Pulse Width Modulated
PLL : Phase Locked Loop
RMS : Root Mean Square
RSP : Robust Servomechanism Problem
THD : Total Harmonic Distortion
UPS : Uninterruptible Power Supplies
VSI : Voltage Source Inverter
ZOH : Zero Order Hold
xviii
CHAPTER 1
INTRODUCTION
1.1 Background
With the growth of internet and information technology industry, the need for
reliable continuous power to protect data integrity and ensuring uninterrupted service is
an important requirement. Uninterruptible Power Supplies (UPS) as a means for ensuring
continuous power delivery to a system with sensitive and critical loads have become
increasingly important [1-3].
A typical UPS configuration is shown in Fig. 1.1. The UPS system provides two
paths of power flow to the load: i) rectifier-inverter path (through the rectifier (AC-DC
converter), battery, and the inverter (DC –AC converter)), ii) bypass static switch path.
When the input power from the utility is available, the rectifier provides a means for
charging the battery, while the inverter provides regulated output voltages to the load.
When the input utility is lost, the battery, which is in parallel with the dc bus of the
inverter, provides an emergency back up power to the inverter, thereby ensuring no
interruption of the power delivery to the load. The bypass static switch provides a means
for fast transfer of power to the load from the inverter path to the utility input or another
1
AC power source, and vice versa. Typically, a secondary backup power source such as an
AC generator is connected to the bypass static switch to provide a longer period of power
supply to the load than the battery. In the event of utility loss, the battery and inverter
system maintains uninterrupted power delivery to the load for a sufficient amount of time
until the secondary power can be made available, at which time the load may be
transferred to the static bypass switch path.
BYPASS STATIC
SWITCH
BYPASS SOURCE
BATTERY
LOAD
UTILITY INPUT
OUTPUT
RECTIFIER INVERTER
Figure 1.1 Typical single UPS system configuration
The power delivered by the inverter system must satisfy certain requirements in
order to qualify as being regulated power. First, the inverter output voltages at steady
state must be maintained at certain Root Means Square (RMS) value independent of the
load conditions [6]. For this requirement, a load regulation at certain load is defined as
the percentage deviation of the output voltage RMS at that load from its value at no load.
A high performance UPS must present low load regulation number for all types of load
up to its rated power level. Second, the inverter must be able to provide output voltages
2
with low total harmonic distortion (THD) under various load conditions. The latter is an
important requirement, since the high harmonic load currents produced by non-linear
loads such as rectifiers used in typical computer power supplies, can significantly distort
the output voltage of the inverter [7, 8]. This distorted output voltage is undesirable to
other types of loads such as electrical motors that may be connected to the UPS, since it
can result in unnecessary power loss in the form of heat and mechanical vibrations in the
motor. The third requirement relates to the ability of the inverter to produce an output
voltage with minimal undershoot and overshoot and provides fast recovery in the event of
load transient (load change). A recovery time of one line cycle or less is typically
required from a high performance UPS, with the RMS output voltage deviates less than
5% under full-load transients.
In addition to providing regulated power to the load, the inverter in a UPS system
must be able to provide system protection from excessive overload conditions such as
short circuit to ground faults. In these events, rather than just turning itself off, the
inverter must be able to maintain an adequate level of inverter currents for sufficient
amount of time necessary to trigger upstream circuit breakers to open and clear the faults.
For this requirement, the inverter must have a fast inverter current limiting control to
response to a sudden short circuit condition at its terminal.
3
The most common inverter circuits currently used in UPS systems are the Pulse
Width Modulated (PWM) inverters using Insulated Gate Biolar Transistor (IGBT) power
switches, as shown in Fig. 1.2 for a three-phase electrical system. The inverter system
consists of a three-phase IGBT bridge converter with L-C filter at the output and
optionally a three-phase transformer that provides voltages transformation and isolation.
⎡Vinvab⎤
⎡Vloadan ⎤
⎡Vpwmab⎤ ⎢Vload ⎥
⎢Vpwm ⎥ ⎢Vinv ⎥
⎢ bc ⎥ ⎢ bc ⎥ ⎢ bn ⎥
⎢⎣Vpwmca ⎥⎦ ⎢⎣Vinvca ⎥⎦ Delta-Wye Transformer ⎢⎣Vloadcn ⎥⎦
Linv
x
Iinva
U
Iloada L
Cgrass
Cinv Cinv n
O
Vdc Iinvb A
y
V
Iloadb
D
Iinvc W
z
Iloadc
gating signals DSP system voltages and currents

measurement
Figure 1.2 IGBT PWM Inverter system
4
As the power requirement of a system supplied by a UPS grows, two options are
possible, either to use a large UPS unit or to use multiple UPS units in parallel. The
former approach may be undesirable because of higher initial cost, installation
difficulties, and reliability. Paralleling UPS units, by contrast, provides for system
expansion and redundancy. Fig. 1.3 shows a typical parallel UPS units’ system setup.
BYPASS STATIC UPS1

SWITCH
BYPASS SOURCE
UTILITY INPUT
BATTERY
LOAD
OUTPUT
RECTIFIER INVERTER
BYPASS STATIC UPS2

SWITCH
BATTERY
RECTIFIER INVERTER
Figure 1.3 A typical parallel UPS configuration
One of the technical challenges involved in paralleling UPS units is to ensure that
the load is shared properly by each inverter operating in parallel while still maintaining
the voltage regulation at the load. To achieve this, a proper load sharing technique must
5
be employed. The difficulties in the load sharing are due to the non-uniformity of the
units, component tolerances, and variations in the connecting line impedances. A good
load sharing technique must be able to overcome these effects.
The research work described in this dissertation focuses on development of digital
control algorithms for a single IGBT PWM inverter shown in Fig. 1.2 and load sharing
control for the PWM inverters in the parallel configuration shown in Fig. 1.3. Several
prior works have been published in the area of control of PWM inverters for UPS
applications. This PhD research addresses some of the issues raised on the previous
works and presents alternative methods for achieving better performances and for
satisfying the requirements of a high performance UPS system outlined above.
1.2 LITERATURE REVIEW
1.2.1 Low Total Harmonic Distortion Output Voltage Control and Inverter Current
Control
Techniques for producing low Total Harmonic Distortion (THD) in PWM
inverters (single-phase or three-phase) have discussed in several prior works. In the early
days, the carrier-modulated PWM techniques such as the triangular wave comparison
type PWM were very popular [9-11]. Microcomputer based techniques using
preprogrammed PWM pattern have also been utilized [12-21]. In these techniques, the
PWM patterns are generated by computing switching edges which satisfy certain
performance criteria such as controlling the fundamental component and eliminating
specified harmonics. Two main disadvantages of these techniques are: slow voltage
6
regulation response due to average voltage control, and phase displacement between the
reference sine wave and the filter output varies with the load [19]. More recent PWM
techniques also include time optimal response switching PWM [22-25].
With the advances in Digital Signal Processing (DSP) Technology, digital
instantaneous real time control of voltage and current for PWM inverters has been the
focus of many research works. Among these are the real-time deadbeat-controlled PWM
[26-33] and other techniques based on instantaneous feedback controls [34-57]. These
techniques may achieve very fast response for load disturbances when properly designed,
but it is also known that these systems have a high THD for non-linear load (crest-load)
[19]. Techniques based on sliding mode control theory [58-65] and intelligent control
using fuzzy logic or neural networks [66-75] have also been attempted. Like the
previously mentioned techniques, these techniques also lack the ability to completely
reject the harmonic disturbances in the output voltage waveforms due to non-linear loads.
Recently, the use of the internal model principle to achieve very low THD output
voltage in single-phase PWM inverters has been reported [76-85]. The theory is based on
the internal model principle proposed by [86] which states that the asymptotic tracking of
controlled variables toward the corresponding references in the presence of disturbances
(zero steady state tracking error) can be achieved if the models that generate these
references and disturbances are included in the stable closed loop systems. In other
words, if we include the frequency modes of the references and the disturbances to be
eliminated in the control loop, then the steady state error will not contain these frequency
modes. Applying the internal model principle into the output voltages control in a three-
7
phase PWM inverter means that the fundamental frequency mode (50 Hz or 60 Hz) has to
be included in the controller since the references vary at this frequency. Elimination of
the voltages errors due to the load currents at other harmonics frequencies can then be
achieved by including the frequency modes of these harmonics into the controller.
The repetitive control — first introduced for UPS applications in [76] —
guarantees zero steady state error at all the harmonic frequencies less than half of the
sampling period. However, the repetitive control is not easy to stabilize for all unknown
load disturbances and cannot deliver very fast response for fluctuating load [77]. In [76],
the latter problem is solved by including a ‘one sampling ahead preview controller”, and
in [77-85], the stability result of [76] is enhanced by providing adaptive mechanisms for
unknown load disturbances.
1.2.2. Load Sharing Methods
The following sub sections provide reviews of existing techniques for paralleling
inverters available in the literature [89-114]. The basic methods have been classified into
four different types:
1. Instantaneous Current Sharing with Master/Slave Control [89-96]
2. Difference from Average Active/Reactive Power Method [97-101]
3. Frequency and Amplitude Droop Method [102-112]
4. Signal Injection Method for Reactive and Harmonic Current Sharing [113, 114]
A summary of each type is presented and its advantages and disadvantages are discussed
in the following sub sections.
8
1.2.2.1 Instantaneous Current Sharing with Master/Slave Control [89-96]
The instantaneous current sharing technique is a load sharing technique that uses
the load current as a feedback signal to the paralleled inverters in order for them to share
the output currents equally. In this technique, one of the inverters acts as a master
controller that has the responsibility for establishing the required voltage at the load,
while the other inverters acting as slave controllers, will try to match their output currents
to the load current feedback signal.
Fig. 1.4 shows a block diagram of the instantaneous load sharing technique as
described in [89] and [90]. Each inverter in Fig. 1.4 consists of a PWM inverter with
output LC filter and transformer. Each inverter is equipped with a voltage regulator,
which regulates the capacitor voltage, and an inner inverter current control loop. Unit no.
1 acts as the master controller and is responsible for establishing the load voltage based
on the reference voltage. In typical UPS applications, the reference voltage is either
synchronized to an external bypass AC voltage, or to an internal oscillator signal. The
master control contains an outer RMS voltage control loop for load voltage regulation.
The output current produced by the master unit is distributed to the other units that act as
slaves. Each of the slave inverters then tries to regulate its output current to match the
master’s load current. This is made possible by the inclusion of an outer load current
control loop in each of the slave units.
9
Synchronization SYNCH. Vref (t ) = Vm sin (ωt + φ )
signal LOGIC
&
SINEWAVE
GENERATOR
Vref (t )
Instantenous UNIT 1 (MASTER)
Current Controller
Cap Voltage Controller
*
V pwm PWM
Inverter
Vrms* + + V1 VL
+ PWM LOAD
PI VC CC
Method
- - -
I1
V1
Vrms
RMS
I L1
Vref (t )
UNIT 2 (SLAVE)
Instantenous
Current Controller
*
I L1 V pwm PWM
Inverter
+ V1
+ + PWM
PI VC CC
Method
- - -
I2
I L2 V2
Vref (t )
Instantenous UNIT 3 (SLAVE)
Current Controller
I L1 *
V pwm PWM
Inverter
+ V1
+ + PWM
PI VC CC
Method
- - -
I3
I L3 V3
Figure 1.4 Instantaneous Current Sharing with Master/Slave Control Type 1 [89, 90]
10
Note that in the control scheme shown in Fig. 1.4, the reference voltage will need
to be distributed to all the inverters in order for them to generate synchronized voltage at
the output. This means that each inverter must be equipped with a Phase Locked-Loop
for synchronization to this reference signal. This requirement is eliminated in [91] which
presented a variation of the instantaneous load current sharing technique. In [91], the
slave units are configured as current source PWM inverters rather than as voltage
sources. Fig. 1.5 shows a block diagram of the load sharing control in [91]. The master
unit is a voltage source PWM inverter (VSI) with a single loop voltage control. The total
load current produced is measured by an additional controller box called Parallel
Distribution Center which in turn sends proportion of this total load current to each slave
based on its power rating. Each slave unit controls its output current based on the current
command sent by the Parallel Distribution Center. Other variations of the instantaneous
control technique are given in [92-96].
The advantage of the instantaneous load current technique is that it provides fast
load sharing response since the control is performed instantaneously. However, the need
for having one unit to act as a master unit represents drawback to this method, since it
provides for the occurrence of a single point failure, i.e. if the master unit fails the overall
system will be down. Also the needs to distribute instantaneous analog current signal to
each of the inverters in parallel may present some practical problems, such as noise,
measurement grounding issues or failure/broken wires, which can cause undesirable
operations.
11
UNIT 1 (MASTER-VSI)
Vref (t ) = Vm sin (ωt + φ )
Voltage Controller
PWM
Inverter
SYNCH. VL
Synchronization
LOGIC + PWM
LOAD
& VC
signal Method
SINEWAVE
GENERATOR -
VL
UNIT 2 (SLAVE-CSI)
Current Controller
PWM
Inverter
IL I L* 2 + PWM
CC
Method
-
I2
POWER
DISTRIBUTION
CENTER
UNIT 3 (SLAVE-CSI)
Current Controller
PWM
Inverter
*
I L3 + PWM
CC
Method
-
I3
Figure 1.5 Instantaneous Current Sharing with Master/Slave Control Type 2 ([91])
12
1.2.2.2 Difference from Average Active/Reactive Power Method [97-101]
This technique of load sharing is based on the power flow theory in an ac system,
which states that the flow of the active (P) and reactive power (Q) between two sources
can be controlled by adjusting the power angle and the voltages magnitudes. It can be
shown that the active power flow P is predominantly controlled by the power angle,
while the reactive power Q is predominantly controlled by the voltages magnitudes.
Figure 1.6 shows two inverters represented by two voltage sources connected to a load
through line impedance represented by pure inductances L1 and L2 for analysis
simplification purpose.
E1∠δ 1 V∠0 E2∠δ 2
jωL1 jωL2
I1 I2
Figure 1.6 Two inverters connected to a load
The complex power at the load due to inverter 1 is given by:
S1 = P1 + jQ1 = V ⋅ I1
*
(1.1)
*
where I 1 is the complex conjugate of the inverter 1 current and is given by:
*
⎡ E cos δ 1 + jE1 sin δ 1 − V ⎤
I =⎢ 1
*
⎥ (1.2)
jωL1
1
⎣ ⎦
13
*
⎡ E cos δ 1 + jE1 sin δ 1 − V ⎤ (1.3)
∴ S1 = V ⎢ 1 ⎥
⎣ jωL1 ⎦
This gives the active and reactive power flowing from inverter 1 as:
VE1
P1 = sin δ 1 (1.4)
ωL1
VE 1 cos δ 1 − V 2
Q1 = (1.5)
ωL1
Similarly for the second inverter
VE 2
P2 = sin δ 2 (1.6)
ωL2
VE 2 cos δ 2 − V 2
Q2 = (1.7)
ωL2
From equations (1.4) thru (1.7), it can be seen that, if δ 1 and δ 2 are small then the real
power flow is mostly influenced by the power angles δ 1 and δ 2 , while the reactive
power flow predominantly depends on the inverter voltages E1 and E 2 . This means that
to certain extent the real and reactive power flow can be controlled independently. Since
controlling the frequencies dynamically controls the power angles, the real power flow
control can be equivalently achieved by controlling the frequencies of the voltages
generated by the inverters.
Fig. 1.7 shows a block diagram of this load sharing technique for two inverters in
parallel. Each inverter controls its share of real and reactive power to match the
corresponding average power by modifying its internal reference voltage. In order for
each unit to know the average power, the real and reactive power of each unit must be
communicated by some means digitally or analog. In [97-99], the active and reactive
14
powers are obtained by decomposing the load current of each UPS into its active and
reactive components. In [100] and [101] the real and reactive powers deviations are
obtained from the differences of the output currents of the two inverters PI controllers are
used to force each power to equal its average. The real power affects the amplitude of the
reference voltage, while the reactive affects the phase or the frequency. Each inverter
then regulates its voltage to the modified reference voltage as shown in Fig. 1.7.
Note that this technique does not require any units to act as a master or slaves,
hence preventing single point failure in the system. Also good real and reactive power
sharing control can be achieved with control update in the order of once every line cycle.
Therefore, the communication link between each unit can be done digitally to achieve
better noise immunity.
One of the drawbacks of this technique is the fact that the average power control
only affects the fundamental component of the load current. It does not force the
harmonic contents of the load current to share. Hence, if the load is non-linear then
harmonic fluctuating currents will flow amongst the inverters. This is undesirable since it
increases losses in the system. Another disadvantage of this method is that it requires
communication link between inverters for the common synchronization signal and the
sharing of power information.
15
INVERTER 1
Vnom
Vref 1 ( k ) = Vm1 sin θ1 (k )

Pavg + ∆P1 ∆V1 Vm1
PI
- Voltage Controller Current Controller
-
+
P1 SINE WAVE + *
REFERENCE VC CC V pwm
GENERATION
- -
V1 I1
Qavg + ∆Q1 ∆θ1 θ1
PI
-
-
θ sync1 (k ) Pavg = (P1 + P2 ) 2
Q1
Qavg = (Q1 + Q2 ) 2
PLL
P1 Q1
Common reference
synchronization signal
P2 Q2
INVERTER 2 Pavg = (P1 + P2 ) 2
PLL Qavg = (Q1 + Q2 ) 2
θ sync (k )
Qavg + ∆Q2 ∆θ 2 θ2
PI
- Voltage Controller Current Controller
-
+
Q2 SINE WAVE + *
REFERENCE VC CC V pwm
GENERATION
- -
∆V2 V2 I2
Pavg + ∆P2 Vm 2
PI
-
-
Vref 2 (k ) = Vm2 sin θ 2 (k )
P2 Vnom
Figure 1.7 Difference from average power control
16
1.2.2.3 Frequency and Amplitude Droop Method [102-112]
This technique uses the same philosophy used in conventional power system with
multiple generators. The generators share the system load by drooping the frequency of
each generator with the real power P delivered by the generator. This allows each
generator to take up changes in total load in a manner determined by its frequency droop
characteristic and essentially utilizes the system frequency as a communication link
between the generator control systems [102]. Similarly, a droop in the voltage magnitude
V with reactive power Q is used to ensure reactive power sharing.
In the droop technique, the P-f droop and Q-V droop characteristic of each
inverter i in the paralleled system can be described by:
f i = f 0 − mi ( P0i − Pi ) (1.8)
Vi = V0 − ni (Q0i − Qi ) (1.9)
where fi and Vi denote the frequency and voltage of the inverter i , f0 and V0 represent the
nominal frequency and voltage magnitude of the system, and mi and ni are the droop
coefficients. Figure 1.8 shows a block diagram of the frequency and amplitude droop
technique and Fig. 1.9 shows the droop characteristics.
17
P0i f0i
Pi
- ∆f i +
+ mi + fi
mi < 0
Q0i V0i
- ∆V +
Qi
+ ni
+ Vi
ni < 0
Figure 1.8 Frequency and Amplitude Droop Technique
The proportion of load shared by each inverter can be adjusted based on its
apparent power rating by choosing the droop coefficient as follows:
m1 ⋅ S1 = m2 ⋅ S2 = L = mn ⋅ Sn (1.10)
n1 ⋅ S1 = n2 ⋅ S2 = L = nn ⋅ Sn (1.11)
In Figure 1.9, two inverters can be seen to share the real and reactive loads proportionally
based on the chosen droop coefficients.
18
f0 V0
∆f ∆V
f V
m2 n2
m1 n1
P1 P2 Q1 Q2
Figure 1.9 Droop Characteristics
The advantage of the droop method is that it does not require communication
signals amongst units in parallel, thereby increasing the reliability of the system.
However, because of the droop characteristics, the frequency and amplitude of the system
voltage will drop to such a value that all unit will be operating in a new lower frequency
and voltage different than the nominal values. Also as in the average power method, the
method only works well for linear loads, but it will not help to share the harmonics
components caused by non-linear loads. Another drawback of this method is the lack of
robustness toward voltage measurement error. Errors in the voltage/currents measurement
feedback signal used for the control can significantly affect the power sharing. This is
due to the lack of closed loop control of the power sharing method.
19
1.2.2 4 Signal Injection Method for Reactive and Harmonic Current Sharing [113], [114]
The signal injection method proposed in [113] and [114] provides a way to share
the reactive and harmonic current of paralleled inverters. In this method two signals at
frequencies different than the fundamental are injected to the fundamental reference
voltage. One injected signal is used to control the reactive power sharing and the other is
used for harmonic powers sharing. This is done in addition to the fundamental droop for
the fundamental real power sharing.
Using this method, the reference voltage consists of the following:
v ref = 2 (V cos ωt + Vh1 cos ω q t + Vh 2 cos ω d t )
where ( V , ω ) are the fundamental voltage and frequency, ( Vh1 , ω q ) are the voltage and
frequency of signal injected to share the reactive power Q, and ( Vh 2 , ω d ) are the voltage
and frequency of signal injected to share the harmonic distortion power D. Vh1 and
Vh 2 are fixed, while the ω q and ω d are varied for reactive and harmonic power sharing.
To force reactive power sharing, the frequency of the ( Vh1 , ω q ) signal is drooped
by the local output vars Q i.e:
ω q = ω q 0 − BQ (1.10)
Also, the small real power at frequency ω q due to the injected signal ( p q ) is measured
and used to droop the fundamental voltage V as in:
V = V0 − Dv p q (1.11)
Similarly, to force the distortion power sharing, the frequency of the second injected
signal is drooped by the local distortion signal D.
20
ωd = ωd 0 − C ⋅ D (1.12)
where D is calculated using the apparent power S, the real power P, and the reactive
power Q from the following:
D = S 2 − P2 − Q2 (1.13)
In the case of the distortion power, the small real power at frequency ω d due to the
injected signal ( pd ) is measured and used to droop the bandwidth of the control signal as
in:
BW = BW0 − Dbw pd (1.14)

Figure 1.10 shows a diagram of the overall signal injection method. The
attractiveness of the signal injection method relies on the fact that it allows for sharing of
the harmonic distortion power in addition to real and reactive power sharing. Also it does
not require control connection to achieve the power sharing. One of the drawbacks of this
method is that the injected signals decrease the waveform fidelity of the output voltages.
This is undesirable in a very high performance UPS system where the output voltage
THD is typically specified to be less than 5%.
21
REAL POWER SHARING ω0
P +
∆ω ωq0
m - ω HARMOMIC POWER SHARING
REACTIVE POWER SHARING ω q0 ∆ω q

+
D
C - ωq
Q ∆ω q
+ BW0
B - ωq
V0
+
pd
DBW ∆BW
- BW
+
pd
DV ∆V
- V
v ref = 2 (V cos ωt + Vh1 cos ω q t + Vh 2 cos ω d t )
Figure 1.10 Power Sharing using Signal Injection Method
22
1.3 Research Outline
This PhD research addresses the development of control techniques for single
PWM inverter and parallel PWM inverters.
1.3.1 Development of Voltage and Current Control for Single Inverter System
The voltage control technique proposed in this research uses the perfect control of
robust servomechanism problem (Perfect RSP) theory developed in [87] to ensure perfect
tracking of the output voltages under unknown load by providing means for eliminating
errors at specified harmonic and at the same time ensuring good transient response. The
perfect RSP theory combines this internal model principle with optimal state feedback to
guarantee stability of the closed loop system and providing arbitrary good transient
response.
It is to be noted that, although the perfect RSP used in this research only
eliminates voltage harmonic at some specified frequencies, the perfect RSP control is still
a very suitable control for three-phase PWM inverters. It is to be emphasized that in a
three-phase system, most of the voltage harmonics, like the even harmonics or higher
order harmonics, are either non-existence or negligible in values. Therefore, not too
many significant harmonics are left for the control to handle. Moreover, the perfect RSP
by itself already provides a good transient response.
In this research, the perfect RSP control of the voltages harmonics will be
combined with a fast current controller using a discrete time sliding mode controller [88]
for limiting the inverter currents under overload condition. This is one of the important
features necessary for a UPS, which is not addressed in the repetitive control work of
23
[76-85]. The discrete sliding mode controller has been chosen because of the fast and no-
overshoot response that it provides. The current controller acts as an inner loop to the
perfect RSP control of the output voltages in the outer loop. In this case, the perfect RSP
voltage control has been designed by accounting for the extra dynamic introduced by the
discrete time sliding mode controller. This way, the stability of the overall control system
is still guaranteed.
The Perfect RSP controller guarantees exact asymptotic tracking of the
fundamental frequency reference and error regulation of the load disturbance at each of
the harmonic frequency included in the compensators. The RSP guarantees this property
independent of any perturbations in the plant as long as they do not destabilize system
[87]. Perturbations in a UPS system may come as results of load disturbances, noise and
uncertainties in the manufacturing of the components used. It is important therefore to
analyze the stability property of the resulting controller under possible disturbances that
might destabilize the system in order to ensure proper operation of the UPS over its
intended operating range. In this PhD research, a Structured Singular Value µ -
framework has been used to study the stability robustness of the control system under
structured perturbations caused by components parameters variations and load variations.
24
Finally, the effectiveness of the proposed controller has been verified thru
simulations and experimental studies. A 5 kVA experimental test bed has been designed
and built at the Mechatronics Laboratory of The Ohio State University for this purpose.
The results show that the proposed controller provides an output voltage with excellent
regulation and THD less than 2.5% under both linear and non-linear load while still
maintaining good transient response under sudden load changes.
1.3.2 Development of Load Sharing Technique for Paralleled Inverters System
The load sharing technique developed in this research attempts to address and
improve the issues that exist in the previous research works as described earlier. To
ensure good load-sharing, the proposed scheme combines two control methods: droop
control method and average power control method. In this method, the sharing of real and
reactive powers between each UPS is implemented by two independent control variables:
power angle and inverter output voltage amplitude. Especially, the average power method
is used in order to significantly reduce the sensitivity of the load sharing to voltage/
current measurement error and wiring impedances mismatches. This scheme guarantees
good load-sharing of the fundamental components of the load currents. The droop control
method on the other hand provides a way for the paralleled inverter to still maintain load
sharing in the event of loss of communications between units.
25
To ensure sharing of harmonic contents of the load currents, a harmonic droop
sharing technique is proposed in this research. The technique is based on the voltages and
currents control for single PWM inverter developed in this research. The proposed
harmonic droop technique has the advantage that it only affects the harmonic
compensator gains and does not degrade the fundamental voltage regulation.
Simulations and experimental results have been performed to show the
effectiveness of the proposed scheme. Specifically the following have been investigated
in this research thru simulations and experimental studies:
1. Sensitivity of the load sharing control to the following: component mismatches,
measurement error, or unbalanced load or wire impedances.
2. Sharing of harmonic components of the currents under non-linear loads
3. Effect of the loss of inter-communication between units
4. Load sharing control for units with different kVA ratings.
A second 5kVA test bed unit has been built at the laboratory for the purpose of testing the
effectiveness of the proposed parallel inverter control scheme.
1.4 Chapters Organizations
Chapter 1, this chapter, is the introduction part of this dissertation.
Chapter 2 discusses the development of the single inverter control system. It
begins with the development of a state space model of the single PWM inverter system,
followed by brief summaries of the perfect RSP control theory and Discrete Sliding
Mode control theory. It then proceeds with the development of the current controller and
26
voltage controller using the two control methods. Next, some practical considerations are
given in relation to the tuning and implementation of the controllers. The chapter ends
with explanations on how to use Matlab to compute and design the controller gains.
Chapter 3 provides analysis and simulation studies of the controller designed in
Chapter 2. A summary of robust stability test using the Structured Singular Value µ -
framework is first presented, followed by the development of a closed-loop uncertain
system necessary for the robust stability analysis. The chapter then provides robust
stability analysis and transient performance evaluations of the system for different
controllers resulting from different parameters choices in the cost function of the perfect
RSP control. Finally, this chapter presents simulation results of the complete three-phase
PWM inverter system.
In Chapter 4, the experimental work involved for the single inverter system is
discussed. This chapter presents a description of the 5 kVA test bed used for the purpose
of verifying the effectiveness of the single inverter control. The experimental results
obtained from this test bed are then presented and discussed.
Chapter 5 and Chapter 6 discuss the results of this PhD research for control of the
parallel inverters system. Chapter 5 explains the parallel control strategy, while Chapter 6
discusses simulations and experimental results performed to verify its effectiveness.
Chapter 5 begins with the proposed load sharing control, followed by discussion of
stability analysis of the combined average power method and droop method. The chapter
then discusses the reference angle generation and provides explanation of the harmonic
sharing strategy. In Chapter 6, a detailed description of the simulation system
27
implementation for the parallel inverter system is first described. The detailed
descriptions of the simulation system is necessary here in order to give the reader better
understanding of the practical implementation of the parallel control strategy and of the
extensive simulation results that follows. Chapter 6 ends with a description of the
experimental test bed used to verify the effectiveness of the parallel inverter control, and
presents the experimental results obtained.
This dissertation ends with Chapter 7 which gives conclusions to the overall
research work and suggestions for possible future work.
28
CHAPTER 2
CONTROL OF SINGLE INVERTER SYSTEM
2.1 Theoretical Background
The voltage control technique proposed here uses the perfect control of robust
servomechanism problem (Perfect RSP) theory developed in [87] to ensure perfect
tracking of the output voltages under unknown load by providing means for eliminating
errors at specified harmonic and at the same time ensuring good transient response. The
theory is based on the internal model principle proposed by [86] which states that
asymptotic tracking of controlled variables toward the corresponding references in the
presence of disturbances (zero steady state tracking error) can be achieved if the models
that generate these references and disturbances are included in the stable closed loop
systems. In other words, if we include the frequency modes of the references and the
disturbances to be eliminated in the control loop, then the steady state error will not
contain these frequency modes. Applying the internal model principle into the output
voltages control in a three-phase PWM inverter means that the fundamental frequency
mode (50 Hz or 60 Hz) has to be included in the controller since the references vary at
this frequency. Elimination of the voltages errors due to the load currents at other
29
harmonics frequency can then be achieved by including the frequency modes of these
harmonics into the controller. The perfect RSP theory combines this internal model
principle with optimal state feedback to guarantee stability of the closed loop system and
providing arbitrary good transient response.
2.1.1 State space model of the plant
For development of the control algorithm, a state space model of the system
shown in Fig. 2.1 needs to be developed. Each phase of the delta-wye transformer has
been modeled as an ideal transformer with leakage inductance Ltrans and series
resistance Rtrans on the secondary winding as shown in Fig. 2.2 The secondary
transformer currents are denoted as Isnd a , Isnd b , and Isnd c . The transformer’s turn
ratio tr is defined as tr = (V 2 / V 1) where V1 and V2 denote the rated line-to-neutral
primary and secondary voltages respectively, Note that the transformer input-output
phase relationship shown in Fig. 2.1 and Fig. 2.2 corresponds to a particular type of
Delta-Wye transformer used in the experimental test bed in this research.
30
⎡Vinvab⎤
⎡Vloadan ⎤
⎡Vpwmab ⎤ ⎢Vload ⎥
⎢ bc ⎥ ⎢ bc ⎥ ⎢ bn ⎥
⎢⎣Vpwmca ⎥⎦ ⎢⎣Vinvca ⎥⎦ Delta-Wye Transformer ⎢⎣Vloadcn ⎥⎦
Linv
a
Iinva
A
Iloada L
Cload
Cinv Cinv
O
Vdc Iinvb A
c
B
Iloadb
D
b
Iinvc C
z
Iloadc
gating signals DSP system voltages and currents

measurement
Figure 2.1 IGBT PWM Inverter Systems for UPS
DELTA-WYE TRANSFORMER
Ltrans Rtrans
u
x
+ tr
tr − Vinv ab Isnd a
− ⋅ Isnd a −
tr
⋅ Isnd c 3
3 Ltrans Rtrans
v 3 -
y
tr n
− Vinvca
3 -
tr - Isnd b
− ⋅ Isnd b tr +
3 + − Vinvbc Ltrans Rtrans
w 3 z
Isnd c
Figure 2.2 Delta-Wye Transformer model
31
Using the transformer model in Fig. 2.2, the dynamic equations of the output filter
circuit in Fig. 2.1 can be written as in equations (2.1.a)-(2.1.d):

r
dVinvabc 1 r 1 r
= I invabc − Tri ⋅ I snd abc (2.1.a)
dt 3Cinv 3Cinv
r
dI invabc R r 1 r 1 r
= − inv I invabc − Vinvabc + Vpwmabc (2.1.b)
dt Linv Linv Linv
r
dVload abc 1 r 1 r
= I snd abc − I load abc (2.1.c)
dt C load C load
r
dI snd abc R r 1 r 1 r
= − trans I snd + Trv ⋅Vinv abc − Vload abc (2.1.d)
dt Ltran Ltran Ltran
where the voltages and currents vectors are defined as in (2.2).

r
Vpwm abc = [Vpwmab
′ Vpwmbc ′ ]T = 1
′ Vpwmca [Vpwm ab Vpwm bc Vpwm ca ]
T
3
r
Vinv abc = [Vinv ab
′ Vinv bc ′ ]T = 1
′ Vinv ca [Vinv ab Vinv bc Vinv ca ]
T
3
r
Vload abc = [Vload a Vload b Vload c ] ,
T
r
I load abc = [Iload a Iload c ]
T
Iload b
r
I snd abc = [Isnd a Isnd c ] ,
T
Isnd b
r
I invabc = [Iinvab Iinvca ]
T
Iinvbc
(2.2)
= 1 ⋅ [Iinv a − Iinvb Iinvb − Iinvc Iinvc − Iinv a ]
T
Note that in the dynamic equations of (2.1), the average values of PWM signals
commands [Vpwm ab Vpwmbc Vpwm ca ] have been used to model the IGBT PWM
T
32
switching voltages. Matrices Tri and Trv in equation (2.1.a) and (2.1.d) denote the currents
and voltages transformations of the delta-wye transformer. Based on Fig. 2.2 these
matrices are given by (2.3):
⎡− 2 1 1⎤ ⎡− 1 0 0⎤
Tri = ⋅ 1 − 2 1 ⎥ ,
tr ⎢
Trv = tr ⋅ ⎢ 0 − 1 0 ⎥ (2.3)
3 ⎢ ⎥ ⎢ ⎥
⎢⎣ 1 1 − 2⎥⎦ ⎢⎣ 0 0 − 1⎥⎦
For convenience in the control analysis and implementation, it is advantageous to
rewrite the dynamic equations of (2.1) in some form of per-unit (PU) system. Define the
following per-unit voltages and currents:

r r r r r r
v pwm abc = Vpwm abc V 1 , v inv abc = Vinv abc V 1 , i inv abc = I inv abc I 1 ,
r r r r
v load abc = Vload abc V 2 , i load abc = I load abc I 1 (2.4)
where V1 and V2 are as defined earlier, and I1 and I2 denote the rated primary and
secondary currents, respectively. Also define the following per-unit impedances as
follows:
xl inv ≡ ω f Linv Z 1 , xrinv ≡ Rinv Z 1 , xcinv ≡ 1 (ω f 3C inv ) Z 1 ,
xl tran ≡ ω f Ltran Z 1 , xrtran ≡ Rtran Z 1 , xcload ≡ 1 (ω f C load ) Z 1 (2.5)
where the base impedances Z1 and Z2 are defined as:
Z1 ≡ V 1 I1 Z2 ≡V 2 I2 (2.6)
Using the quantities defined above the dynamic equations (2.1) can be rewritten
as in (2.7):
r r r
dv invabc
dt
(
= ω f ⋅ xcinv ⋅ i invabc − tri ⋅ i snd abc ) (2.7.a)
33
r
di invabc
=
1
(− xrinv ⋅ i invabc − vrinvabc + vrpwmabc ) (2.7.b)
dt xlinv ω f
r
r r
dVload abc
dt
(
= ω f ⋅ xcload i snd abc − i load abc ) (2.7.c)
r
r
di snd abc
dt
=
1
xl tran ω f
( r r
− xrtran ⋅ i snd abc + trv ⋅ v invabc − v load abc ) (2.7.d)
where matrices tri and trv are now independent of the transformer turn ratio, and are
given by (2.8):
⎡− 2 1 1⎤ ⎡− 1 0 0⎤
1⎢
tri = 1 −2 1 ⎥, trv = 0 − 1 0 ⎥
⎢ (2.8)
3 ⎢ ⎥ ⎢ ⎥
⎢⎣ 1 1 − 2⎥⎦ ⎢⎣ 0 0 − 1⎥⎦
To obtain a state space model of the system, the dynamic equations in (2.7) are
transformed to the DQ0 stationary reference frame using the transformation:

v r
f qd 0 = K S ⋅ f abc , (2.9)
with
⎡1 − 0.5 − 0.5 ⎤
2⎢
KS = 0 − 3 2 3 2⎥ ,
3⎢ ⎥
⎢⎣0.5 0.5 0.5 ⎥⎦
f qd 0 = [ f q , f d , f 0 ] , f abc = [ f a , f b , f c ]
T T
r r
where f abc denotes the abc voltages and currents defined in (2.4), and f qd 0 the
corresponding to the DQ0 stationary reference frame variables. The circuit dynamics can
then be written as in (2.10):
34
r
r r
dv inv qd
dt
(
= ω f ⋅ xcinv ⋅ i inv qd − triqd ⋅ i snd qd ) (2.10.a)
r
di inv qd
=
1
(− xr ⋅ i inv qd − v inv qd + v pwmqd )
r r
(2.10.b)
xlinv ω f
inv
dt
r
r r
dv load qd
dt
(
= ω f ⋅ xcload i snd qd − i load qd ) (2.10.c)
r
r
di snd qd
dt
=
1
xl tran ω f
(− xr tran
r r
⋅ i snd qd + trv qd ⋅ v inv qd − v load qd ) (2.10.d)
dvload 0
= ω f ⋅ xcload (isnd 0 − iload 0 ) (2.10.e)
dt
disnd 0 1
= (− xrtran ⋅ isnd 0 − vload 0 ) (2.10.f)
dt xl tran ω f
r
where f qd = [ f q f d ], and matrices triqd and trvqd are defined as:
[
triqd = K s ⋅ Tri ⋅ K S
−1
]row 1, 2
⎡− 1 0 ⎤
=⎢ ⎥ (2.11.a)
⎣ 0 − 1⎦
col 1, 2
[
trv qd = K s ⋅ Trv ⋅ K S
−1
] row1, 2
⎡− 1 0 ⎤
=⎢ ⎥ (2.11.b)
⎣ 0 − 1⎦
col 1, 2
Notice that, due to the three-wire system of the inverter and filter, the zero
components of the inverter voltages ( vinv0 ), the inverter currents ( iinv0 ) and the input
PWM voltages ( vpwm0 ) are trivial and they do not appear in (2.10). Furthermore, define
changes of variables as follows:

r r
′ = triqd ⋅ i snd qd
i snd qd
35
r r
′ = triqd ⋅ i load qd
i load qd
r r
′ = trvqd −1 ⋅ v load qd
v load qd (2.12)
Using (2.12), the state space equations (2.10) can be rewritten in the form (2.13):
r
r r
dv inv qd
dt
(
= ω f ⋅ xcinv ⋅ i inv qd − ⋅i snd qd
′ ) (2.13.a)
r
di inv qd
=
1
r r
(2.13.b)
xlinv ω f
inv
dt
r
′ r r
dv load qd
dt
(
= ω f ⋅ xcload i snd qd
′ − i load qd
′ ) (2.13.c)
r
′ r
di snd qd
dt
=
1
xl tran ω f
(− xr tran ⋅ i snd qd
r r
′ + v inv qd − v load qd
′ ) (2.13.d)
dvload 0
= ω f ⋅ xcload (isnd 0 − iload 0 ) (2.13.e)
dt
disnd 0 1
= (− xrtran ⋅ isnd 0 − vload 0 ) (2.13.f)
dt xl tran ω f
Define the following per-unit capacitances, inductances, and resistances:
cinv ≡ 1 cload ≡ 1
ω f xcinv , ω f xcload ,
ωf ωf
linv ≡ , ltrans ≡ , (2.14)
xl inv xltrans
rinv ≡ xrinv , rtrans ≡ xrtrans
Substituting these definitions to the dynamic equations in (2.13), equivalent circuits can
be drawn in the DQ0 stationary reference frame as shown in Fig. 2.3. From Fig. 2.3, it
can be seen that the 0-axis equivalent circuit of the load-side of the transformer is
36
completely decoupled from the qd-axis equivalent circuits. This shows that the zero
components of the load voltages and the secondary transformer currents ( Vload 0 and Isnd 0 )
v
are not controllable by the input PWM voltages Vpwmqd . The 0-component of the load
currents will be non-zero under unbalanced load condition or under non-linear load in the
form of triplent harmonics. This 0-component of the load currents will create 0-
component of the load voltages, which is undesirable. Since the 0-component of the load
voltages is uncontrollable, no action can be done by the control to compensate for it.
However, as is apparent from Fig. 2.3, the small capacitor at the output along with the
leakage inductance of the transformer act as an LC filter which can be tuned to provide
attenuation to the effect of the 0-component of the load current to the load voltages’.
From Fig. 2.3, the amount of this attenuation at steady state can be calculated from:
jω ⋅ Ltrans + Rtrans
Vload 0 ( jω ) = ⋅ Iload 0 ( jω ) (2.14)
1 − ω Ltrans C grass + jω ⋅ R trans C grass
2
where ω = 2πf and f is a harmonic frequency of interest.
37
Iinvq Isndq′
linv rinv ltrans rtrans Iloadq

+
+ +
Vpwmq Vinv q cinv cload Vloadq′
- - -
Iinvd Isndd′
linv rinv ltrans rtrans Iloadd

+
+ +
Vpwmd Vinvd cinv cload Vloadd′
- - -
Isnd0
ltrans rtrans
+
cload Vload0 Iload0
Figure 2.3 Equivalent circuits in the DQ0 stationary reference frame
38
2.1.2 Perfect Control of Robust Servomechanism Problem
Finding a solution to a Robust Servomechanism Problem (RSP) for a system
involves finding a controller for the system such that: given a modeled class of unstable
tracking/disturbance signals, exact asymptotic tracking/regulation occurs for all plant
perturbations which do not produce instability. A perfect controller for the RSP solves the
RSP and also provides arbitrarily good transient error, with no unbounded peaking in the
error response of the system. Below some of the main results of the perfect RSP
discussed in [87] and [121] are summarized.
Consider the plant to be regulated described by the following equations:
x& = Ax + Bu + Ed
y = Cx + Du + Fd
(2.15)
ym = Cm x + Dmu + Fm d
e = yref − y
where x ∈ R n , u ∈ R m are the inputs, y ∈ R r are the outputs to be regulated, y m ∈ R rm are
the measurable outputs, d ∈ R δ are the disturbances, y ref ∈ R r are the reference input
signals, and e ∈ R r are the error in the system. Assume the disturbance d can be generated
from the following systems:
η&1 = Ψ1η1 , d = C1η1 , η1 ∈ R n1 (2.16)
and the reference input signals y ref from the following:
η&2 = Ψ2η 2 y ref = C 2η 2 η 2 ∈ R n 2 (2.17)
with eig ( Ψ1 ) ⊂ C + and eig ( Ψ2 ) ⊂ C + , where eig (⋅) denotes the eigenvalues and C +
denotes the closed right complex half plane. This type of signals includes constant,
39
polynomial, sinusoidal, polynomial-sinusoidal, etc occurring in most applications [121].
Let Λ := {λ1 , λ 2 ,K, λ p } be the zeros of the least common multiple of minimal polynomial
of Ψ1 and Ψ2 (multiplicities repeated), then a linear controller that solves the RSP for
(2.15), consists of the following structure:
u = ξ + K1η (2.18)
where η ∈ R r⋅ p is the outputs of a servo-compensator and ξ ∈ R m is the output of a
stabilizing-compensator S. The servo compensator has the form:
η& = Acη + Bc e (2.19)
with
Ac = block diag (Ω, Ω,K, Ω )
r
Bc = block diag (γ , γ ,K , γ )
and
⎡0⎤
⎡ 0 1 0 L 0 ⎤ ⎢0⎥
⎢ 0 0 1 L 0 ⎥ ⎢ ⎥
Ω=⎢ ⎥ ,γ = ⎢M⎥
⎢ M M M M M ⎥ ⎢ ⎥
⎢ ⎥ ⎢0⎥
⎣− σ 1 −σ2 −σ3 L −σ p⎦
⎢⎣1⎥⎦
where the coefficients σ i , i = 1,2,K, p are given by the coefficients of the polynomial
∏ (λ − λ ) ; i.e.,
i =1
i
p
λ p + σ p λ p −1 + L + σ 2 λ + σ 1 := ∏ (λ − λi ) (2.20)
i =1
40
The servo compensator gain K1 in (2.18) and the stabilizing-compensator S
should be found to stabilize and provide intended behavior to the following stabilizable
and detectable system:
⎡ x& ⎤ ⎡ A 0 ⎤⎡ x⎤ ⎡ B ⎤
⎢η& ⎥ = ⎢− B C +
Ac ⎥⎦ ⎢⎣η ⎥⎦ ⎢⎣− Bc D ⎥⎦
u
⎣ ⎦ ⎣ c
⎡ y m ⎤ ⎡C m 0 ⎤ ⎡ x ⎤ ⎡ Dm ⎤
⎢η ⎥=⎢ 0 +
I ⎥⎦ ⎢⎣η ⎥⎦ ⎢⎣ 0 ⎥⎦
u
⎣ ⎦ ⎣ (2.21)
Note that, given a modeled class of references/disturbances, the servo-
compensator is unique within the class of coordinate transformations and nonsingular
input transformations [121]. The stabilizing compensators S are, however, not unique;
there are various classes of stabilizing compensators that can be used in a robust
servomechanism controller. One of them, adopted in this PhD research, is the
complementary controller where the stabilizing compensator is given by:
S : ξ = K0 x (2.22)
where x can either be the measured states of the system, or the estimates found using an
observer (if not all states are measurable). In this case, the control u is given by state
feedback found to stabilize the augmented system of the plant and the servo-
compensator:
~ ~
x& = A ⋅ ~
~ x + B ⋅u (2.23)
~ ⎡ A 0⎤ ~ ⎡ B ⎤ ~ ⎡ x⎤
A=⎢ B=⎢ x =⎢ ⎥,
⎣ − Bc C Ac ⎥⎦ ⎥
⎣ − Bc D ⎦ ⎣η ⎦
u = K 0 x + K 1η = [K 0 K 1 ]~
x := K ⋅ ~
x
41
A perfect controller for the robust servomechanism problem can be stabilized
using Cheap Control method, where the gains K = [K 0 K1 ] are found by minimizing the
following performance index [87]:
∞
J ε = ∫ (z ' z + ε ⋅ u ' u ) dτ , z = C ⋅ ~
~
x (2.24)
0
where ε > 0 is an arbitrarily small scalar. The optimal control gain K = K opt , which
~
minimizes this performance index, is given by: K opt = − 1 ε B ' Popt , where Popt is the unique
positive semi-definite solution to the algebraic Riccati equation [87]:
~ ~ ~ ~ 1 ~~
A' Popt + Popt A + C ' C − Popt B B ' Popt = 0 (2.25)
ε
42
2.1.3 Discrete-Time Sliding Mode Control
Discrete time sliding mode controller is an approach in the sliding mode control
theory, which is suitable for digital implementation since it does not exhibit the chattering
phenomena due to direct digital implementation of continuous time sliding mode control
[88].
Consider a continuous linear time invariant system
x& (t ) = Ax (t ) + Bu (t ) + Ed (t ) (2.26)
y (t ) = Cx(t )
e(t ) = y (t ) − y ref (t )
with state vector x (t ) ∈ R n , control u(t ) ∈ R m , output to be regulated y (t ) , reference
input y ref (t ) , and disturbance d (t ) . System (2.26) can be transformed to a discrete time
system with sampling time Ts to yield:
x ( k + 1) = A* x ( k ) + B * u( k ) + E * d (k ) (2.27)
y ( k ) = Cx(k )
e(k ) = y ( k ) − y ref (k )
where :
TS A ⋅(TS −τ )
A* = exp( A ⋅ TS ) B* = ∫ e B dτ
0
TS A ⋅(TS −τ )
E* = ∫ e E dτ
0
It is desired to control the output y ( k ) to follow the reference y ref ( k ) . For this
purpose we can choose a sliding mode manifold in the form of: s( k ) = Cx(k ) − y ref ( k )
43
such that when discrete-time sliding mode exists we have y ( k ) → y ref ( k ) .Discrete-time
sliding mode exists if the control input u (k ) is designed as the solution of:
s (k + 1) = CA* x (k ) + CB * u(k ) − y ref ( k + 1) = 0 (2.28)
The control law that satisfies (2.28) is called ‘equivalent control’ and is given by:
u eq (k ) = − (CB * ) (CA* x (k ) − y ref ( k + 1) )

−1
(2.29)
If the control is limited to a value u0 i.e. u (k ) ≤ u0 then the following modified control
law can be applied:

r r
⎧ u eq (k ) for u eq (k ) ≤ u 0
⎪ r
u (k ) = ⎨ u eq (k ) r (2.30)
⎪u 0 ur (k ) for u eq (k ) > u 0
⎩ eq
With control law (2.30), discrete-time sliding mode exists after a finite number of steps.
44
2.2 Control System Development
To achieve fast current limiting capability for the inverter, the control strategy
uses a two-loop control structure: an inner inverter currents loop and an outer load
v
voltages loop as shown in Fig. 2.4. The outer loop regulates the load voltages ( Vload qd ) to
v
follow 50/60 Hz balanced three-phase voltages references ( Vref qd ) and generates the
r
inverter currents commands ( I cmd qd ), which are limited. The inner loop in turn generates
the PWM voltage commands to regulate the inverter currents to follow the inverter
current command. A standard voltage space vector algorithm is then used to realize these
PWM command voltages. Notice that the 0-components of the load voltages are not
regulated by the control, since it is uncontrollable.
r
r *
r Vpwm qd (k )
I cmd qd I cmd qd
r r r
Vref qd (k ) eVqd eIqd Line-to-Line
Robust ServoMechanism + Discrete Sliding Mode
Voltage
Limiter Space
+ Controller Controller
Vector
- - PWM
r r
Vload qd (k ) I invqd (k ) PWM timing
states states
Figure 2.4 Overall control system
Fig. 2.5 shows the timing diagram of the PWM gating signals generation in
relation with the A/D sampling time of the DSP. It can be seen that there is a one-half
PWM period delay between the time the signals are sampled by the A/D and the time the
PWM control action is applied.
45
A/D sampling A/D sam pling
for time k for tim e k+1
D SP tim er for PW M
generation
new values of PW M timing new values of PW M timing
for tim e k take affect for time k+1 take affect
control being control being

computed computed
for time k for tim e k+1
0.5 T pwm 0.5 Tpwm
T pwm T pwm
T pwm=PW M period
Figure 2.5 Control timing diagram
The next two subsections summarizes the development of the two control loops,
the inner current loop using the discrete sliding mode controller and the voltage control
loop using the robust servomechanism principles.
2.2.1 Discrete-Time Sliding Mode Current Controller
For designing the discrete time sliding mode current controller, consider the
inverter and filter subsystem with no transformer and load dynamics:

r
r r
dv inv qd
dt
(
= ω f ⋅ xcinv ⋅ i inv qd − triqd ⋅ i snd qd ) (2.31.a)
r
di inv qd
=
1
r r
(2.31.b)
xlinv ω f
inv
dt
r
Assuming the secondary transformer currents i snd qd as disturbances, this
subsystem can be written in state space form as:

r r r r
x&1 = A1 x1 + B1u + E1d 1 (2.32)
46
r r r
r ⎡ 02 x2 ω f ⋅ xcinv ⋅ I 2 x 2 ⎤ r ⎡ 02 x 2 ⎤
A1 = ⎢ r r ⎥, B1 = ⎢ r ⎥,
⎢⎣ − (xl inv ω f ) ⋅ I 2 x 2 ⎢⎣(xlinv ω f ) ⋅ I 2 x 2 ⎥⎦
−1 −1
02 x 2 ⎥⎦
r ⎡− ω f ⋅ xcinv ⋅ triqd ⎤
E1 = ⎢ r ⎥,
⎣ 02 x 2 ⎦
r
r r
[
where the states are x1 = v inv qd , i inv qd ] r r
, the inputs u = v pwmqd and disturbances
r
d 1 = i snd qd .
The discrete form of (41) can be calculated as:

r *r *r
r
x1 (k + 1) = A1 x1 (k ) + B1 u (k ) + E1 d 1 (k )
*
where
TS
A1* = exp( A ⋅ TS ) B1* = ∫ e A1 ⋅TS B1 dτ
0
TS
E1* = ∫ e A1 ⋅TS E1 dτ
0
and TS is the A/D sampling time, which in this case is equal to the PWM period T pwm
To force the inverter currents to follow their commands, the sliding mode surface
r r r r r
is chosen as: s (k ) = C1 ⋅ x1 (k ) − i cmd (k ) where C1 ⋅ x1 (k ) = i inv qd (k ) , so that when
r r r
discrete sliding mode occurs, we have s (k ) = 0 or i inv (k ) = i cmd (k ) . The existence of
the discrete sliding mode can be guaranteed if the control is given by:
r r
⎧ u eq (k ) for u eq (k ) ≤ u0
⎪ r
u (k ) = ⎨ u eq (k ) r (2.33)
⎪u0 ur (k ) for u eq (k ) > u0
⎩ eq
r
where the equivalent control input ueq (k ) is calculated from:
47
r
r
(
ueq (k ) = C1 B1
*
) (ircmd
−1
qd
*r
)
− C1 A1 x1 (k ) − C1 E1 d1 (k )
*
(2.34)
and u0 denotes the maximum value of the PWM voltage command realizable by the space
vector algorithm.
Note that the secondary transformer currents are needed for the control, but these
currents are not measured in the system (see Fig.2.1). A linear Luenberger observer can
be easily designed to estimate these currents for control purposes. However, in most
practical cases we can approximate these currents with the load currents (i.e.
r r
I snd qd ≈ I load qd ) since the currents through the output capacitor filters are small. From
simulations and experiments, the effect of using this approximation is unnoticeable in the
control performance.
Due to the computation delay of the DSP (Fig. 2.5), the control action given by
(2.34) will result in undesirable overshoots during transients. This effect can be
r r
minimized, however, if the states x1 ( k ) and disturbances d 1 (k ) are replaced with their
first order one-half step ahead predicted values given by:

r r r
x1p ( k ) = 1.5 ⋅ x1 ( k ) − 0.5 ⋅ x1 (k − 1)
r r r
d 1p ( k ) = 1.5 ⋅ d 1 ( k ) − 0.5 ⋅ d 1 (k − 1) (2.35)
r
The equivalent control input ueq (k ) then becomes:
r
r
(
u eq (k ) = C1 B1
*
) (Ircmd
−1
qd
*r
− C1 A1 x1p (k ) − C1 E1 d 1p (k )
*
) (2.36)
48
2.2.2 Voltage Controller Design using Discrete Perfect RSP
The voltage control loop designed in this research is based on the discrete form of
the technique developed in Davison [87] discussed in the previous section. To design the
load voltages controller, let’s first consider the entire plant system with the-0 components
of the voltages and currents omitted as given in (2.37). As explained in the previous
section, these 0-components are completely decoupled and uncontrollable from the
inputs, and therefore are not useful to be included in the controller design. In the system
(2.37), an input delay of one-half the PWM period ( 0.5T pwm ) has been explicitly included
to account for the computation delay of the DSP.

r r
x& p (t ) = A p x p (t ) + B p u (t − 0.5T pwm ) ,
r r r
⎡ 02 x 2 ω f ⋅ xcinv ⋅ I 2 x 2 02 x2 − ω f ⋅ xcinv ⋅ triqd ⎤
⎢ r r r r ⎥
r
Ap = ⎢
− ( xl inv ω
r f
)−1
⋅ I 2x2 02 x 2
r
02 x2
r
02 x 2
r ⎥
⎢ 02 x 2 02 x 2 02 x2 ω f ⋅ xcload ⋅ I 2 x 2 ⎥
⎢ r r r ⎥
⎢⎣(xl trans ω f ) ⋅ trv qd − (xl tran ω f ) ⋅ I 2 x 2 − xrtran (xl tran ω f ) ⋅ I 2 x 2 ⎥⎦
−1 −1 −1
02 x 2
,
r
⎡ 02 x 2 ⎤
⎢ r ⎥
r (xl
B p = ⎢ inv
ωf )
r
−1
⋅ I 2x2 ⎥
, (2.37)
⎢ 02 x 2 ⎥
⎢ r ⎥
⎣ 02 x 2 ⎦
The states variables for the system (2.37) are chosen as

r r r r
r
[ ] v
x p = Vinv qd , I inv qd ,Vload qd , I snd qd , with the inputs as u = Vpwm qd . System (2.37) can
be transformed to a discrete-time system with sampling time Ts = T pwm to yield:
49
r r r r
x p (k + 1) = Φ ⋅ x p (k ) + Γ1 ⋅ u (k − 1) + Γ2 ⋅ u (k ) (2.38)
where
TS 0.5TS
∫e ∫e
Apτ Apτ
Φ=e , Γ1 = B p dτ , Γ2 = B p dτ
ApTS
0.5TS 0
Discrete time system (2.38) can be written in a standard discrete time state space
r r v
equations by adding the extra states: x a (k ) = u (k − 1) = Vpwm qd (k − 1) to yield:
r r
⎡ x p (k + 1)⎤ ⎡ Φ Γ1 ⎤ ⎡ x p (k )⎤ ⎡Γ2 ⎤ r
⎢r ⎥ = ⎢r r ⋅ ⎢r ⎥ + ⎢ r ⎥ ⋅ u (k )
0 2 x 2 ⎥⎦ ⎣ x a (k )⎦ ⎣ I 2 x 2 ⎦
(2.39)
⎣ x a (k + 1)⎦ ⎣0 2 x 2
so that the system can be written as:

r *r *r
x *p (k + 1) = Ap x *p (k ) + B p u (k ) (2.40)
where:
r
r* ⎡ x p (k )⎤ ⎡ Φ Γ ⎤ ⎡Γ ⎤
x p (k ) = ⎢ r ⎥ , Ap = ⎢ r
*
r 1 ⎥ , B *p = ⎢ r 2 ⎥
⎣ x a (k )⎦ ⎣0 2 x 2 02 x2 ⎦ ⎣I 2x2 ⎦
To design the voltage controller, we need to consider the true plant (2.40) and the
discrete time sliding mode current controller as the equivalent ‘plant’ as seen by the outer
voltage loop. Using equation (2.36) and (2.40) the augmented true plant and discrete
sliding mode current controller can be found as in (2.41).

r r r
x *p (k + 1) = Ad x *p (k ) + Bd u1 (k ) (2.41)
r r
with u1 (k ) = I cmd qd
*
( k ) , and
(
Ad = A*p − B *p C1 B1 ) (B C
* −1 *
1 11 + E1*C12 )
(
Bd = B *p C1 B1
* −1
)
50
r r r r r
⎡ I 2x2 02 x2 02 x2 02x2 02 x2 ⎤
C11 = ⎢ r r r r r ⎥
⎣0 2 x 2 I 2x2 02 x2 02x2 02 x2 ⎦
r
[
C12 = 0 2 x 2
r
02x2
r
02 x2
r
I 2x2
r
02 x2 ]
Note that the augmented system given in (2.41) was found assuming the approximation
r r
I snd qd ≈ I load qd has been used.
Now, assume ωi = 2πf i i = 1,2,K n are frequencies of the reference voltages and
harmonics to be eliminated. For a 60-Hz UPS system with desire to eliminate 5th and 7th
harmonics, for example, we use ω1 = 2π ⋅ 60 , ω 2 = 2π ⋅ 5 ⋅ 60 , and ω3 = 2π ⋅ 7 ⋅ 60 . We
can then choose the servo-compensator to be of the form (2.42):

r r
η& = Acη + Bc eVqd
r r r
eVqd = Vref qd − Vload qd (2.42)
where
r r r r r
η = [η1 ,η 2 ,Lη n ]T η i ∈ R 4 , i = 1,2,K n
Ac = block diag [Ac1 , Ac2 , L , Acn ]
Bc = [Bc1 , Bc2 , L , Bcn ]

T
with
r r
⎛ 02 x2 I 2x2 ⎞
Aci = ⎜⎜ r r ⎟ , i = 1,2, K n
− ω 0 2 x 2 ⎟⎠
2
⎝ i I 2x2
r r
(
Bci = 0 2 x 2 I 2x2 )
T
i = 1,2, K n
51
r r r
Note that each of the blocks η&i = Ac1η i + Bci eVqd represents a state space
implementation of the continuous transfer function: 1 s 2 + ωi ( 2

) for each of the qd-axis
voltages errors.
The servo compensator (2.42) can be transformed to a discrete time system to
yield:
r r r r r r
η (k + 1) = Ac*η ( k ) + Bc* eVqd ( k ) , eVqd ( k ) = Vref qd (k ) − Vload qd (k ) (2.43)
where:
Bc* = ∫ e A1⋅(TS −τ ) Bc dτ
TS
Ac* = exp( Ac ⋅ TS )
0
Now that we have determined the ‘plant’ and the servo compensator, the control
input for the perfect robust servomechanism controller is given by:

r r
u1 (k ) = I cmd qd
*
(k ) = K 0 x *p ( k ) + K1η ( k ) (2.44)
where the gains K = [K 0 K 1 ] are found by minimizing the discrete performance index:
∞
J ε = ∑ (z ( k ) ' z (k ) + ε ⋅ u( k ) ' u ( k ) ) ,
k =0
⎡ x *p ⎤
z=⎢ ⎥ (2.45)
⎣η ⎦
for the augmented ‘equivalent plant’ (2.41) and the servo compensator (2.43):
r r
⎡ x *p (k + 1)⎤ ⎡ Ad 0 ⎤ ⎡ x *p (k )⎤ ⎡ Bd ⎤
⎢ ⎥=⎢ + u (k )
Ac* ⎥⎦ ⎢⎣ η (k ) ⎥⎦ ⎢⎣ − Bc* D ⎥⎦ 1
(2.46)
⎣ η (k + 1) ⎦ ⎣− Bc C
*
where ε > 0 is an arbitrarily small scalar.
52
Current Limit and Control Saturation Handling
r *
The current command I cmd qd (k ) generated by the robust servomechanism
voltage controller above is limited in magnitude as in (2.47) to yield the current

r
command I cmd qd (k ) , which will be implemented by the inner loop current controller:
r r
⎧ I cmd qd *
(k ) *
if I cmd qd (k ) ≤ I max
r ⎪⎪ r
I cmd qd (k ) = ⎨ I cmd qd (k ) r
*
(2.47)
⎪ Ircmd * (k ) I max
*
if I cmd qd (k ) > I max
⎪⎩ qd
I max represents the maximum allowable magnitude of the inverter currents.
Equation (2.47) limits the magnitude of the current commands but maintains their vector
directions in the qd-space.

r
The states ηi of the servo-compensator can be seen as sine wave signal generators
that get excited by the harmonic contents of the error signals at frequency ωi . When the
control inputs of the robust servomechanism voltage controller saturate

r *
i.e., I cmd qd (k ) > I max the servo-compensator states will grow in magnitude due to the
break in the control loop. This problem is similar to the integrator windup problem that
occurs in an integral type controller. To prevent this, the servo-compensator in (2.43) can
be modified as follows:
r r r
η (k + 1) = Ac*η ( k ) + Bc*e1 ( k ) ,
r
r ⎧⎪erVqd ( k ) if I cmd qd
*
≤ I max
e1 ( k ) = ⎨ r (2.48)
⎪⎩ 0 if I cmd qd > I max
*
53
Using (2.48), during the current limit saturation, the servo compensator states will
continue to oscillate at the harmonic frequency with constant magnitude. The resulting
robust servomechanism controller structure is shown in Fig. 2.6.
r *
I cmd qd (k ) > I max
r r
Vref qd (k ) eVqd Discrete implementation of
states η1
r
1 r
+ ⋅ I 2×2
s 2 + ω12
r
Vload qd (k ) Current limit
r Equation (4.17) r
K1 *
I cmd qd I cmd qd
Discrete implementation of r
r states η2
1
⋅ I 2×2 Servo
s 2 + ω2 2 Compensator
Gains
r
. ⎡ Vinv qd (k ) ⎤
.. K2 ⎢ r ⎥
⎢ rI invqd (k ) ⎥
Stabilizing compensator ⎢ Vload (k ) ⎥
gains ⎢ r qd ⎥
Discrete implementation of r
states η n
⎢ I load qd (k ) ⎥
⎢ r ⎥
⎢⎣Vpwm qd (k −1)⎥⎦
1 r
⋅ I 2×2
s 2 + ωn 2
Figure 2.6 Output voltages controller using robust servomechanism controller
2.3. Practical considerations
2.3.1 Balanced realization of the harmonic servo compensators
In the preceding section, each discrete harmonic servo compensator is formed by
directly applying discretization (2.43) to the continuous state space implementation of the
transfer function 1 s 2 + ωi ( 2
) as given in (2.42). The discrete time system resulting from
this process (2.43) generally results in coefficients of the matrices Ac* and Bc* that have
wide dynamic range. This results in numerical difficulties in implementing the
54
compensator in a fixed point Digital Signal Processor such as the one used in this
research. To alleviate this problem, a balanced state space realization may first be
performed to (2.42) in order to provide matrices coefficients with comparable dynamic
range. Given the system (2.42), a balanced realization may be found by finding a
diagonal similarity transformation T and a scalar α such that:
⎡ TAc T −1 TBc / α ⎤
⎢ ⎥
⎣αI 2 x 2T
−1
0 ⎦
has approximately equal row and column norms [120]. The balanced realization of (2.42)
is then given by:

r r
η& = Abalcη + Bbalc eVqd (2.49)
with
Abal c = TAc T −1 , Bbalc = TBc / α −1
The continuous state space (2.49) can then be discretized to obtain the discrete
implementation of each harmonic servo compensator as shown in (2.42). Note the
balanced realization process outline above can easily accomplished in Matlab using the
command ssbal [120].
2.3.2 Tuning the optimum stabilizing gains for desired dynamic performance
The discrete performance index given in (2.45) applies equal weighting to the
plant states x *p and the servo compensator states η . To obtain a desired dynamic
performance and achieve robust stability, the cost function may be modified to provide
different weighting for the plant states, fundamental and harmonic servo compensator
states as follows:
55
∞
⎛ ⎞
J ε = ∑ ⎜ w p ⋅ x *p (k ) ' ⋅ x *p ( k ) + wS1 ⋅η1 ( k )′ ⋅η1 (k ) + wSH ∑η h ( k )′ ⋅η h ( k ) + ε ⋅ u(k ) ' u( k ) ⎟ (2.50)
k =0 ⎝ h ⎠
where constants w p , wS , and wSH are weighting constants scalars for the plant states,
fundamental, and harmonic servo compensator states respectively. The effect of choices
of values for w p , wS , and wSH in the dynamic performance of the system will be further
studied in the next chapter.
Matlab can be used to find the optimum state feedback gains K = [K 0 K 1 ] that
minimizes (2.50), by using the command dlqr.
2.3.3 Matlab Script for Control Gains Calculations
From the system equations (2.14) and the equivalent circuits shown in Fig. 2.14, it
can be seen that the d-axis and q-axis components of the system are completely
decoupled. Therefore, a controller can be designed for one of the axis, and the same
controller can be used for the other axis. In this section, step-by-step instructions are
given to calculate the control gains for the controller using Matlab. The complete lsiting
of the Matlab commands discussed in this section is also given in Appendix A.
56
1. Define the plant parameters, sampling frequency, and harmonic frequencies.
KVA=5e3;
inv_volt=240/sqrt(3); % L-N Inverter Cap Voltage
out_volt=120; % L-N output voltage
tr=out_volt/inv_volt; % transformer turn ratio
Cinv=55e-6; % Inverter filter capacitance
Linv=1.8e-3; % Inverter filter inductance
Rinv=0.1; % Inverter filter resistance
Cload=5e-6; % Output capacitor
fs=40e6/2/3704; % PWM switching frequency

Tsamp=1/fs; % Define control sampling time
%% Define fundamental frequency

ffun=60;
wfun=2*pi*ffun;
%% Define harmonics frequencies

w1=wfun; % 1st harmonic
w2=2*wfun; % 2nd harmonic
w3=3*wfun; % 3rd harmonic
w4=4*wfun; % 4th harmonic
2. Define power, voltages, and current bases, and compute the per-unit values of the filter
components.
KVAb=1/3*5e3; % Single phase KVA base

Vb_load=out_volt*sqrt(2); % Load voltage base
Ib_load=KVAb/out_volt*sqrt(2); % Load current base
Vb_inv=inv_volt*sqrt(2); % Inv Filter voltage base
Ib_inv=KVAb/inv_volt*sqrt(2); % Inv Filter current base
Zb_inv=Vb_inv/Ib_inv; % Inverter Filter impedance base
Zb_load=Vb_load/Ib_load; % Load impedance base
%% Compute perunit value of filter components

xCinv=1/(wfun*3*Cinv)/Zb_inv % Inverter capacitor filter
xLinv=(wfun*Linv)/Zb_inv % Inverter inductor filter
xRinv=Rinv/Zb_inv; % Inverter inductor losses
xLtrans=0.03 % 3% p.u transformer inductance

xRtrans=0.01 % 1% p.u transformer losses
xCload=1/(wfun*Cload)/Zb_load % Output capacitor
57
3. Design the dicrete sliding mode current controller. First define the reduced order plant
for the current controller:
A=[0 xCinv*wfun ;
-1/(xLinv/wfun) -xRinv/(xLinv/wfun)];
B=[0; 1/(xLinv/wfun)];
E=[-xCinv*wfun; 0];
F=[0; -1];
C=[0 1];
D=0;
Next, discretize the reduced plant using ZOH method, and compute the equivalent control
coefficient as given in equation 2.34.
sysc=ss(A,B,C,zeros(size(C,1),size(B,2)),'inputdelay',0);
sysd=c2d(sysc,Tsamp,'zoh');
[Acurrd,Bcurrd,Ccurrd,Dcurrd]=ssdata(sysd);
CBinv=inv(Ccurrd*Bcurrd);
CA=Ccurrd*Acurrd;
CD=Ccurrd*F;
sysc=ss(A,E,C,zeros(size(C,1),size(B,2)),'inputdelay',0);
[Acurrd1,Ecurrd,Ccurrd1,Dcurrd1]=ssdata(sysd);
CE=Ccurrd1*Ecurrd;
Define the following gain vector:
Ksm =[CBinv(1,1) -CBinv(1,1)*CA(1,1)*[1.5 -0.5] -CBinv(1,1)*CA(1,2)*[1.5 -0.5] -CBinv(1,1)*CE(1,1)*[1.5 -0.5] ];
The equivalent control with one-half step-ahead prediction 2.36 can be then implemented
by:
ueq = Ksm⋅ [Icmd(k ) Vinv(k ) Vinv(k − 1) Iinv(k ) Iinv(k − 1) Iload(k ) Iload(k − 1)]
T
Numerical values of the discrete sliding mode gains are:
>> see(Ksm_q)
Columns 1 through 7
0.8646 1.5000 -0.5000 -1.2099 0.4033 -0.0739 0.0246
58
5. Design the robust servomechanism controller. First define the true plant.
Ao=[ 0 xCinv*wfun 0 -xCinv*wfun;

-1/(xLinv/wfun) -xRinv/(xLinv/wfun) 0 0;
0 0 0 xCload*wfun;
1/(xLtrans/wfun) 0 -1/(xLtrans/wfun) -xRtrans/(xLtrans/wfun)];
Bo=[0;
1/(xLinv/wfun);
0;
0];
Co=[0 0 1 0];
Do=zeros(size(C,1),size(B,2));
Next, discretized the true plant using the ZOH method.
sysc=ss(Ao,Bo,Co,Do,'inputdelay',0.5*Tsamp);
[Aod,Bod,Cd,Dd]=ssdata(sysd);
Calculate equivalent plant with DSM current controller
C1=[eye(2) zeros(2,3)];
C2=[zeros(1,3) 1 0];
Ad=Aod-Bod*(CBinv*CA*C1+CBinv*CE*C2);
Bd=Bod*CBinv;
Cc_star=eye(size(Ch_star,1));
Compute the servo harmonic compensators. First define the analog implementation. The
following commands define the compensator with fundamental, 3rd, 5th, and 7th
harmonics included.
Ch1=[0 1;
-w1^2 0];
Ch2=[0 1;
-w2^2 0];
Ch3=[0 1;
-w3^2 0];
Ch4=[0 1;
-w4^2 0];
Ch5=[0 1;
-w5^2 0];
Ch7=[0 1;
-w7^2 0];
Ch_star=[[Ch1 zeros(2,2) zeros(2,2) zeros(2,2) ];
[zeros(2,2) Ch3 zeros(2,2) zeros(2,2) ];
[zeros(2,2) zeros(2,2) Ch5 zeros(2,2) ];
[zeros(2,2) zeros(2,2) zeros(2,2) Ch7 ]
];
59
Bh_star=[0; 1; 0; 1; 0; 1; 0; 1;];
Then compute the balanced realization of the compensators and obtain the discrete
implementation of controller.
csysc=ss(Ch_star,Bh_star,Cc_star,zeros(size(Ch_star,1),size(Bh_star,2)));
[csysbc,Tbal]=ssbal(csysc);
csysd=c2d(csysbc,Tsamp,'zoh');
[Acon_d,Bcon_d,Ccon_d,Dcon_d]=ssdata(csysd);
The numerical values of the servo compensators A matrices are given by:
>> Acon_d
Acon_d =
Columns 1 through 6
0.9976 0.0947 0 0 0 0
-0.0514 0.9976 0 0 0 0
0 0 0.9781 0.1883 0 0
0 0 -0.2296 0.9781 0 0
0 0 0 0 0.9397 0.3716
0 0 0 0 -0.3148 0.9397
0 0 0 0 0 0
0 0 0 0 0 0
Columns 7 through 8
0 0
0 0
0 0
0 0
0 0
0 0
0.8829 0.3644
-0.6050 0.8829
Form the augmented equivalent plant and the servo compensator
Ad_big=[Ad zeros(size(Ad,1),size(Acon_d,2));
-Bcon_d*Cd Acon_d];
Bd_big=[Bd ; -Bcon_d*Dd];
60
Next, we will compute the optimum gains that stabilize the system and minimize the cost
function given in (2.50). Matlab command [K,S,e] = dlqr(A,B,Q,R,N) computes the
optimal gain matrix K such that the state-feedback law u(k)=-Kx(k) minimizes the
quadratic cost function:
∞
J ε = ∑ (x (k ) ' ⋅ Q ⋅ x ( k ) + u ( k ) ' Ru ( k ) + 2 x ′(k ) Nu(k ) )
k =0
To use the dlqr command for cost function (2.50), define R = ε , N = 0 , and the states
weighting matrix Q as follows:
⎡Q1 0 ⎤ ⎡w I 0 ⎤
Q=⎢ ⎥ Q1 = wP ⋅ I 5 x 5 Q 2 = ⎢ S1 2 x 2
⎣ 0 Q 2⎦ ⎣ 0 wSH I 6 xx 6 ⎥⎦
epsilon=1e-5;
WP=0.005; %WP
WS1=5e5; %WS1
WSH=1e-2*5e5; %WH
Q1=WP*eye(size(Ad,1));
Q2=eye(size(Acon_d,1));
Q2(1:2,:)=WS1_W*Q2(1:2,:);
Q2(3:8,:)=WSH*Q2(3:8,:);
Q=[ Q1 zeros(size(Ad,1),size(Acon_d,2));
zeros(size(Acon_d,1),size(Ad,2)) Q2];
R=epsilon;
Now perform the optimal calculations of the gains using dlqr
[Kd,S,E]=dlqr(Ad_big,Bd_big,Q,R);
Kd=-Kd;
Scale the inputs by a constant to provide better dynamic range of matrix Bcon_d.
s_scale=600;
Bcon_d=s_scale*Bcon_d;
Kd(:,6:13)=Kd(:,6:13)/s_scale;
Numerical values of the optimum gains are:
61
>> Kd
Kd =
Columns 1 through 6
-5.4062 -0.2959 -0.9034 -0.4877 -0.6694 5.6999
Columns 7 through 12
12.8965 0.0013 0.0012 -0.0005 0.0018 -0.0019
Column 13
0.0006
>> Bcon_d
Bcon_d =
0.0053
0.1110
0.0105
0.1103
0.0209
0.1089
0.0207
0.1067
The servo compensator can then be implemented using:
x servo (k + 1) = Acon _ d ⋅ x servo ( k ) + Bcon _ d ⋅ error
62
CHAPTER 3
ANALYSIS AND SIMULATIONS OF THE SINGLE INVERTER CONTROL
The RSP controller developed in the previous chapter guarantees exact asymptotic
tracking of the fundamental frequency reference and error regulation of the load
disturbance at each of the harmonic frequency included in the servo compensators. The
RSP guarantees this property independent of any perturbations in the plant as long as they
do not destabilize system. Perturbations in a UPS system may come as results of load
disturbances, noise and uncertainties in the manufacturing of the components used. It is
important therefore to analyze the stability property of the resulting controller under
possible disturbances in order to ensure proper operation of the UPS over its intended
operating range.
A system is said to achieve robust stability if it remains stable for all considered
perturbations in the plant. In this chapter, the stability robustness of the system with the
controller developed in the previous chapter will be investigated using the Structured
Singular Values or µ-framework. Specifically, perturbations due to load variations and
parameters uncertainties of the filter components are considered.
63
Recall from the preceding chapter, that the chosen cost function
∞
⎛ ⎞
J ε = ∑ ⎜ w p ⋅ x *p (k ) ' ⋅ x *p ( k ) + wS1 ⋅η1 ( k )′ ⋅η1 (k ) + wSH ∑η h ( k )′ ⋅η h ( k ) + ε ⋅ u(k ) ' u( k ) ⎟ (3.1)
k =0 ⎝ h ⎠
provides a way of tuning the performance of the controller through the choice of the
weighting scalars w p , wS , and wSH . In this chapter, the effect of different choices of
these scalars to stability robustness of the system and its transient performance will be
investigated. It is important to remember that even though, each choice of the weighting
scalars results in stability of the nominal plant, each choice may not necessarily achieve
the robust stability of the system under plant uncertainties. The transient performance of
the system is evaluated by performing moving window RMS calculations of the three
phase output voltages under transient load change from 0 to 100% resistive load.
3.1 Robust Stability analysis
3.1.1 Robust Stability Analysis Using Structured Singular Value (µ)
Structured Singular Value (µ) can be used to analyze the stability robustness of a
Multi-Input-Multi-Output (MIMO) linear system under structured perturbations. In order
to use the µ-framework to analyze robust stability of a linear system under perturbation,
the problem needs to be recast into a feedback loop diagram of Fig. 3.1 where M
represents a known stable MIMO transfer function of the linear system with n inputs and
n outputs and ∆ a structured uncertainty matrix of the form (3.2)[116].
64
{
∆ = diag [δ 1 I r1 ,Kδ s I rs , ∆ 1 K ∆ F ] : δ i ∈ C , ∆ j ∈ C
m j xm j
} (3.2)
S F
∑ ri + ∑ m j = n
i =1 j =1
Figure 3.1 Representation of a linear system with uncertainties
The structured singular value of M with respect to the uncertainty set ∆ is defined as
[116]:
1
µ ∆ (M ) = (3.3)
min{σ (∆ ) : ∆ ∈ ∆, det (I − M∆ ) = 0}
The Generalized Small-Gain Theorem provides robust stability result of the
system using the structured singular value. It states that, if nominal M(s) is stable then the
perturbed system (I − M∆ ) is stable for all stable ∆ i for which ∆ i

−1
∞
≤ 1 if and only if
for all ω ∈ R [117].

µ ∆ (M ( jω )) > 1
1
65
Exact computation of µ ∆ (M ( jω )) is difficult. Commercial software, however, is
available (like Matlab µ-Tools toolbox), which computes upper and lower bound of µ by
several optimization steps [116].
As stated earlier, in order to use the µ-framework to analyze robust stability, the
problem needs to be recast to that of Fig. 3.1. A class of general feedback loops called
Linear Fractional Transformations (LFTs) can be used to achieve this. For complete
discussion of the LFT and its use in representing model uncertainties refer to [116].
66
3.1.2 Uncertain Open Loop Model
Figure 3.2 shows the single-phase equivalent circuit of the converter with RL
load, which represents the open-loop model of the plant
iinv isnd′ iload′

linv rinv ltrans rtrans
+
+ +
vpwm vinv cinv cload vload′ yrload ylload
- - -
Figure 3.2 Open loop model of the nominal plant
The dynamic equations of the plant are given by (3.4):
dvinv 1
= (iinv − ⋅isnd ′) (3.4.a)
dt cinv
diinv 1
= (− rinv ⋅ iinv − vinv + vpwm ) (3.4.b)
dt linv
dvload ′ 1
= (isnd ′ − yrload ⋅ vload ′ − il ) (3.4.c)
dt cload
disnd ′ 1
= (− rtran ⋅ isnd ′ + vinv − vload ′) (3.4.d)
dt l tran
dil
= yl load ⋅ vload ′ (3.4.e)
dt
iload ′ = yrload ⋅ vload ′ + il (3.4.f)
67
Let us assume that the following parameter variations exist in the system due to
manufacturing tolerances of the components used:
• Inverter filter capacitor tolerance: ±6%
• Inverter filter inductor tolerance: ±15%
• Inverter filter inductor losses tolerance: ±50%
• Output filter capacitor tolerance: ±6%
• Transformer filter inductor tolerance: ±15%
• Transformer filter inductor losses tolerance: ±50%
Furthermore, the specification of the unit requires that it operates stably without
degradation in performance for load from 0 to 200% with power factor of 0.8 lagging at
maximum load. Beyond this point, the UPS shall transfer the load to bypass static switch
automatically. This specification represents variation of the resistive load from 0 to
160%, and inductive load from 0 to 120%.
The above parameters variations due to manufacturing components tolerances and
load variations can be precisely written as follows:
cinv = cinvnom (1 + cinvtol ⋅ δ cinv ) , δ cinv < 1 (3.5.a)
linv = linvnom (1 + linvtol ⋅ δ linv ) , δ linv < 1 (3.5.b)
cload = cload nom (1 + cload tol ⋅ δ cload ) , δ cload < 1 (3.5.c)
linv = linvnom (1 + linvtol ⋅ δ linv ) , δ linv < 1 (3.5.d)
rinv = rinvnom (1 + rinvtol ⋅ δ rinv ) , δ rinv < 1 (3.5.e)
rtrans = rtranstnom (1 + rtranstol ⋅ δ rtrans ) , δ rtrans < 1 (3.5.f)
68
yrload = yrload nom (1 + yrload tol ⋅ δ yrload ) , δ yrload < 1 (3.5.g)
yl load = ylload nom (1 + ylload tol ⋅ δ ylload ) , δ ylload < 1 (3.5.h)
Terms with subscript nom indicate the nominal values of the parameters as given in
(2.14), with yrload nom = 0.8 , and ylload nom = 0.6 . The tolerances are assigned as follow:
cinv tol = 0.06 , linvtol = 0.15 , cload tol = 0.06 , ltranstol = 0.15 , rinvtol = 0.5 ,
rtranstol = 0.5 , yrload tol = ylload tol = 1.0
Parameters cinv , linv , cload , and ltrans appear as their inverses in the dynamic
equations (3.4), and can be represented using lower LFT as shown in Fig. 3.3. For rinv ,
rtrans , yrload , and yl load , define the following:
rinvdel ≡ rinv nom rinvtol , (3.6.a)
rtransdel ≡ rtransnom rtranstol , (3.6.b)
yrload del ≡ yrload nom yrload tol , and (3.6.c)
ylload del ≡ ylload nom ylload tol , (3.6.d)
then these parameters can be represented as LFTs shown in Fig. 3.4.
69
1 1 1 1
⇔
⇔
⇔
⇔
⎡ 1 ⎤ ⎡ 1 ⎤ ⎡ 1 ⎤ ⎡ 1 ⎤
− cinvtol ⎥ ⎢ linv − linvtol ⎥ ⎢ cload − cload tol ⎥ − ltranstol ⎥
⎢ cinv ⎢ ltrans
⎢ nom
⎥ ⎢ nom
⎥ ⎢ nom
⎥ ⎢ nom
⎥
⎢ 1 ⎢ 1 ⎢ 1 1
− cinvtol ⎥ − linvtol ⎥ − cload tol ⎥ ⎢ − ltranstol ⎥
⎣⎢ cinv nom ⎦⎥ ⎣⎢ linvnom ⎦⎥ ⎣⎢ cload nom ⎦⎥ ⎣⎢ ltransnom ⎦⎥
δ cinv δ linv δ cload δ ltrans
Figure 3.3 LFTs for 1 , 1 ,1 , and 1

rinv rtrans yrload ylload

⇔
⇔
⇔
⎡rinv rinvdel ⎤ ⎡rtrans rtrans del ⎤ ⎡ yrloadnom yrloaddel ⎤ ⎡ ylload nom ylload del ⎤
⎢ 1 ⎢ 1 0 ⎥⎦
0 ⎥⎦
⎢ 0 ⎥⎦ ⎢ ⎥
⎣ ⎣ 1 ⎣ 1 0 ⎦
⎣
δ rinv δ rtrans δ yrload δ ylload
Figure 3.4 LFTs for rinv , rtrans , yrload , and yl load
70
For each uncertain term, the corresponding LFT in Fig 3.3 and Fig. 3.4 can be
substituted in to the dynamic model of equation (3.4), with the uncertain perturbations
separated out as shown in Fig. 3.5. The diagram shown in Fig. 3.5 contains all the known
model of the plant and will be referred to as the nominal open-loop plant model P. This
model can be combined with a structured perturbation model as shown in Fig. 3.6 which
shows the interconnection with the structured uncertainty set ∆ .
71
iinv
∫
⎡ 1 ⎤ vinv
⎢ cinv − cinvtol ⎥
isnd
wcinv ⎢ nom
⎥ zcinv
⎢ 1 − cinvtol ⎥
⎢⎣ cinvnom ⎥⎦
iinv
⎡ rinv rinvdel ⎤
∫
iinv
vinv ⎡ 1 ⎤
⎢ 1 0 ⎥⎦
z rinv
⎢ linv − linvtol ⎥
wrinv
⎣ vpwm ⎢ nom
⎥
wlinv ⎢ 1 − linvtol ⎥ zlinv
⎢⎣ linv nom ⎥⎦
vload
∫
⎡ yrloadnom yrloaddel ⎤ il vload
⎢ ⎡ 1 ⎤
w yrload ⎣ 1 0 ⎥⎦ z yrload ⎢ cload − cload tol ⎥
isnd ⎢ nom
⎥
⎢ 1
wcload − cload tol ⎥ zcload
⎢⎣ cload nom ⎥⎦
isnd
∫
⎡rtrans rtrans del ⎤ isnd
⎢ 1 ⎡ ⎤
0 ⎥⎦
vload 1
wrtrans ⎣ z rtrans ⎢ ltrans − ltranstol ⎥
vinv ⎢ nom
⎥
⎢ 1
wltrans − ltranstol ⎥ zltrans
⎣⎢ ltransnom ⎦⎥
∫
vload il
⎡ ylload nom ylload del ⎤
⎢ ⎥
w ylload ⎣ 1 0 ⎦ z ylload
iload
il
Figure 3.5 Block diagram of the nominal plant
72
vpwm vinv
iinv
vload
iload
wcinv zcinv
wlinv zlinv
wcload P (s ) zcload
wltrans zltrans
wrinv z rinv
wrtrans zrtrans
w yrload z yrload
w ylload z ylload
wcinv zcinv
⎛ δ cinv ⎞
wlinv ⎜ ⎟ zlinv
wcload ⎜ δ linv ⎟
⎜δ ⎟ zcload
wltrans ⎜ cload ⎟ zltrans
⎜ δ ltrans ⎟
wrinv ∆ (s ) = diag ⎜ ⎟ z rinv
δ
wrtrans ⎜ rinv ⎟ zrtrans
w yrload ⎜ δ rtrans ⎟
⎜δ ⎟ z yrload
w ylload ⎜ yrload ⎟ z ylload
⎜δ ⎟
⎝ ylload ⎠
Figure 3.6 Interconnection of the nominal open loop plant with ∆ to form uncertain open
loop model
73
The state space model of the nominal plant P can be derived from Fig. 3.5 with
the following states, inputs, and outputs variables:

r
States: x = [vinv iinv vload il ]
T
isnd
Inputs: u = [vpwm wcinv w ylload ]

r T
wlinv wcload wltrans wrinv wrtran w yrload
Outputs:
y = [vinv iinv vload z ylload ]

r T
iload z cinv z linv z cload zltrans z rinv z rtran z yrload
The state space equations are given as:

v r r
x& = AP x + BP u
r r r
y = C P x + DP u (3.7)
where
⎡C ⎤ ⎡D ⎤
AP = [Anom ] BP = [Bnom Bdel ] C P = ⎢ nom ⎥ DP = ⎢ nom ⎥ (3.8)
⎣ C del ⎦ ⎣ Ddel ⎦
⎡ 1 −1 ⎤
⎢ 0 0 0 ⎥
cinvnom cinv nom
⎢ ⎥
⎢ −1 − rinvnom ⎥
0 0 0
⎢ linvnom linvnom ⎥
AP = ⎢ − yrload nom 1 −1 ⎥
⎢ 0 0 ⎥
⎢ cload nom cload nom cload nom ⎥
⎢ 1 −1 − rtransnom ⎥
⎢ ltrans 0 0 ⎥
ltransnom ltransnom
⎢ nom
⎥
⎣ 0 0 ylload nom 0 − rε ⋅ ylload nom ⎦
T
⎡ 1 ⎤
Bnom = ⎢0 0 0 0⎥
⎣ linvnom ⎦
74
⎡ − cinv tol 0 0 0 0 0 0 0 ⎤
⎢ − rinvdel ⎥
⎢ 0 − linvtol 0 0 0 0 0 ⎥
⎢ linvnom ⎥
− yrload del
Bdel = ⎢⎢ 0 0 − cload tol 0 0 0 0 ⎥
⎥
cload nom
⎢ − rtransdel ⎥
⎢ 0 0 0 − ltranstol 0 0 0 ⎥
⎢ ltransnom ⎥
⎢⎣ 0 0 0 0 0 0 0 ylload del ⎥⎦
⎡1 0 0 0 0 0 0 0⎤
⎢0 1 0 0 0 0 0 0⎥
C nom =⎢ ⎥
⎢0 0 1 0 0 0 0 0⎥
⎢ ⎥
⎣0 0 yrload nom 0 1 0 0 0⎦
⎡ 1 −1 ⎤
⎢ 0 0 0 ⎥
cinv nom cinv nom
⎢ ⎥
⎢ −1 − rinvnom ⎥
0 0 0
⎢ linvnom linvnom ⎥
⎢ − yrload nom 1 −1 ⎥
⎢ 0 0 ⎥
⎢ cload nom cload nom cload nom ⎥
C del =⎢ 1 −1 − rtransnom ⎥
⎢ ltrans 0 0 ⎥
ltransnom ltransnom
⎢ nom
⎥
⎢ 0 1 0 0 0 ⎥
⎢ 0 0 0 1 0 ⎥
⎢ ⎥
⎢ 0 0 1 0 0 ⎥
⎢⎣ 0 0 1 0 0 ⎥⎦
r
⎡ 03 x 9 ⎤
Dnom =⎢ ⎥
⎣0 0 0 0 0 0 0 yrload del 0⎦
75
⎡ 0 − cinv tol 0 0 0 0 0 0 0⎤
⎢ 1 − rinv del ⎥
⎢ 0 − linv tol 0 0 0 0 0⎥
⎢ linv nom linv nom ⎥
⎢ 0 − yrload del
0 0 − cload tol 0 0 0 0⎥
⎢ cload nom ⎥
⎢ − rtrans del ⎥
Ddel =⎢ 0 0 0 0 − ltranstol 0 0 0⎥
⎢ ltrans nom ⎥
⎢ 0 0 0 0 0 0 0 0 0⎥
⎢ ⎥
⎢ 0 0 0 0 0 0 0 0 0⎥
⎢ 0 0 0 0 0 0 0 0 0⎥
⎢ ⎥
⎢⎣ 0 0 0 0 0 0 0 0 0⎥⎦
76
3.1.3 Using Matlab to Derive Uncertain Closed Loop Model
As stated earlier, in order to use the µ -framework to analyze the robust stability
of the system, the system needs to be recast in to that of Fig. 3.1. In this case, the system
comprises of the nominal open loop P plant with the controller loop closed around it as
illustrated in Fig. 3.7.a. The system enclosed by the box in Fig. 3.7.a needs to be
combined to form the closed loop plant M as shown in Fig. 3.7.b. Matlab, specifically the
µ -Analysis and Synthesis Toolbox, has been utilized to help in achieving this purpose. A
complete listing of Matlab M-file discussed in this section is given in Appendix B.
error
vref
vref error
wcinv z cinv
wlinv zlinv
vpwm vinv wcload zcload
⇔
iinv wltrans zltrans
vload wrinv zrinv
wrtrans M (s ) zrtrans
iload
w yrload z yrload
wcinv zcinv w ylload z ylload
wlinv zlinv
wcload P (s ) zcload
wcinv z cinv
wltrans zltrans
⎛ δ cinv ⎞
wrinv z rinv wlinv ⎜ ⎟ zlinv
wrtrans zrtrans ⎜δ ⎟ zcload
w yrload z yrload
⎜ δ ltrans ⎟
w ylload
wrinv ∆ (s ) = diag ⎜ ⎟ zrinv
z ylload δ
⎜ δ rtrans ⎟
w yrload ⎜δ ⎟ z yrload
wcinv zcinv ⎜δ ⎟
⎛ δ cinv ⎞ ⎝ ylload ⎠
wlinv ⎜ ⎟ zlinv
⎜δ ⎟ zcload
⎜ δ ltrans ⎟
wrinv ∆ (s ) = diag ⎜ ⎟ zrinv
δ
w yrload
⎜ δ rtrans ⎟
⎜δ ⎟ z yrload
⎜δ ⎟
⎝ ylload ⎠
(a) (b)
Figure 3.7 Uncertain closed loop model
77
Since the controller is implemented in the discrete time system, the following
steps are necessary to obtain the closed loop plant model in Fig. 3.7.b:
• Apply a Zero Order Hold transformation to the continuous plant P, to include the
effect of the sample and hold process of the digital sampling process. This step
should also include the half sampling time computation delay. Let Ap, Bp, Cp, Dp be
the Matlab variables that hold the matrices in (3.8), then this step can be
accomplished with the following Matlab command:
sysp=ss(Ap,Bp,Cp,Dp);
sysp.inputdelay=[0.5*Tsamp zeros(1,8)];
syspd=c2d(sysp,Tsamp,'zoh');
• Transform the discretized plant back to continuous system in the w-plane by
applying an inverse Tustin transformation. This transformation has the property of
preserving the frequency response of the discrete time systems.
sysp_w=d2c(syspd,'tustin');
[Ap_c,Bp_c,Cp_c,Dp_c]=ssdata(sysp_w);
• Obtain state space representations of the RSP and Discete Sliding Mode controller
with inputs and outputs definitions as shown in Fig. 3.8
78
vref err
icmd
vinv
vload iinv vinv
vpwm
vload iinv
iload iload
vpwm
Figure 3.8 The RSP and DSM controllers
The discrete sliding mode controller with one-half step ahead predictor can be
r
written in state space form with the inputs u ( k ) = [icmd vinv iinv iload ] and
outputs y ( k ) = vpwm as:

r r
x ( k + 1) = ASM x (k ) + BSM u ( k )
r r r
y ( k ) = C SM x + DSM u (3.9)
where
⎡0 1 0 0 ⎤
ASM = 0 3 x 3 BSM = ⎢0 0 1 0 ⎥
⎢ ⎥
⎣⎢0 0 0 1⎦⎥
C SM = [Ksm3 Ksm5 Ksm7 ]
DSM = [Ksm1 Ksm2 Ksm4 Ksm6 ]
Ksm is the DSM control gains obtained in section 2.3.3 Step 3.
The perfect robust servo-compensators with output y ( k ) = vpwm and inputs
79
r
u ( k ) = [err vinv iinv vload iload vpwm],
can be written in state space form as in (3.10):

r r r
x ( k + 1) = Aservo x (k ) + Bservo u ( k )
r r r
y ( k ) = C servo x + Dservo u (3.10)
where:
⎡ Acon _ d 0 2 hx1 ⎤ ⎡ Bcon _ d 0 2 hx 5 ⎤

Aservo = ⎢ Bservo = ⎢
⎣ 01 x 2 h 0 ⎥⎦ ⎣ 01 x 5 0 ⎥⎦
C servo = [Kd 6 K Kd13 Kd 5 ] Dservo = [0 Kd1 K Kd 4 0]
The combined controller state-space system can then be calculated using sysic
( µ -Toolbox) command in Matlab [116] as follows:
dsm=pck(Asm,Bsm,Csm,Dsm);
servo=pck(Aservo,Bservo,Cservo,Dservo);
systemnames='dsm servo';
inputvar='[err; plant{4}]';
outputvar='[dsm]';
input_to_dsm='[servo; plant(1,2,4)]';
input_to_servo='[err; plant(1:4) ; dsm]';
sysoutname='Hcontrol_d';
cleanupsysic = 'yes';
sysic;
• The combined controller system is then transformed into the w-plane in
continuous domain using the inverse Tustin transformation. In Matlab this can be
achieved using
[Acontrol,Bcontrol,Ccontrol,Dcontrol]=unpck(Hcontrol_d);
sys_con_d=ss(Acontrol,Bcontrol,Ccontrol,Dcontrol,Tsamp);
• Finally the closed loop plant model P is obtained by invoking the sysic command
with the following specification:
80
plant_nom_w=pck(Ap_c,Bp_c,Cp_c,Dp_c);
controller_w=pck(Acontrol,Bcontrol,Ccontrol,Dcontrol);
systemnames='plant_nom_w controller_w';
inputvar='[vref ; w{8}]';
outputvar='[vref-plant_nom_w(3); plant_nom_w(5:12)]';
input_to_plant_nom_w='[controller_w; w(1:8)]';
input_to_controller_w='[vref-plant_nom_w(3);plant_nom_w(1:4)]';
sysoutname='M;
sysic;
The Matlab variable M contains the closed loop plant M as shown in Fig. 3.7.b.
81
3.1.4 Computing Individual Perturbation Frequency Response and the Structured
Singular Value using Matlab
Now that the closed loop plant M has been obtained, we are ready to compute the
frequency response of M(jw). This is accomplished using the following:
omega=logspace(-1,5,500);
clp_g=frsp(clp_w,omega);
In the robust stability study, we only need to consider the transfer functions seen by the
perturbations. These transfer functions can be obtained from clp_g above using:
clpstab_g=sel(clp_g,2:9,2:9);
It is instructive to plot the individual perturbation frequency response in order to obtain
insight as to how each parameter affects the system. The following commands are used to
plot these
for i=1:8
subplot(4,2,i)
vplot('liv,m',sel(clpstab_g,i,i));
grid
end
Finally the structured singular value of the system for robust stability study is obtained
using the following:
deltaset = [-1 0;-1 0;-1 0; -1 0; -1 0; -1 0; 1 1; 1 1];

[bnds,dvec,sens,pvec] = mu(clpstab_g,deltaset);
vplot('liv,m',bnds);
82
3.2 Tuning the controller performance using w p , wS , and wSH
Recall from the previous chapter the w p , wS , and wSH in cost function (3.1) are
the weighting scalars for the plant states, fundamental, and harmonic servo compensator
states respectively. The selection of values of these scalars provides a way of tuning the
controller for desired transient performance and stability robustness. The structured
singular value discussed in the previous sections will be used to evaluate the robust
stability of each controller resulting from different choices of weighting scalars. A time
response simulation of the single phase equivalent circuit will be used to compare the
transient performance of each controller. To quantify the transient performance, it is
common in the industry to use the deviation of the RMS output voltage from its nominal
value during a 100% resistive load change as a performance measure. A less than 5%
deviation of output voltage under 100% resistive load transient is not an uncommon
specification in the industry for a high performance UPS.
Consider the following cases of weighting scalars below.
Case 1: w p = 0.5 , wS = 5 × 105 , and wSH = wS
In all the cases above, equal weighting scalars are applied to the fundamental
compensator states and the harmonic states ( wSH = wS ), while the plant states weighting
83
w p in each case is decreased from 0.5 all the way down to 0.0001. The time response
simulations for Case 1 and Case 4 are illustrated in Fig. 3.9 and Fig. 3.10 respectively,
each of which showing the output voltage, reference voltage, load current, and RMS
variation of the output voltage during both 0 to 100% and 100% to 0% resistive load
transients. From Fig. 3.9 and Fig. 3.10 it can be seen that the output voltage RMS
deviates as much as close to 20% for Case 1 and approximately 4% for Case 4.
The time response similar to Fig. 3.9 and Fig. 3.10 was obtained for each of the
cases 1 to 5 and the resulting RMS output voltage variations are plotted collectively in
Fig. 3.11. It can be seen that as the scalar weighting w p decreases, the transient
performance improves, with the RMS variation as little as 2% for the case w p = 0.0001 .
These results are not unexpected since the weighting scalars represent the penalty applied
to each state in the system. Intuitively, decreasing w p while keeping the compensator
states weighting the same, decreases the penalty cost applied to the plant states in the cost
function to be minimized. This results in allowing the plant states to move more freely
and hence faster response. Notice, however, that only Case 4 and Case 5 results in RMS
variations of less than 5%.
To analyze the robust stability, the upper bound of the structured singular value in
each case is plotted in 3.12. It can be seen that only Case 1, Case 2, and Case 3 achieve
robust stability under the considered structured perturbations with the peak value of in
µ ∆ (M ( jω )) each case being less than 1. Case 4 and case 5 --the only cases with
acceptable transient performances-- do not achieve robust stability with the peak values
of µ ∆ (M ( jω )) being 1.1 and 4 respectively.
84
Figure 3.9 Transient response for Case 1: w p = 0.5 , wS = 5 × 105 , and wSH = wS (Top:
Output voltage and its reference, Middle: Load current, Bottom: RMS variations of
output voltage).
Figure 3.10 Transient response for Case 4: w p = 0.005 , wS = 5 × 105 , and wSH = wS (Top:
Output voltage and its reference, Middle: Load current, Bottom: RMS variations of
output voltage).
85
Figure 3.11 RMS output voltage variations during 0 to 100% and 100% to 0 for
different w p ,and wSH = wS
86
Figure 3.12 Upper bound of the structured singular values for different w p ,and wSH = wS
87
Consider now the following cases of scalars weighting:
Case 6: w p = 0.5 , wS = 5 × 105 , and wSH = 0.01 × wS
In the cases 6 to 10 the wP is assigned the same value as in Cases 1 to 5 respectively, but
smaller weighting is used for the harmonic compensator states as compared to the
fundamental’s. Fig 3.13 and Fig. 3.14 show the time responses of Case 6 and Case 9
respectively, while Fig. 3.15 shows the RMS variations for all cases. Comparing Fig.
3.13 thru 3.15 with Fig. 3.9 thru 3.11, it can be seen that the transient response improves
for each of the last 5 cases, with Case 9 and Case 10 now result in only 2% and 1% RMS
variations respectively.
Fig. 3.16 shows the upper bound of the structured singular value in Cases 6 to 10.
It can be seen that reducing wSH improves the stability robustness of each of the cases
previously considered. The counterpart of Case 4 (Case 9) now achieves robust stability
with µ ∆ (M ( jω )) peak value of 0.7 giving robust stability margin of 1 > 1 . Case 10 still
0.7
does not achieve robust stability with peak value of µ ∆ (M ( jω )) still greater than 1.
Comparing all the above cases, it can be seen that Case 9 gives the best transient
performance while still maintaining stability robustness of the system under the
structured perturbations considered.
88
Figure 3.13 Transient response for Case 6: w p = 0.5 , wS = 5 × 105 , and wSH = 0.01 × wS
(Top: Output voltage and its reference, Middle: Load current, Bottom: RMS variations
of output voltage).
Figure 3.14 Transient response for Case 9: w p = 0.005 , wS = 5 × 105 , and wSH = 0.01 × wS
(Top: Output voltage and its reference, Middle: Load current, Bottom: RMS variations
of output voltage).
89
Figure 3.15 RMS output voltage variations during 0 to 100% and 100% to 0 for
different w p ,and wSH = 0.01 × wS
90
Figure 3.16 Upper bound of the structured singular values for different w p ,and
wSH = 0.01 × wS
91
Continuing with the analysis, it is instructive to see how each parameter
perturbation affects the stability robustness of the system. For this purpose, the frequency
response of each individual perturbation can be plotted as shown in Fig, 3.17 for the
system with controller in Case 9.
Figure 3.17 Individual-perturbation frequency response for system with controller in

Case 9. (X-axis in each plot is frequency in rad/sec)
92
It can be seen from Fig. 3.17 that for all the perturbations, the frequency response
values are less than 1.0, which confirms the stability robustness result of the structured
singular value presented earlier. The inverter filter inductor has the highest peak
frequency response value, with peak value of around 0.7, which means that an individual
perturbation in this parameter will be the closest to the margin of making the system to be
unstable. Closed loop pole-zero map of the uncertain closed loop system in Figure 3.6
with all other δ ’s set to zero except for the δ linv can be obtained for different values of
δ linv less than 1 and greater than 1. This is illustrated in Fig. 3.18. The system is stable at
nominal inductance value ( δ linv = 0 ), δ linv = −0.5 , and at the lowest value of the
component tolerance ( δ linv = −1.0 ). As the value δ linv is decreased further the system
finally becomes unstable at δ linv slightly less than -1.4.
93
Figure 3.18 Pole-zero map of closed loop uncertain system for different values of
individual-perturbation in inverter filter inductance parameter
94
3.3 Simulations of the Complete System
In this section, simulation results of the complete three-phase converter system
including the PWM inverter are presented. The simulations have been performed in
Simulink Matlab with SimPowerSystem Blocksets. The SimPowerSystem Toolbox
allows simulation of power electronic circuit devices and components in Simulink,
requiring only interconnection of library components models for building the circuits for
simulations.
The simulation results presented in this report have been obtained using the
proposed control strategy with the controller obtained in Case 9 in the previous section.
The following cases will be investigated
1. Regulation under linear load
2. Transient performance.
3. Harmonic tracking and regulation under non-linear load
4. Short Circuits at the output terminals
The PWM switching frequency is chosen to be 5400 Hz and the control update
rate is equal to the PWM switching period giving an update rate of 90 times per 60 Hz
line cycle (Tsamp=1/60/90)
95
3.3.1 Steady state performance
Fig. 3.19 thru Fig. 3.21 show the steady state waveforms of load currents, load
voltages, and inverter voltages for different types of load both from simulations and
experimental results. The RMS values of the line-to-line load voltages for each case is
given in Table 3.1 It can be seen from Table 3 that all the numbers show that the
regulations of the load voltages are within 1%.
Load Simulation
Ph. A Ph. B Ph. C
No load 120.0 120.0 120.0
Full load 120.0 120.0 120.0
1-phase 119.7 121.1 119.2
2-phase 119 120.8 120.3
Table 3.1 Output voltages regulation
96
Figure 3.19 Simulation results for balanced full resistive load
97
Figure 3.20 Simulation results for unbalanced single-phase resistive load
98
Figure 3.21 Simulation results for unbalanced two-phase resistive load
99
3.3.2 Transient Performance
Fig. 3.22 and Fig. 3.23 show the simulation results respectively for 0-
100% load transient. It can be seen that the waveforms of the voltages and currents for
both cases look very similar. The voltage transients in both cases were characterized by
the existence of dips in the voltages and followed by slight overshoots exhibiting some
5th and 7th harmonic contents. The harmonics showed up as responses of the servo
harmonic compensator to load transients. Notice that the load transient lasts for only one
cycle of the fundamental, which shows the fast response of the controller. Also, in any
cases the RMS load voltages variation were less than the 5% meeting the specification
required.
100
Figure 3.22 Simulation results for 0-100% resistive load transient
101
Figure 3.23 Simulation results for 0-100% resistive load transient
102
3.3.3 Harmonic tracking and regulation under non-linear load
To verify the effectiveness of the controller in rejecting the disturbance caused by
harmonics disturbances, the system can be tested under non-linear load. However, since a
non-linear load may contain other harmonics than those included in the servo
compensators, it is hard to judge whether or not each harmonic compensator has been
implemented correctly. As an alternative, test may be conducted to verify how well the
controller can track references containing the specified harmonics. This in turn will give a
good indication of how well the controller can reject those harmonic disturbances.
In Fig. 3.24, 3.25, 3.26, and 3.27, simulation results are presented for cases when
the DQ voltages references contain only the fundamental component, the fundamental
with 5th harmonic, the fundamental with 7th harmonic, and the fundamental with 5th and
7th harmonics, respectively. It can be seen that in all cases the actual DQ voltages follow
the harmonic references perfectly. This indicates that the controller in turn is able to
reject disturbances at the 5th and 7th harmonic frequencies.
103
200
Vrefq & Vloadq (volts)

100
-100
-200
0.05 0.055 0.06 0.065 0.07 0.075 0.08 0.085 0.09 0.095 0.1
200
Vrefd & Vloadd (volts)
100
-100
-200
0.05 0.055 0.06 0.065 0.07 0.075 0.08 0.085 0.09 0.095 0.1
Figure 3.24 Simulation result: Tracking of fundamental references
200
100
-100
-200
0.05 0.055 0.06 0.065 0.07 0.075 0.08 0.085 0.09 0.095 0.1
200
100
-100
-200
0.05 0.055 0.06 0.065 0.07 0.075 0.08 0.085 0.09 0.095 0.1
Figure 3.25 Simulation result: Fundamental with 5th harmonic references tracking
104
200

100
-100
-200
0.05 0.055 0.06 0.065 0.07 0.075 0.08 0.085 0.09 0.095 0.1
200
100
-100
-200
0.05 0.055 0.06 0.065 0.07 0.075 0.08 0.085 0.09 0.095 0.1
Figure 3.26 Simulation result: Fundamental with 7th harmonic references tracking
200
100
-100
-200
0.05 0.055 0.06 0.065 0.07 0.075 0.08 0.085 0.09 0.095 0.1
200
100
-100
-200
0.05 0.055 0.06 0.065 0.07 0.075 0.08 0.085 0.09 0.095 0.1
Figure 3.27 Simulation result: Fundamental with 5th and 7th harmonic references tracking
105
3.3.4 Short Circuit at the output terminals
The final verification to the proposed control algorithm is for its ability to limit
the inverter currents under short circuits at the output terminal. Fig. 3.28 shows the
simulation results for this condition. In this case, the current limit was set at 300% level..
From these figures it can be seen that the discrete sliding mode controller provides a fast
and minimal overshoot on the inverter currents.
Figure 3.28 Simulation result: Short circuits at the output terminals
106
CHAPTER 4
EXPERIMENTAL RESULTS OF SINGLE INVERTER CONTROL
4.1 5kVA Experimental Test Bed
The effectiveness the proposed control strategy has been verified on a 5 kVA
experimental test bed built at the Mechatronics Laboratory of the Ohio State University.
Fig. 4.1 shows a block diagram of the test bed. The converter system consists of the
following:
• Three-phase 240 V utility input that also acts as the bypass source.
• A three-phase PWM rectifier system built from a Semikron Power converter
system consisting of 1200V/50A IGBT modules (SKM 50 GB 123 D) with a gate
driver module (SKHI-22), three-phase input filter inductors with inductance of 8.4
mH, and DC bus capacitors with total capacitance of 2200 µF
• A three-phase PWM inverter system built from a second Semikron Power
converter system with 1200V/50A IGBT modules (SKM 50 GB 123 D) and a
gate driver module (SKHI-22).
• Inverter LC filter with the following component values: Linv = 1.8mH ,
Cinv = 55µF and Cout = 5µF
107
• A 6 kVA, 60 Hz, 240V Delta/208V Wye, Z=3% three-phase isolation
transformer
• Load for the PWM inverter consists of a linear load with resistive and inductive
components, and non-linear load consisting of three single-phase diode rectifiers
as shown in Fig. 4.2
108
⎡Vinv ab ⎤
⎡Vload an ⎤
⎡Vbyp ab ⎤ ⎡Vpwm ab ⎤ ⎢Vload ⎥
⎢Vbyp ⎥
⎢ bc ⎥ ⎢ bc ⎥ ⎢ bn ⎥
⎢ bc ⎥
⎣⎢Vpwm ca ⎦⎥ ⎣⎢Vinv ca ⎦⎥ ⎣⎢Vload cn ⎦⎥
⎣⎢Vbyp ca ⎦⎥
2.0mH
Iin a Iinv a Iload a
1100uF Vdc 1100uF

Iin b Iinv b
Iload b
Iin c Iinv c
Iload c
109
Figure 4.1 The 5 kVA Experimental Test Bed System
Figure 4.2 Three single-phase diode rectifier as non-linear load
Two Texas Instruments TMS320F2407 Digital Signal Processor control systems
have been designed to provide independent control of the three-phase PWM rectifier and
the three-phase PWM inverter as shown in Fig. 4.1. Signal conditioners circuits have
been designed and built to provide interfacing of the high voltages and currents
measurements to the on-chip Analog Digital Converter system of the TMS320F2407
DSP. Complete descriptions of the signal conditioning/interface circuitries and firmware
code used in this research are given in reference [141].
110
4.2 Experimental Results
4.2.1Performance measures of the proposed control
Table 4.1 gives the steady state RMS output voltages regulation under different
types of loads. It can be seen that the control strategy provides good output voltages
regulation in all cases. Note that, the deviations in the output voltages for unbalanced
load are due to the uncontrollable 0-component of the load currents. However, as can be
seen the effect is minimal showing the effectiveness of the LC filter at the output side of
the transformer.
Fig. 4.3 shows the waveforms of the load currents, load voltages, and inverter
voltages under various linear loads: resistive, inductive, balanced, and unbalanced load.
Table 4.2 summarizes the output voltages THD under different types of loads showing
the superior THD performance of the proposed control strategy. Better results may be
obtained by including more harmonics to be eliminated into the robust servomechanism
controller.
Fig. 4.4 and 4.5 show the responses of the load voltages on resistive load
transients, 0-100% and 100%-0 respectively. It can be seen that the load voltages recover
within less than a cycle after the load is applied. Even though in both cases the output
voltages exhibit slight overshoot due to the under-damped nature of the control, the
output voltages magnitudes deviate less than 5% of the nominal. These results show that
the perfect RSP controller provides fast transient recovery under load transients with
minimal overshoot in the response.
111
Finally, the effectiveness of the current controller was verified by applying a
sudden three-phase short circuit on the output load terminals. The current limit was set at
300% level, and the inverter was shutdown deliberately after ten cycles of short circuit
condition. The results are shown in Fig. 4.6. It can be seen that the discrete sliding mode
controller provides a fast and minimal overshoot on the inverter currents.
Load Experiments
Ph. A Ph. B Ph. C
No load 119.9 120.1 120.1
Full load resistive 119.9 120.1 120.1
1-phase resistive 119.6 121.2 119.3
2-phase resistive 118.9 120.9 120.4
Full load 0.8pf lag 119.9 120.1 120.1
Full load Non-linear 119.9 120.1 120.1
Table 4.1 Output voltages regulation
TYPES OF LOAD Output voltages THD

No load 0.90%
100% balanced resistive load 0.50%
100% 0.8 pf load 0.8%
100% unbal. resistive (ph.A) 0.7%
100% unbal. resistive (ph.A&B) 0.6%
Non-linear load 2.2%
Table 4.2 Output voltages THD
112
(a) (b)
(c) (d)
Figure 4.3 Steady state linear load (a) 100% resistive balanced (b) 100% 0.8pf load (c)
100% resistive unbalanced (phase A unloaded) (d) 100% resistive unbalanced (phase
A&B). Top: load currents; middle: load voltages; bottom: inverter voltages.
Figure 4.4 Resistive load transient: 0% to 100%. Top: three-phase load currents, bottom:
three-phase load voltages resistive load transient
113
Figure 4.5 Resistive load transient:100% to 0% Top: three-phase load currents, bottom:
three-phase load voltages resistive load transient
Figure 4.6 Three-phase short-circuit on output terminals. Top: inverter currents, middle:
load voltages, and bottom: inverter voltages.
114
4.2.2 Comparison with Synchronous Reference Frame Control with PI controllers
It is instructive to compare the proposed control with commonly used PI
controllers. To provide a fair comparison, the PI controls should preferably be performed
in synchronous reference frame where perfect sinusoidal quantities will appear as dc
quantities. Note that it is not necessary for the proposed control to be performed in the
synchronous frame, since the proposed control can guarantee zero steady state error for
signals varying at fundamental frequency. Fig. 4.7 shows the synchronous reference
frame control of the voltages and currents using the PI controllers. In this figure, the
voltages and currents are expressed in the synchronous reference frame using
transformation (4.1):
f qe = f qs ⋅ cos ωt − f ds ⋅ sin ωt
(4.1)
f ds = f qs ⋅ sin ωt + f ds ⋅ cos ωt
where the qs and ds subscripts denote variables in the stationary reference frame,
the qe and de denote the synchronous reference frame variables, and ωt represent the
phase angle of the voltages references. Given three-phase balanced voltages references, it
can be shown using (4.1) that the de and qe references voltages in the synchronous
reference frame are given by the maximum value of the reference voltage Vmax and 0
respectively as shown in Fig. 4.7. The control shown in Fig. 4.7 also includes decoupling
terms [26] that are used to compensate for the coupling of the d and q dynamics due to
transformation (4.1), and feed forward terms used to improve transient performance.
115
Iqeload Vqeinv
*
0
Iqeinv Vqe pwm
ω ⋅ Cinv ω ⋅ Linv
Vqeinv Iqeinv
Vdeinv Ideinv
ω ⋅ Cinv ω ⋅ Linv
Vde pwm *
V max
Ideinv *
Ideload Vdeinv
Figure 4.7 Synchronous Reference Frame Voltage and Current Control with PI
controllers
It is worth noting that, if properly tuned, the control given in Fig. 4.8 can easily
provide a good transient response for sudden load changes. Also, based on the internal
model principle [86], since the PI controller includes an integral term ( 1 s ), the controller
guarantees zero steady state error for references and disturbances at zero frequency in
synchronous reference frame, which in turn correspond to fundamental frequency
references and disturbances in abc reference frame. Therefore, it is expected that the
control in Fig. 4.7 would have a good steady state voltage regulation and low total
harmonic distortion (THD) voltage when only linear balanced loads are applied.
However, when disturbances other than the zero frequency (in synchronous reference
frame) exist, then the PI controller can no longer guarantee a perfect regulation at steady
state. Note that, even though unbalanced linear loads in abc reference frame (or
stationary reference frame) vary at fundamental frequency, in synchronous reference
116
frame they appear as signals varying at frequency other than 0 as apparent from
transformation (4.1). Therefore, the PI controllers shown in Fig. 4.7 would not yield
satisfactory steady performance for non-linear harmonics and unbalanced non-linear and
linear loads.
Figure 4.10 shows experimental results showing the steady state performances
comparison between the proposed control and the control shown in Fig 4.7 under 100%
non-linear load condition. Both controls are updated at the same control rate equal to the
3.2 kHz PWM switching frequency. The non-linear load applied consists of three single-
phase diode rectifiers with RC load as shown in Fig. 4.2 with small amount of linear load
added to obtain 100% rated power. It can be seen that the proposed control yields output
voltages with significantly lower THD than the PI controllers, which confirms the
arguments of the preceding paragraph.
(a) (b)
Figure 4.8 Steady state performance comparisons under non-liner load (a) using proposed
control (b) PI controllers. Top: three phase load currents. Bottom: Three-phase load
voltages
117
CHAPTER 5
CONTROL OF PARALLEL INVERTERS
5.1 Combined Droop Method and Average Power Control
In this PhD research, a combination of the droop method and the average power
control is proposed for load sharing of paralleled inverters as shown in Fig 5.1. The
average power method is used to overcome the sensitivity of the droop method towards
measurements errors and wiring impedance mismatches. Choosing phase angle (instead
of frequency) as the controlling variable for the real power control has the advantage that
the average power control can be deactivated by setting the input to the integrator to zero
if communication error is detected. This makes the load sharing control to be less
dependent on the existence of the inter-communication signals between units. Another
way of looking at this is that the average power control fine-tunes the droop method to
achieve proper load sharing when measurement errors or other non-idealities exist. The
simulations and experimental works show that proper load sharing at different load
conditions can still be achieved even after the average power is deactivated.
118
P0 θref
P + - m + ∆θ
+ θ
+
m<0
+
Pavg + T mi
z −1
- integrator mi < 0
Q0 Vnom
- + Vmax
Q + + ∆V
n
+
n<0
Qavg + T
z −1
ni
- integrator ni < 0
Figure 5.1 Combined droop and average power methods for load sharing control
Note that in Fig. 5.1, θ ref represents a reference phase angle which each inverter
needs to lock to. When the bypass source is available, the phase angle θ ref can be obtained
using a Phase Locked Loop algorithm that locks both phase frequency of each inverter to
a common source. When the bypass source is not available, no common reference exists
for the inverters to synchronize to. Each inverter in this mode will free-run at its nominal
frequency. In this case, the load sharing phase adjustment will attempt to lock the phase
angle; however some other means must exist to lock frequency of each inverter. A slight
119
different in frequency will cause each inverter to be out of synchronization which in turn
will break the load sharing control above. The solution to this issue will be further
discussed in the next sub section.
Another issue to address is what power quantities should be used for the method
proposed. Most previous works in paralleled three-phase inverters use total three-phase
real and reactive power for this purpose. However, using total power does not guarantee
load sharing of individual phase in the case of unbalanced load or wire impedances. To
answer this question, in this research the load sharing control shall be applied to the
individual DQ axis circuit i.e. the method shall be applied to the real and reactive power
on each D and Q axis. The reasoning for this can be justified if one examines the DQ0
model of the paralleled inverters as shown in Fig. 5.2. The problem of paralleling three-
phase inverters can be broken down into paralleling three-independent single-phase
circuit. Since the 0-component is not controllable and the filter has suppressed its
quantities, the load sharing shall only be accomplished for the D and Q axis single-phase
circuitry.
120
Iload q1
Z out _ q1 Z wire _ q1
+ +
Vload q1
Iload q
-
Iload d 1
Z out _ d 1 Z wire _ d 1
+ +
Vload d 1 Iload d
-
Iload01 Z wire _ 01
Z out _ o1
+
Vload 01
Iload 0
-
Iloadq 2
Z out _ q 2 Z wire _ q 2
+ +
Vload q 2
-
Iload d 2
Z out _ d 2 Z wire _ d 2
+ +
Vload d 2
-
Iload 02
Z out _ o 2 Z wire _ 02
+
Vload 02
Figure 5.2 DQ0 model of paralleled inverters
Applying the proposed load sharing control for the individual D and Q axis, we
obtain the following equations (5.1) to (5.6) for updating the phases and amplitudes of the
D and Q voltages references,
121
Q-Axis:
Phase Angle:
⎧P − Pq if activated
φq (k + 1) = φq (k ) + mi ⋅ ePq ePq = ⎨ q _ avg
⎩ 0 if deactivated
∆θ q (k ) = φq (k ) + m ⋅ (Pq − Pq 0 ) (5.1)
θ q (k ) = θ ref (k ) + ∆θ q (k )
Amplitude:
⎧Q − Qq if activated
υ q (k + 1) = υ q (k ) + ni ⋅ eQq eQq = ⎨ q _ avg
Vmax_ q (k ) = Vnom + υ q (k ) + n ⋅ (Qq − Qq 0 ) (5.2)
Voltage Reference:
Vref _ q (k ) = Vmax_ q (k ) ⋅ sin[θ q (k )] (5.3)
D-Axis:
Phase Angle:
⎧P − Pd if activated
φd (k + 1) = φd (k ) + mi ⋅ ePd ePd = ⎨ q _ avg
∆θ d (k ) = φd (k ) + m ⋅ (Pd − Pd 0 ) (5.4)
θ d (k ) = θ ref (k ) + ∆θ d (k )
Amplitude:
⎧Q − Qd if activated
υ d (k + 1) = υ d (k ) + ni ⋅ eQd eQq = ⎨ d _ avg
Vmax_ d (k ) = Vnom + υ d (k ) + n ⋅ (Qd − Qd 0 ) (5.5)
Voltage Reference:
Vref _ d (k ) = Vmax_ d (k ) ⋅ cos[θ d (k )] (5.6)
122
5.2 Stability Analysis of Combined Droop and Average Control Method
In this section, stability of the paralleled UPS with the combined droop and
average control method described in the previous section will be investigated. Stability
analysis of paralleled UPS with only the frequency and voltage droop method has been
discussed in several prior works [106-108]. In these prior works, small signal analysis
models were developed to study the stability of the paralleled inverters network around
the state of equilibrium. The droop technique analyzed in [106] uses total three-phase
instantaneous active and reactive power, and therefore can not be directly extended to
analyze the proposed control in this research, since in this research the paralleling
problem is viewed as a three separate single-phase circuits (Fig. 5.2). Reference [107]
and [108], on the other hand, provide the analysis for two interconnected single phase
inverters using frequency and voltage droop method. The stability analysis provided in
this section, hence, follows [107] and [108], with the exception that the analysis will be
performed for the phase and voltage droop method combined with the average power
control method. Additionally, the analysis provided here is performed in discrete time
domain, as opposed to the continous time domain as in [107-108].
123
Fig. 5.3 shows an equivalent circuit of two paralleled inverters for one of the dq
phases in Fig. 5.2 with a resistive load and interconnection impedances modeled as
inductors. Due to the high bandwith of the voltage control loop as compared to the
bandwidth of the power dynamics, it is safe to assume the UPS inverters acting as ideal
voltage sources [106]. The variables E1 and E 2 represent the per-unit rms voltage, and
δ 1 and δ 2 power angles of the output voltages of UPS1 and UPS2 respectively. jX 1 and
jX 2 denote the per-unit impedances of the interconnection wires, and R represents the
per unit resistive load impedance.
E1∠δ 1 E2 ∠δ 2
jX 1 jX 2
I1 R I2
Figure 5.3 Two inverters connected to a load
124
The active and reactive power delivered by each UPS can be calculated using
phasor analysis and are given by:
P1 = a1 E1 + b ⋅ E1 E 2 sin(δ 1 − δ 2 ) + cE1 E 2 cos(δ 1 − δ 2 )

2
(5.7.a)
P 2 = a 2 E 2 + b ⋅ E1 E 2 sin (δ 2 − δ 1 ) + cE1 E 2 cos(δ 2 − δ 1 )

2
(5.7.b)
Q1 = d 1 E1 − b ⋅ E1 E 2 cos(δ 1 − δ 2 ) + cE1 E 2 sin(δ 1 − δ 2 )

2
(5.7.c)
Q 2 = d 2 E 2 − b ⋅ E1 E 2 cos(δ 2 − δ 1 ) + cE1 E 2 sin (δ 2 − δ 1 )

2
(5.7.d)
where
a1 = RX 2 D a 2 = RX 1 D
2 2
b = R 2 (X 1 + X 2 ) D c = RX 1 X 2 D
(
d1 = R 2 ( X 1 + X 2 ) + X 1 X 2
2
)D (
d 2 = R 2 (X 1 + X 2 ) + X 1 X 2 D
2
)
D = R 2 (X 1 + X 2 ) + (X 1 X 2 )
2 2
Considering small deviations around the equilibrium point ( δ 1e , δ 2 e , E1e , E 2 e ),
equations (5.7) can be linearized as follows:
⎡ ∆P1 ⎤ ⎡ ∆δ 1 ⎤
⎢ ∆P ⎥ ⎢ ∆δ ⎥
⎢ 2 ⎥ = S ⋅⎢ 2⎥ , S = [sij ], i, j = 1K 4 (5.8)
⎢ ∆Q1 ⎥ ⎢ ∆E1 ⎥
⎢ ⎥ ⎢ ⎥
⎣ ∆Q2 ⎦ ⎣ ∆E 2 ⎦
where each sij is given as:
s11 = bE1e E2 e cos(δ 1e − δ 2 e ) − cE1e E 2 e sin(δ 1e − δ 2 e )
s12 = −bE1e E 2 e cos(δ 1e − δ 2 e ) + cE1e E 2 e sin(δ 1e − δ 2 e ) = − s11
s13 = 2a1 E1e + b ⋅ E 2 e sin(δ 1e − δ 2 e ) + cE 2 e cos(δ 1e − δ 2 e )
s14 = b ⋅ E1e sin(δ 1e − δ 2 e ) + cE1e cos(δ 1e − δ 2 e )
125
s21 = −bE1e E 2 e cos(δ 2 e − δ 1e ) + cE1e E 2 e sin(δ 2 e − δ 1e )
s 22 = bE1e E 2 e cos(δ 2 e − δ 1e ) − cE1e E 2 e sin(δ 2 e − δ 1e )
s23 = b ⋅ E 2 e sin(δ 2 e − δ 1e ) + cE 2 e cos(δ 2 e − δ 1e )
s 24 = 2a 2 E 2 e + b ⋅ E1e sin(δ 2 e − δ 1e ) + cE1e cos(δ 2 e − δ 1e )
s31 = b ⋅ E1e E 2 e sin(δ 1e − δ 2 e ) + cE1e E 2 e cos(δ 1e − δ 2 e )
s32 = −b ⋅ E1e E 2 e sin(δ 1e − δ 2 e ) − cE1e E 2 e cos(δ 1e − δ 2 e )
s33 = 2d1 E1e − b ⋅ E 2 e cos(δ 1e − δ 2 e ) + cE 2 e sin(δ 1e − δ 2 e )
s34 = −b ⋅ E1e cos(δ 1e − δ 2 e ) + cE1e sin(δ 1e − δ 2 e )
s41 = −b ⋅ E1e E 2 e sin(δ 2 e − δ 1e ) − cE1e E 2 e cos(δ 2 e − δ 1e )
s42 = b ⋅ E1e E2 e sin(δ 2 e − δ 1e ) + cE1e E2 e cos(δ 2 e − δ 1e )
s 43 = −b ⋅ E 2 e cos(δ 2 e − δ 1e ) + cE 2 e sin(δ 2 e − δ 1e )
s 44 = 2d 2 E 2 e − b ⋅ E1e cos(δ 2 e − δ 1e ) + cE1e sin(δ 2 e − δ 1e )
In this research, each of the active and reactive powers is computed once every
one line cycle and digital low pass filtering is applied to each power computation for the
purpose of removing measurement noise. The digital filters used are given in (5.9)
p1m (k + 1) = (1 − γ ) p1m (k ) + γP1 (k ) (5.9.a)
p2 m (k + 1) = (1 − γ ) p2 m (k ) + γP2 (k ) (5.9.b)
q1m (k + 1) = (1 − γ )q1m (k ) + γQ1 (k ) (5.9.c)
q2 m (k + 1) = (1 − γ )q2 m (k ) + γQ2 (k ) (5.9.d)
126
Using the filtered power quantities in (5.9), the combined average power control
and droop method from the previous section can be written in per unit notation as
follows:
δ 1 (k ) = φ1 (k ) + m ⋅ p1m (5.10.a)
δ 2 (k ) = φ2 (k ) + m ⋅ p2 m (5.10.b)
E1 (k ) = 1 + υ1 (k ) + n ⋅q1m (5.10.c)
E 2 (k ) = 1 + υ 2 (k ) + n ⋅q 2 m (5.10.d)
with the integrator states updated as in (5.11) .
mi
φ1 (k + 1) = φ1 (k ) + ⋅ ( p1m − p 2 m ) (5.11.a)
2
mi
φ2 (k + 1) = φ2 (k ) + ⋅ ( p 2 m − p1m ) (5.11.b)
2
ni
υ1 (k + 1) = υ1 (k ) + (q1m − q2 m ) (5.11.c)
2
ni
υ 2 (k + 1) = υ 2 (k ) + (q2 m − q1m ) (5.11.d)
2
Using small signal analysis (5.9), (5.10), and (5.11) can be linearized as shown in
(5.12), (5.13), and (5,14) respectively.
Linearized power filter
∆p1m (k + 1) = (1 − γ )∆p1m (k ) + γ∆P1 (k ) (5.12.a)
∆p2 m (k + 1) = (1 − γ )∆p2 m (k ) + γ∆P2 (k ) (5.12.b)
∆q1m (k + 1) = (1 − γ )∆q1m (k ) + γ∆Q1 (k ) (5.12.c)
∆q2 m (k + 1) = (1 − γ )∆q2 m (k ) + γ∆Q2 (k ) (5.12.d)
127
Linearized Combined Average and Droop Control
∆δ 1 (k ) = ∆φ1 (k ) + m ⋅ ∆p1m (5.13.a)
∆δ 2 (k ) = ∆φ2 (k ) + m ⋅ ∆p2 m (5.13.b)
∆E1 (k ) = ∆υ1 (k ) + n ⋅ ∆q1m (5.13.c)
∆E 2 (k ) = ∆υ 2 (k ) + n ⋅ ∆q 2 m (5.13.d)
Linearized Integrator Equations
mi
∆φ1 (k + 1) = ∆φ1 (k ) + ⋅ (∆p1m − ∆p 2 m ) (5.14.a)
2
mi
∆φ2 (k + 1) = ∆φ2 (k ) + ⋅ (∆p 2 m − ∆p1m ) (5.14.b)
2
ni
∆υ1 (k + 1) = ∆υ1 (k ) + (∆q1m − ∆q2 m ) (5.14.c)
2
ni
∆υ 2 (k + 1) = ∆υ 2 (k ) + (∆q2 m − ∆q1m ) (5.14.d)
2
Substituting (5.13) into the linearized power equations (5.8), we obtain linearized
equations in terms of the integrator states and power filter states perturbations as:
⎡ ∆P1 ⎤ ⎡ ∆φ1 ⎤ ⎡ m∆p1m ⎤

⎢ ∆P ⎥ ⎢ ∆φ ⎥ ⎢m∆p ⎥
⎢ 2 ⎥ = S ⋅⎢ 2 ⎥ + S ⋅⎢ 2m ⎥
(5.15)
⎢ ∆Q1 ⎥ ⎢ ∆υ1 ⎥ ⎢ n∆q1m ⎥
⎢ ⎥ ⎢ ⎥ ⎢ ⎥
⎣ ∆Q2 ⎦ ⎣ ∆υ 2 ⎦ ⎣ n∆q2 m ⎦
If we define the following states vector
∆x = [∆p1m ∆p2 m ∆q1m ∆q2 m ∆φ1 ∆φ2 ∆υ1 ∆υ 2 ]

T
then from (5.12), (5.14), and (5.11) we can write:
∆x (k + 1) = A∆ ⋅ ∆x (k ) (5.16)
128
where:
A∆ =
⎡(1 − γ ) + mγs11 mγs12 nγs13 nγs14 γs11 γs12 γs13 γs14 ⎤
⎢ mγs21 (1 − γ ) + mγs22 nγs 23 nγs24 γs21 γs22 γs23 γs24 ⎥
⎢ ⎥
⎢ mγs31 mγs32 (1 − γ ) + nγs33 nγs34 γs31 γs32 γs33 γs34 ⎥
⎢
⎢ mγs41 mγs 42 nγs 43 (1 − γ ) + nγs44 γs41 γs42 γs43 γs44 ⎥⎥
⎢ mi
− i
m
0 0 1 0 0 0 ⎥
⎢ 2 2 ⎥
⎢ m mi ⎥
⎢ − i 0 0 0 1 0 0 ⎥
⎢ 2 2 ⎥
⎢ ni ni
0 0 − 0 0 1 0 ⎥
⎢ 2 2 ⎥
⎢ n ni ⎥
⎢⎣ 0 0 − i 0 0 0 1 ⎥
2 2 ⎦
Equation (5.16) describes the system dynamics around the equilibrium point. The
eigenvalues of matrix A∆ can be used to determine the stability of the system around the
state of equilibrium and the type of dynamic response expected. For example, assume the
following system parameters: X 1 = 0.001 , X 2 = 0.002 , and R = 1.0 . The filter time
constant is chosen to be γ = 0.5 . Let us consider two cases of droop coeffiecients and
integrator gains as follows:
Case 1: m = n = −0.001 and mi = ni = −0.0003
Case 2: m = n = −0.001 and mi = ni = −0.0008
Case 3: m = n = −0.005 and mi = ni = −0.0008
The state of equilibrium for each case needs to be calculated using power flow analysis.
However, since the amplitude and phase adjustments made by each UPS are very small
compared to the nominal value of the voltages and the phases are always initially in
129
synchronization with respect to a reference voltage, we can choose ( δ 1e , δ 2 e , E1e ,
E 2 e )=(0, 0, 1,1) for calculation of each terms in matrix S in (5.8). The eigenvalues of
matrix A∆ for each case are obtained as follow:
Case 1:
0.3118, 0.3122, 0.8547, 0.8546, 0.5000, 0.5000, 1.0000, 1.0000
Case 2:
0.3120, 0.8546, 0.5833 ± 0.3051i, 0.5000, 0.5000, 1.0000, 1.0000
Case 3:
-1.0369, -1.0344, 0.8690, 0.8690, 0.5000, 0.5000, 1.0000, 1.0000
In Case 1 and Case 2, all the eigenvalues are located within the unit circle, so both
systems are stable. In case 3, two of the eigenvalues lie outside of the unit circle so the
system is unstable. In Case 1, all eigenvalues are real, and therefore the system has a
damped response. Case 2 presents eigenvalues with imaginary components so the system
response can be expected to be oscillatory. To verify these findings, simulations of the
circuit of Fig. 5.2 with the proposed control have been performed using Simulink Power
System Blockset. Figure 5.4 (a), (b), and (c) show the system responses ( P1 , P2 , Q1 , and
Q2 ) for Case 1, Case 2, and Case 3, respectively. It can be seen that the small signal
stability analysis accurately predicts the nature of stability for each case.
130
(a) (b)
(c)
Figure 5.4 System responses (a) Case 1, (b) Case 2 (c) Case 3
131
5.3 Generation of the Reference Angle θ ref
As explained in the previous section, when the bypass source is available the
reference angle θ ref can be obtained using a PLL that locks the phase and frequency of
each inverter to those of the bypass source. Fig. 5.5 shows a single-phase digital PLL that
can be used to achieve this purpose. At each sampling time, the PLL computes the
average over one reference cycle ( Tref = 2π ωref ) of the product of the bypass voltage
Vbyp with the cosine of the reference angle θ ref . A PI controller is then used to force this
average to zero. Using the relation sin α ⋅ cos β = 0.5 sin(α + β ) + 0.5 sin(α − β ) , it can be
easily seen that when the one cycle average becomes zero, the reference angle θ ref is
phase and frequency locked to the bypass voltage.
t +Tref
∫ [V ⋅ cos(θ ref )] dt
1
⋅
ωnom
byp
Vbyp ⋅ cos(θ ref )

Tref t
Vbyp θ ref
T
ωref z −1
cos( )
Figure 5.5 Generation of reference angle for the case when bypass source is available
132
When the bypass source is not available, the reference θ ref needs to be updated
differently than that of Fig. 5.5. In this research, a method is proposed to force the
frequency of each inverter to stay lock together during free-running operation. This
method is shown in Fig. 5.6. The idea of this method originates from the fact that if the
frequencies of the inverters are not the same, then the load sharing angle adjustment ∆θ
in Fig. 5.1 will continue to ramp up or down at a rate proportional to frequency errors
between the two sources. To prevent this, the inverter frequency needs to be adjusted to
force the rate of change of the angle adjustment to zero. In the method shown in Fig. 5.6,
the rate of change of the angle adjustment is forced to zero through an integrator that
outputs the frequency adjustment from the nominal value. Note that since there is only
one θ ref for both DQ axis, the rate of change of ∆θ is calculated from the average rate of
change of the D and Q phase angle adjustments.
ωnom
∆θ (k )
δω ωref θ ref
T T
kf
z −1 z −1
∆θ (k − 1)
Figure 5.6 Generation of reference angle for the case when bypass source is available
133
5.4 Harmonic Sharing
The proposed load sharing method above does not guarantee the harmonic
components of the load current to share, since it affects only the phase and magnitude of
the fundamental output voltage. A means must exist to affect the harmonic components
of the load currents based on its harmonic contents. The individual control of the
harmonics proposed for the single PWM control in this PhD research, presents a clear
advantage for achieving this purpose. The control gains affecting the harmonic in the
voltage control can be individually adjusted based on the harmonic content of the load
current at that harmonic frequency. For example, the pole frequencies of the harmonic
compensator can be shifted based on the harmonic content of the load current at those
frequencies. This is illustrated in Fig. 5.7, where I3, I5, and I7 denote the harmonic
contents of the load currents at third, fifth, and seventh harmonics respectively, and ω 3′ ,
ω 5′ , and ω 7′ are the third, fifth, and seventh harmonic frequencies of the harmonic
compensator poles. Unlike previous works, the harmonic drooping method proposed has
the advantage that it does not degrade the fundamental component properties; it only
affects the individual harmonic when it exists.
134
ω3
I3 +
∆ω 3
m3 + ω 3′
ω5
I5 +
∆ω 5
m5 + ω5′
ω7
I7 +
∆ω 5
m7 + ω7′
m3 < 0 m5 < 0 m7 < 0
Figure 5.7 Harmonic Drooping thru the harmonics compensators pole shifting
r r r
If η3 , η5 , and η7 denotes the states of the harmonic servo compensators for 3rd, 5th
and 7th, then the harmonics servo-compensator for the single unit PWM control are
modified as follows:
r r
η&3 = Ac 3 (ω3′ )η3 + Bc eVqd
r r
η&5 = Ac 5 (ω5′ )η3 + Bc eVqd (5.17)
r r
η&7 = Ac 7 (ω7′ )η 7 + Bc eVqd
135
where
r r r
eVqd = Vref qd − Vload qd
r r
⎛ 02 x 2 I 2x2 ⎞
Aci (ωi′ ) = ⎜⎜ r r ⎟ , i = 3,5,7
⎝ − ωi′ I 2 x 2 0 2 x 2 ⎟⎠
2
r r
(
Bc = 0 2 x 2 I 2x2 )
T
i = 1,2, K n
The ω3′ , ω5′ , and ω7′ are computed from the harmonic droop in Fig. 5.7 and are given by:
ω3′ = ω3 + m3 I 3 , ω3 = 2π ⋅ 3 ⋅ 60
ω5′ = ω5 + m5 I 5 , ω5 = 2π ⋅ 5 ⋅ 60 (5.18)
ω7′ = ω7 + m7 I 7 , ω7 = 2π ⋅ 7 ⋅ 60
where I3, I5, and I7 denote the harmonic contents of the load currents at third, fifth, and
seventh harmonics respectively. Note that each of the blocks

r r r
η&i = Aci (ωi′ )ηi + Bci eVqd represents a state space implementation of the continuous
transfer function: 1 s 2 + ωi′ ( 2

) for each of the qd-axis voltages errors. As in the single unit
inverter control, the servo compensators (5.17) can be transformed to a discrete time
system to yield:
r r r
ηi (k + 1) = Aci* (ωi′ )ηi ( k ) + Bc*eVqd ( k ) i = 3,5,7 , (5.19)
r r r
eVqd (k ) = Vref qd ( k ) − Vload qd ( k )
where:
Bc* = ∫0 S e A1⋅(TS −τ ) Bc dτ
T
Ac* = exp( Ac ⋅ TS )
136
The modified robust servo mechanism output voltage control with harmonic
drooping included is shown in Fig. 5.8.
r *
I cmdqd (k ) > I max
r r
Vref qd (k ) eVqd Discrete implementation of
states η1
r
1 r
+ ⋅ I 2×2
s 2 + ω12
r
Vloadqd (k ) Current limit
Discrete implementation of r r r
1 r states η3 K1 *
I cmdqd
Equation (4.17)
I cmdqd
⋅ I 2×2
I3 H ω3′ s 2 + ω3′
2
A Servo
R Compensator
M Gains
O Discrete implementation of r
r η5 r
⎡ Vinvqd (k ) ⎤
N 1 states
I5 ⋅ I 2×2
I
ω5′ s 2 + ω5′ K2 ⎢ r ⎥
⎢ rI invqd (k ) ⎥
2
C
D
Stabilizing compensator ⎢ Vload (k ) ⎥
R
gains ⎢ r qd ⎥
I7 Discrete implementation of r ⎢ I loadqd (k ) ⎥
O states η7
r ⎢r ⎥
⎣⎢Vpwmqd (k − 1)⎦⎥
O 1
P ω7′ 2 ⋅ I 2×2
s 2 + ω7′
Figure 5.8 Output voltages controller using robust servomechanism controller with
harmonic drooping
137
CHAPTER 6
SIMULATION AND EXPERIMENTAL STUDIES OF PARALLEL INVERTERS
CONTROL
6.1 Simulation System Implementation
The proposed load sharing control described in the previous chapter will be tested
in a simulation environment that represents the experimental test-bed. For testing the
effectiveness of the proposed load sharing control, it is not necessary to simulate the
switching devices in the three-phase IGBT PWM inverter since the voltages and currents
at the point where the two UPS are being paralleled are not affected by the high
frequency switching of the PWM inverter. Therefore, in order to reduce the computing
time required to simulate the entire system, the three-phase IGBT PWM inverter will be
modeled as a voltage controlled source with delay of half the PWM cycle time ( Ts / 2 ).
This is a valid assumption assuming that the DC bus voltage can be maintained at
sufficient regulation and a proper space vector PWM switching technique is used for
implementing the PWM voltage command [126].
Simulations will be performed using Matlab/Simulink with the help of
SimPowerSystem Blocksets from Mathworks. The SimPowerSystem Toolbox allows
138
simulation of power electronic circuit devices and components in Simulink, requiring
only interconnection of library components models for building the circuits for
simulations.
The following sections discuss the implementation of the simulation system.
6.1.1 Main Diagram
The main Simulink block diagram for the system is shown in Fig. 6.1. The two
PWM inverter systems are implemented by the blocks PWM Inverter 1 and PWM
Inverter 2. A 3-phase Load Bank block implements different load conditions which are
selectable using the Level input as follows:
1: 2 x 4 kW balanced Resistive Load (can be modified for arbitrary parallel RLC load)
2: 2 x 5 kVA 0.8 pf lagging balanced load (can be modified for arbitrary parallel RLC
load)
3: No Load (=3 Watt resistive)
4: Unbalanced Load (can be modified for arbitrary unbalanced parallel RLC load)
5: Non-linear Load, consists of 3 single-phase diode rectifier, with approximately 5kVA
loading.
139
Figure 6.1 Simulink main diagram of the system
The wiring between the two PWM inverters are modeled by the impedances
ZwA1, ZwB1, ZwC1, ZwA2, ZwB2, and ZwC2 as shown in Fig. 6.1. The values of these
impedances can be changed to model different cases of wiring impedances mismatches.
A global flag COMM_OK in the main diagram (Fig. 6.1) is used for indication of the
condition of the communication link of between the two units. COMM_OK=1 indicates
that the communication link is ok and therefore the two units can use the average power
140
for the load sharing control, COMM_OK=0 indicates otherwise. The powers of each unit
are communicated using the labels PQqd1 and PQqd2 each of which consists of
multiplexed signals of Pq, Qq, Pd, and Qd of inverter 1 and 2 respectively.
The control flag free_run=1 tells both inverter to run in free-running mode, while
free_run=0 tells them to synchronize to the bypass voltage modeled as a sine wave
source VbypAN in Fig. 6.1.
The labels PQ1 and PQ2 consist of the per-phase real and reactive powers of each
inverter in ABC frame (Pa, Qa, Pb, Qb, Pc, Qc). The abc load currents of each inverter
are available as Iload1 and Iload2, and the abc load voltages and currents are given by
Vload and Iload respectively.
6.1.2 PWM Inverter Block
The PWM Inverter 1 and PWM Inverter 2 in the main diagram both contain the
block diagrams shown in Fig. 6.2 The power circuitry consisting of the Inverter, LC
Filter, Transformer, and Output Capacitor subsystems are implemented using the
SimPower System Blockset components.
141
Figure 6.2 PWM Inverter block
The LC Filter, Transformer, and Output Capacitor subsystems consist of standard
SimPowerSystem library blocks and their block diagrams are given in Fig. 6.3(a), 6.3(b),
and 6.3(c), respectively. The values of the inductors and capacitors are given by Matlab
workspace variables Linv, Cinv, and Cout initialized by the control5kva.m file. The
inverter subsystem consists of three ideal controlled voltage sources with half PWM
period delays as shown in Fig. 6.3.d.
142
a) LC Filter b) Transformer
c) Output Capacitors d) Inverter
Figure 6.3 Power circuitries
143
The Transformer is built from a SimpowerSystem standard Delta/Y linear
transformer library with the following nominal parameters:
[Three-phase rated power (VA) Frequency (Hz)]=[ 5e3 60]
Winding 1 (Delta):[Ph-Ph Voltage (Vrms) R(pu) X(pu)] = [ 240 0.015 0.015]
Winding 2 (Wye):[Ph-Ph Voltage (Vrms) R(pu) X(pu)] = [ 208 0.015 0.015]
The inverter inductor filter currents (Iinv), inverter capacitor filter voltages (Vinv),
load voltages (Vload), and load currents (Iload) are measured and multiplexed along with
the bypass voltage into the signal label ACT_SIGNALS. These signals are multiplied by a
constant array Measurement Error Constants to model measurement errors that exist in
the system. For example the Measurement Error Constants can be initialized as: [0.99
1.01 0.99, 1.01 0.99 0.99, 0.999 1.001 0.999, 1.01 0.99 0.99, 1] which represents -1%,
+1%, -1% errors in the inverter phases currents measurements, +1%, -1%, -1% in the
capacitor voltages, -0.1%, +0.1%, -0.1% in the load voltages, and no error in the bypass
voltage measurements.
The measured voltages and current affected by the measurement errors are then
fed through a one-sampling-time (Tsamp=1/60/90) Zero-Order Hold block into the DSP
Output block that implements the control by a digital signal processor. The
communicated power quantities from the other unit are also fed to this block through the
multiplexed signal labeled PQother.
144
6.1.3 DSP Output
Fig. 6.4 shows the implementation of the DSP Output block. The block performs
the load voltages and inverter current control as well as the load sharing control for
parallel operation. The block functionalities are broken down in to four subsystems as
shown in Fig. 6.4.
The DQ Transformation & States Calculations performs the necessary ABC to
DQ stationary reference frame as well as necessary states variables calculation for
control. Implementation of this block is shown in Fig. 6.5.
The DQ Power Calculation subsystem calculates the output real and reactive
powers of each individual D and Q axis from the DQ load voltages and currents. The first
output of this block is a multiplexed signal labeled PQqd which consists of the power
quantities Pq, Qq, Pd, and Qd. The block also generates the 3rd, 5th, and 7th harmonic
currents for each DQ axis which are multiplexed into signals labeled Iq_harm and
Id_harm. Fig. 6.6 shows the implementation of this subsystem. The power quantities are
calculated using PSB library block Discrete Active & Reactive Power with sampling time
equals to Tsamp=1/60/90 and fundamental frequency of 60Hz. The harmonic currents are
computed using the PSB library block Discrete Fourier which gives a discrete Fourier
component of the input signal at a specified harmonic of the fundamental frequency of
60Hz.
The Load Sharing Control, Voltage Controller and Current Controller
subsystems will be discussed in the following sections.
145
Figure 6.4 DSP Output block diagrams
146
Figure 6.5 DQ Transformations & States Calculations
147
Figure 6.6 DQ Power Calculation
148
6.1.4 Load Sharing Control
Fig. 6.7 shows the implementation of the Load Sharing Control block. The real
power sharing of the D and Q axis (equations 5.1 and 5.4) are implemented by the P
Sharing block shown in Fig. 6.8 (a), while the reactive power sharing control (Equations
5.2 and 5.5) are implemented in the Q sharing block Fig. 6.8 (b). The Reference Angle
Generation block generates the reference angle θ ref as discussed in Chapter 5. The two
blocks at the bottom of the diagrams computes the sine-waves references for the Q and D
axis based on the reference angle θ ref , phases and amplitude adjustments for the load
sharing control.
Figure 6.7 Load Sharing Control Block Implementation
149
(a) P Sharing Block (a) Q Sharing Block
Figure 6.8 P and Q Sharing Blocks
150
Fig. 6.9 shows the implementations of P (Fig. 6.9 a) and Q (Fig. 6.9 b) sharing
controls for each D and Q axis in Fig. 6.8. The diagrams implements the equations (5.1)
or (5.4) for P sharing control and (5.2) or (5.5) for Q sharing controls. The signal
COMM_OK defined in the Main Diagram is used to switch off the input to the
integrators. When COMM_OK=1 the power errors are used as the inputs to the
integrators, when COMM_OK=0 constants 0 are used instead. The sampling time of the
discrete time integrators are set at one line cycle period (1/60 sec). The control gains for
these blocks are initialized by Mask Subsystems of the P Sharing and Q Sharing blocks in
the Load Sharing Control block as shown in Fig. 6.10.
151
(a)Pq or Pd Sharing Control
(b) Qq or Qd Sharing Control
Figure 6.9 Individual axis P and Q Sharing Implementation
152
Figure 6.10 Masked-subsystems of P-Sharing and Q-Sharing for initializing load sharing
control gains
The Reference Angle Generation block is implemented as shown in Fig. 6.11. The
top part implements the frequency locking mechanism of Fig. 5.5 for free running
operation, while the bottom part implements the phase-lock loop in Fig. 5.6. The signal
label free_run defined in the Main Diagram selects the input to the Discrete Time
Integrator4 which generates the reference angle. When free_run=1, the frequency
locking frequency output is selected, when free_run=0 the frequency is obtained from the
PLL output. The implementation of reference angle generation in Fig. 18 also ensures
that the continuity of the integrators states in the two mechanisms. During free_run=1,
the integrator in the PI controller of the PLL is held reset, while during free_run=0 the
Discrete Time Integrator5 is held reset. An initial value equal to the output frequency of
the other mechanism is given for each integrator when the reset signal changes from 1 to
0. These values are denoted by the labels df1 and df2 in Fig. 6.11
153
Figure 6.11 Reference Angle Generation implementation
6.1.5 Voltage Controller and Current Controller
The harmonic robust servo mechanism voltage control and sliding mode control
developed in this PhD research will be used for the control of each inverter.
Modifications to the harmonic servo compensators are however necessary in order to
implement the proposed harmonic drooping technique. This modification is included in
the M-File for calculating the servo and sliding mode control gains and its listing is
provided in Appendix A. This m-file needs to be executed prior to running the Simulink
simulation.
Implementation of the Robust Servomechanism Perfect (RSP) voltage controller
is shown in Fig. 6.12. Control for each axis Q and D are implemented as Vq control and
154
Vd control blocks respectively. Each block has df3, df5, and df7 for harmonic drooping
control which are obtained from multiplying the Iq_harm and Id_harm signals calculated
by the DQ Power Calculation (see Fig. 13).
Figure 6.12 Voltage Controller Implementation
Fig. 6.13 implements the Vq (Vd) control block. The Var Freq Harmonic Control
block implement equation (5.19) for harmonic servo compensator with drooping
included. In order to implement the harmonic drooping, the coefficients for matrices
Aci* (ωi′ ) and Bc* in equation (9) have to be computed for all possible values of ωi′ . It can
155
be shown that for fundamental frequency in the small range around 60 Hz, each
coeffiecient in the matrices Aci* (ωi′ ) and Bc* can be approximated by a linear function of
the frequency as in:
Aci* ( f )i , j ≈ pA1i , j + pA2 i , j ⋅ ( f − 60) i, j = 1..2 (9.a)
Bci* ( f )i , j ≈ pB1i , j + pB 2i , j ⋅ ( f − 60) i, j = 1..2 (9.b)
The following Matlab code (included in the Matlab script in Appendix A) can be used to
calculate the coefficients of matrices for Aci* (ωi′) and Bc* based on the above method. Fig.
6.14 shows the implementation of the Var Freq Harmonic Control block using this
method.
harmonic=[1 3 5 7];
Bh_star=[0;1];
for h=1:length(harmonic) % iterate through harmonics 1, 3, 5, 7
i=1;
for f=59.0:0.02:61 % for each harmonic compute the A and B matrix in the range
w=2*pi*f*harmonic(h);
Ch_star=[0 1; % define the analog compensator matrix
-w^2 0];
csysc=ss(Ch_star,Bh_star,eye(2),0);
[csysbc,T]=ssbal(csysc); % perform balanced realization
csysd=c2d(csysbc,Tsamp,'zoh'); % discretize the compensator
[Acon_dx,Bcon_dx,Ccon_dx,Dcon_dx]=ssdata(csysd);
A11(i)=Acon_dx(1,1); % store each coefficient in an array for polyfit
A12(i)=Acon_dx(1,2);
B1(i)=Bcon_dx(1)*300;
B2(i)=Bcon_dx(2)*300;
i=i+1;
end
f=59.0:0.02:61;
pA11{h} = polyfit(f,A11,1); % find the linear fit of each coefficient
pA12{h} = polyfit(f,A12,1);
pB1{h}=polyfit(f,B1,1);
pA11{h}(2)=pA11{h}(2)+pA11{h}(1)*60; % shift the input at 60 Hz
pA12{h}(2)=pA12{h}(2)+pA12{h}(1)*60;
pA21{h}(2)=pA21{h}(2)+pA21{h}(1)*60;
pA22{h}(2)=pA22{h}(2)+pA22{h}(1)*60;
pB1{h}(2)=pB1{h}(2)+pB1{h}(1)*60;
pB2{h}(2)=pB2{h}(2)+pB2{h}(1)*60;
end
156
Figure 6.13 Vq (Vd) Control Implementation
157
(a) Var Freq Harmonic Control
(b) A matrix (b) B matrix
Figure 6.14 Variable Frequency Harmonic Control Implementation
158
The current controller implementation is shown in Fig. 6.15. The control gains are
initialized by the Matlab M-file given in Appendix A.
Figure 6.15 Sliding Mode Current Controller Implementation
159
6.2 Simulations Results
6.2.1 Simulations Conditions
To verify the effectiveness of the proposed load sharing control algorithm,
hypothetical components mismatches among the units will be assumed based on the
worst case tolerances of the components used. It is assumed that the magnetic
components all have ± 10% tolerance while capacitors have ± 6% tolerance. The
mismatches are introduced among the units to create worst case mismatches, including
unbalanced effect among phases within one unit. Table 6.1 shows the assumed
components mismatches in Unit 1 and Unit 2 used for simulations.
Unit 1 Unit2
LinvA +10% -10%
LinvB +10% -10%
LinvC -10% +10%
CinvAB -6% +6%
CinvBC -6% +6%
CinvCA +6% -6%
CoutAB -6% +6%
CoutBC -6% +6%
CoutCA +6% -6%
Xfmr Leakage Primary -10% +10%
Xfmr Leakage Secondary -10% +10%
ZwA 5.0+j5.0 mOhm 2.0+j2.0 mOhm
ZwB 4.8+j4.8 mOhm 2.2+j2.2 mOhm
ZwC 5.2+j5.2 mOhm 1.8+j1.8 mOhm
Table 6.1 Components Mismatches
160
Assuming a ± 0.1% measurement error in each of the signals used by the control
implementation, the following measurement errors constants have been used for the
simulations (see section 6.1.2 for definition of the Measurement Error Constants)
Measurement Errors on Unit 1:
[0.999 1.001 0.999 , 1.001 0.999 0.999 , 1.001 1.001 0.999 , 1.001 0.999 0.999 , 1]
Measurement Errors on Unit 2:
[1.001 0.999 1.001 , 0.999 1.001 1.001 , 0.999 0.999 1.001 , 0.999 1.001 1.001 , 1]
The control gains for the load sharing have been selected as follows. Note that the load
sharing control in this simulation is not implemented in per-unit values.
P Sharing Control:
Kdroop=20e-6 Ki=20e-6 P0=0.5 x 5e3 x 0.8 /3
Q Sharing Control:
Kdroop=10e-4 Ki=20e-4 Q0=0.5 x 5e3 x 0.6 /3
These gains selections give approximately 1 degree span of phase adjustment from no-
load to full load (4 kW= 5 x 0.8) and less than 1V span of amplitude voltage adjustment
for zero reactive power to full (5 x 0.6 kVAR = 3 KVAR). The offsets P0 and Q0 shift
the droop curve halfway in between no-load and full load. This cuts the total phase and
amplitude into half of the overall span for the range of operation from no-load to full
load. Clearly, the selection of the phase control gains above still ensures proper phase
synchronization for bypass operation. The amplitude adjustment is also considerably less
161
than 1% of the nominal voltages amplitude ( 120 2V = 169.7V ) , still ensuring good
voltages regulations from no-load to full load condition.
The harmonic droop gains used in simulations are:
Harmonic Droop Gains= [ 0.02 0.02 0.02]
Proportional and Integral Gains for the PI controller in the Phase Lock Loop:
[Kp Ki]=[18 60]
Frequency locking integral gain: 100
6.2.2 Steady State Load Sharing Performance
In the following simulations steady state load sharing performance of the
proposed control are investigated for different linear and non-linear loads. To obtain the
results, the corresponding load was selected and configured in the Load Bank block and
the simulations were run for 5 seconds, at the end of which the results were collected.
The global flags free_run and COMM_OK are both set to 1, and the gains of the free
running mode frequency locking are also set to 0, so it was assumed that both units were
initially locked in phase and frequency.
Table 6.2, 6.3, and 6.4 summarizes the active and reactive power of each inverter
for balanced linear load with resistive, balanced inductive 0.8 pf, and capacitive 0.9 pf,
with the corresponding steady state load currents shown in Fig. 6.16, 6.17, and 6.18
respectively. It can be seen that for each case the load is shared by the inverters within
1% accuracy.
162
Table 6.5 sunmarizes the result for linear single-phase load, with the load current
waveform in Fig. 6.19. For this case the load power is shared by each inverter within
approximately 3%, which is slightly worst than in the balanced load cases. This can be
expected since the 0-component of the load current flowing due to the unbalanced load
can not be effectively controlled by each inverter
Table 6.6 and Fig. 6.20 show the simulation results for balanced harmonic load. It
can be seen that the load power is shared by the inverters to within less than 1%. Also
from Fig. 6.20 it can be seen that the harmonic load current is shared very well by each
inverter, verifying the effectiveness of the proposed harmonic drooping technique. For a
comparison, Fig. 6.21 shows a result of the simulation when the harmonic drooping
mechanism is disabled. It can be seen in this case the load current is not shared by each
inverter as well as in Fig. 6.20.
163
Unit 1 Unit 2 % Difference
from Average
Pa (watt) 1338.12 1339.5 0.11%
Pb (watt) 1340.08 1338.30 0.13%
Pc (watt) 1338.76 1339.53 0.06%
Ptot (watt) 4017.9 4017.3 0.01%
Qa (var) -5.76 -4.25 N/A
Qb (var) -5.60 -2.00 N/A
Qc (var) -1.26 -6.35 N/A
Qtot (var) -12.62 -12.6 N/A
Load Volt Van=120.32 Vbn=120.31 Vcn=120.31
(V LN rms)
Table 6.2 Steady state results: Resistive Balanced Load (2 x 0.8 x 5.0 kW= 8.0 kW)
Figure 6.16 Output Currents of Unit 1 and Unit 2 under linear balanced resistive load
164
from Average
Pa (watt) 1322.54 1323.50 0.07%
Pb (watt) 1325.08 1321.72 0.25%
Pc (watt) 1322.11 1324.61 0.19%
Ptot (watt) 3969.7 3969.8 0.01%
Qa (var) 984.86 988.31 0.35%
Qb (var) 987.31 988.18 0.09%
Qc (var) 989.87 985.57 0.44%
Qtot (var) 2962.0 2962.1 0.01%
(V LN rms)
Table 6.3 Steady state results: 0.8 lagging Balanced Load (2 x 5kVA 0.8 pf lag)
Figure 6.17 Output Currents of Unit 1 and Unit 2 under 0.8 lagging balanced load
165
from Average
Pa (watt) 1518.81 1520.79 0.13%
Pb (watt) 1520.69 1519.68 0.07%
Pc (watt) 1520.38 1519.89 0.03%
Ptot (watt) 4559.9 4560.4 0.01%
Qa (var) -740.25 -740.17 0.01%
Qb (var) -741.95 -736.00 0.81%
Qc (var) -735.95 -741.96 0.44%
Qtot (var) 2218.2 2218.1 0.01%
(V LN rms)
Table 6.4 Steady state results: 0.9 leading Balanced Load (2 x 5kVA 0.9 pf lead)
Figure 6.18 Output Currents of Unit 1 and Unit 2 under 0.9 lagging balanced load
166
from Average
Pa (watt) 1343.65 1293.78 3.78%
Pb (watt) -12.74 14.21 0.07%
Pc (watt) -13.55 15.03 0.03%
Ptot (watt) 1317.40 1322.2 0.367%
Qa (var) -5.83 -4.00 N/A
Qb (var) -29.69 18.73 N/A
Qc (var) 18.27 -29.26 N/A
Qtot (var) -17.25 -14.53 N/A
(V LN rms)
Table 6.5 Steady state results: Single-phase Loaded (2 x 4.0 kW/3=2.666 kW on phase A
Figure 6.19 Output Currents of Unit 1 and Unit 2 under single-phase resistive load
167
from Average
Pa (watt) 1313.00 1314.03 0.08%
Pb (watt) 1315.53 1312.56 0.23%
Pc (watt) 1312.90 1315.02 0.16%
Ptot (watt) 3941.4 3941.6 0.01%
Qa (var) 772.35 775.40 0.39%
Qb (var) 774.05 775.50 0.19%
Qc (var) 777.12 772.63 0.58%
Qtot (var) 2323.5 2.3235 0.00%
(V LN rms) %THD = 2.77, 2.84, 2.84
Table 6.6 Steady state results: Balanced non-linear load (2x5 KVA, three single-phase
rectifier)
Figure 6.20 Output Currents of Unit 1 and Unit 2 with harmonic drooping enabled
168
Figure 6.21 Output Currents of Unit 1 and Unit 2 with harmonic drooping disabled (gains
set to zero)
6.2.3 Transient Load Sharing Performance
In this section, simulation results are given for transient performance of the proposed
load sharing algorithm. The load was initially set to 8 kW balanced resistive load, and
• At approximately 3.53 sec, the load was change to no-load,
• At approximately 5.72 sec, a 2 x 5kVA 0.8 pf lag load was applied
• At approximately 8.28 sec, the load was changed to 2.666kW single-phase
resistive load.
Other conditions are the same as the simulations in section 3.1
From the results (Fig. 6.22 to Fig. 6.28) it can be seen that proper load sharing
was maintained during all load transients, and good load voltage regulations were also
maintained ( ± 1% at steady state and ± 5% during transients).
169
Figure 6.22 DQ real (top) and reactive (bottom) powers of Unit 1 and Unit 2
Figure 6.23 Output currents of Unit 1 and Unit 2
170
(a)Phase Adjustment Unit 1 (a) Phase Adjustment Unit 2
(a) Amplitude Adjustment Unit 1 (a) Amplitude Adjustment Unit 2
Figure 6.24 Phases and Amplitude Adjustments of Unit 1 and Unit 2
Figure 6.25 RMS load voltages during simulation
171
Figure 6.26 Load transient from Balanced resistive to no-load
Figure 6.27 Load transient from no-load to balanced 0.8 pf lagging
172
Figure 6.28 Load transient from balanced 0.8 pf lagging to single-phase resistive
6.2.4 Synchronization to bypass and Free-Running Mode
To study the bypass synchronized mode and free-running mode operation the following
simulations have been performed:
• Transition from Bypass Synchronized and Free-Running
• Mismatched Clock Frequency during Free-Running Mode
Transition from Bypass Synchronized and Free-Running Mode
In this simulation, transitions between UPS operating modes were investigated.
The bypass voltage (Main Diagram) frequency was set to 60.5 Hz, and the units were
initially run synchronized to bypass (free_run=0). At approximately t=2.25 sec, the
free_run flag was set to 1 simulating the units lost its bypass voltage and entered free-run
mode. Prior to t=3.5 sec, the bypass voltage recovered and the units had to try to
resynchronize to bypass again. During all this time, a constant balanced resistive load of
8 kW was used.
173
Fig. 6.29 shows the bypass and units phase error obtained from the input to PI
controller in the PLL. Fig. 6.30 shows the output frequency of the UPS. It can be seen
that initially the units are phase and frequency locked to the bypass voltage at 60.5 Hz.
The frequency was then automatically set to 60 Hz when the units free-ran. When the
free_run flag was cleared at 3.5 sec, the units tried to resynchronize to bypass again, and
finally regained synchronization at approximately t=5sec.
Figure 6.29 Unit and Bypass phase synchronization error
Figure 6.30 Units Output Frequency
174
Fig. 6.31 and 6.32 show the units DQ powers and output currents during the
modes transitions above. It can be seen that load sharing was properly maintained during
the mode transitions. Only slight transient occurred during the time the units tried to
resynchronize to bypass voltage.
Figure 6.31 Units DQ real (top) and (reactive) powers
Figure 6.32 Units Output Currents
175
Mismatched Clock Frequency during Free-Running Mode
During free-run mode, the output voltage frequency of each UPS is determined by
the sampling time of each DSP in the unit which in turn is determined by the clock
frequency of the crystal used. The crystal frequency error is usually in the range of
hundreds of ppm (parts per million). This small mismatch in the crystals used will be
reflected as output voltage frequency mismatches in the units. To simulate this effect, the
sampling time of each unit must be changed to reflect this clock frequency mismatch.
However, the same effect can be observed by simply changing the constant used in the
Reference Angle Generation block to different values as shown in Fig. 6.33. This
simulated Unit 1 unknowingly generated output voltage at frequency 60.001 and unit 2
generated 59.999 Hz.
To study the effect of this mismatch, the frequency locking mechanism was first
disabled by setting the gains to zero as shown in Fig. 6.33. Fig. 6.34 and 6.35 show the
results of the simulations when the frequency locking control was disabled. It can be seen
that the units failed to maintain proper load sharing and the phase angle adjustment
continually increase or decrease in order to compensate for the frequency mismatches.
Fig. 6.36, 6.37, and 6.38 show the results of simulations when the frequency
locking control was enabled (gains were set to 100). From Fig. 6.36, it can be seen that
the frequency locking control adjusted the frequency of each unit such that their
difference was compensated. This resulted in proper power load sharing as shown in Fig.
6.37 and prevented the phase adjustments to change continuously in Fig. 6.38.
176
Unit 1
Unit 2
Figure 6.33 Modifying the Reference Angle Generator Block for simulating mismatched
crystal clock frequencies
177
Figure 6.34 DQ real (top) and reactive (bottom) powers during free-run with mismatched
frequency and frequency locking disabled
(a) Unit 1 phases adjustments
(b) Unit 2 phases adjustments
Figure 6.35 Units phases adjustments during free-run with mismatched frequency and
frequency locking disabled
178
(a) Unit 1
(b) Unit 2
Figure 6.36 Frequency locking adjustments during free-run with mismatched frequency
179
Figure 6.37 DQ real (top) and reactive (bottom) powers during free-run with mismatched
frequency and frequency locking enabled
(a) Unit 1 phases adjustments
(b) Unit 2 phases adjustments
Figure 6.38 Units phases adjustments during free-run with mismatched frequency and
frequency locking enabled
180
6.2.5 Load Sharing with Unequal Proportion
In the following simulations, the effectiveness of the proposed control for load
sharing of unlike units’ sizes is investigated. The following simulations assume that it
was desired to have unit 1 handle only 1/3 of the total load while unit 2 handle 2/3 of the
total load. In other words, this simulated conditions where unit 1 is half the size of unit 2.
Fig 6.39 shows the changes that need to be made in the Load Sharing Control Block in
order to accomplish this.
Figure 6.40 shows the results of the unequal proportion load sharing at steady
state for two different types of loads. It can be seen that the proposed load sharing control
effectively made the units share the load based on the desired proportion. The transient
performance was studied by changing one load to the other during simulation, and the
results are shown in Fig 6.41, 6.42 and 6.43. From these results, it can be seen that proper
load sharing was maintained during transient condition.
181
Unit 1 Unit 2
Figure 6.39 Setting up the control gains for unlike units sharing simulations
182
0.8 pf lagging Balanced Load (2 x 3 KVA 0.8 Resistive Balanced Load (2 x 3KW x 0.8 = 4.8 kW)
lag)
Unit 1 Unit 2 % P2/P1 Unit 1 Unit 2 % P2/P1

Pa (watt) 530.54 1061.50 200.08% Pa (watt) 669.31 1339.38 200.11%
Pb (watt) 531.50 1061.34 199.69% Pb (watt) 669.90 1339.59 199.97%
Pc (watt) 530.47 1062.28 200.25% Pc (watt) 669.47 1339.89 200.14%
Ptot(watt) 1592.5 3185.1 200.01% Ptot(watt) 2008.7 4018.9 200.07%
Qa (var) 392.96 789.83 201.00% Qa (var) -4.26 -6.22 N/A
Qb (var) 394.48 790.67 200.43% Qb (var) -3.91 -4.15 N/A
Qc (var) 398.85 788.23 197.63% Qc (var) -0.68 -7.41 N/A
Qtot (var) 1186.3 2368.8 199.68% Qtot (var) 2962.0 2962.1 N/A
Load Volt Van=119.76 Vbn=119.76 Load Volt Van=120.33 Vbn=120.33
(VLNrms) Vcn=119.76 (VLNrms) Vcn=120.33
Figure 6.40 Steady state performance of load sharing with unequal proportion
183
Figure 6.41 DQ real (top) and reactive (bottom) powers of Unit 1 and Unit 2 for unequal
load sharing proportion
184
(a)Phase Adjustment Unit 1 (a) Phase Adjustment Unit 2
(a) Amplitude Adjustment Unit 1 (a) Amplitude Adjustment Unit 2
Figure 6.42 Phases and Amplitude Adjustments of Unit 1 and Unit 2 for unequal load
sharing proportion
Figure 6.43 Units Output Currents during transient for unequal load sharing proportion
185
6.2.6 Lost of Inter-Unit Communication
The following simulations studied the effect of losing the inter-unit
communication when the two units were running in parallel. The system load was
initially set to balanced 8 kW resistive load. To simulate the lost of communication
condition, the global flag COMM_OK was changed from 1 to 0 at t=4 sec as shown in
Fig 6.44. After loosing the communication the units ran at the same load for a while, until
the load was changed to balanced 4 kW resistive at approximately t=5.23 sec. At t=
7.515, the load was changed again back to the balanced 8 kW resistive.
Figure 6.45, 6.46, 6.47, and 6.48 show the results of the simulation. It can be seen
that even after the inter-unit communication was lost, the two units maintain the proper
load sharing. This verifies that the dependency of the proposed load sharing technique on
the communication is not critical. The communication is used only to improve the
performance of the load sharing under components mismatches and the present of
measurements errors.
Figure 6.44 COMM_OK flag was cleared at t=4 sec to simulate lost of communication
186
Figure 6.45 Units output DQ real (top) and reactive (bottom) powers when
communication was lost at t=4 sec
Figure 6.46 Units’ output currents when communication was lost at t= 4 sec
187
Figure 6.47 Units output currents transient from 8kW to 4 kW after communication was
lost
Figure 6.48 Units output currents transient from 4kW to 8 kW after communication was
lost
188
6.3 Experimental Test Bed
To verify the effectiveness of the parallel inverters control, a second 5 kVA test
bed unit was built at the Mechatronics Laboratory at The Ohio State University. The two
units are interconnected as shown in Figure 6.49. Communication between the two units
is accomplished through an RS232 serial communication link between the two Inverter
DSP systems as shown in Fig. 6.49.
189
⎡Vinv ab ⎤ ⎡Vload an ⎤
⎡Vbyp ab ⎤ ⎡Vpwm ab ⎤ ⎢Vload ⎥
⎢Vbyp ⎥
⎢ bc ⎥ ⎢ bc ⎥ ⎢ bn ⎥
⎢ bc ⎥
⎣⎢Vpwm ca ⎦⎥ ⎣⎢Vinv ca ⎦⎥ ⎣⎢Vload cn ⎦⎥
⎣⎢Vbyp ca ⎦⎥
2.0mH
Iina Iinv a Iload a
1100uF Vdc 1100 uF

Iin b Iinv b
Iload b
Iinc Iinv c
Iload c
⎡Vinv ab ⎤
⎡Vload an ⎤
⎡Vbyp ab ⎤ ⎡Vpwm ab ⎤
190
⎢Vpwm ⎥ ⎢Vinv ⎥ ⎢Vload ⎥
⎢Vbyp ⎥
⎢ bc ⎥ ⎢ bc ⎥ ⎢ bn ⎥
⎢ bc ⎥
⎢⎣Vbyp ca ⎥⎦ ⎣⎢Vpwm ca ⎦⎥ ⎣⎢Vinv ca ⎦⎥ ⎣⎢Vload cn ⎦⎥
2.0mH
Iina Iinv a Iload a
1100uF Vdc 1100 uF

Iin b Iinv b
Iload b
Iinc Iinv c
Iload c
Figure 6.49 Experimental Test Bed for Parallel Inverters

6.4 Experimental Results
Fig.6.50, 6.51, and 6.52 show the steady state performance of the load sharing
control under various loads conditions. In Fig. 6.50 and 6.51, each trace box shows the
per-phase load voltage and the two units’ output currents. For Fig. 6.52 only the two
units’ output currents are shown. From top to bottom the quantities apply for phase a, b,
and c respectively. In Fig. 6.50, balanced three-phase resistive load is applied, while in
Fig. 6.51 resistive loads are applied with unbalanced loading (phase a being unloaded).
Fig. 6.52 shows the load sharing performance under non-linear load in the forms of three
single-phase diode rectifiers with RC loads. It can be seen that the load currents are well
shared between the two units, which verifies the effectiveness of the harmonic sharing
droop control.
Fig. 6.53 and Fig. 6.54 show the performance of the load sharing control under
changing load conditions. In Fig. 6.53, a 100% to 0% load change and 0% to 100% load
change are shown on the same plot. Fig. 6.54 shows more detailed view of the 0 to 100%
load change. It can be seen the load sharing was well maintained under both load
transients.
Finally, in Fig. 6.55 unit 2 is brought on-line while unit 1 was supplying different
types of loads on each of its phases. Phase a and b were loaded with resistive loads while
phase c was loaded with a single-phase diode rectifier load. It can be seen that within a
few cycles the different loads are shared by the two units, verifying the effectiveness of
the control under reconnection transients and its robustness towards different per-phase
loading conditions.
191
Figure 6.50 Steady state load sharing performance for balanced resistive load
Figure 6.51 Steady state load sharing performance for unbalanced resistive load
192
Figure 6.52 Steady state load sharing performance for balanced non-linear rectifier load.
Figure 6.53 Dynamic performance: l00% to 0% and 0% to 100% load changes. Each
trace box shows the two units output currents for phase a, b, and c (from top to bottom)
193
Figure 6.54 Dynamic performance 0% to 100% load acquire (zoom in of Fig. 6.53).
Figure 6.55 Unit 2 is reconnected with different load applied on each phase. Phase a and
phase b: linear resistive load. Phase c: single-phase non-linear load.
194
CHAPTER 7
CONCLUSIONS AND FUTURE WORK
7.1 Conclusions
The first part of this PhD research outlines the development of a digital control
strategy for a single three-phase PWM inverter used in UPS applications. The control
strategy combines the perfect RSP controller for low THD output voltages regulation and
the discrete sliding mode current controller for fast over-current protection. The voltage
controller was developed by including the dynamic of the current controller into the plant
with the computation delay of the DSP accounted for. It was shown that by including the
harmonic frequency mode to be eliminated into the perfect RSP controller, superior low
THD performance could be achieved without sacrificing the transient recovery
performance of the output voltages.
The stability robustness of the proposed control system was verified using
Structured Singular Value Method under structured perturbations due to component
parameters errors and linear load variations. It was shown that the scalar weighting in the
optimal control cost function provides a way of tuning the transient performance of the
controller while maintaining stability robustness of the system under considered
195
perturbations. The presented simulation and experimental results verified the
effectiveness of the proposed control strategy both in providing low THD output voltages
regulations and in providing protection under short circuit condition.
The second part of this research describes a novel load sharing method that can
properly control the load-sharing such as the real, reactive, and harmonic powers for
parallel operation of UPS systems. The proposed scheme is implemented by combination
of droop method, average power control method, and harmonic droop sharing control
using only low bandwidth power information exchanged between each UPS unit. In
particular, the average power control method significantly reduced the sensitivity about
voltage and current measurement errors, the droop method allowed proper load sharing
when the communication between units was lost, and the harmonic control loop
guaranteed harmonic power sharing under nonlinear loads. Small signal stability analysis
was used to analyze the stability of the combined average power and droop method.
From the simulation and experimental results presented, it was shown that the
proposed parallel control method is effective in maintaining proper load sharing under
different types of loads including linear and non-linear loads in steady state and transient
conditions. It was also shown that when communication between units is lost, proper load
sharing can still be maintained. In this case, a control strategy is introduced for
maintaining the output voltage phase angle and frequency synchronization between
inverters in the event that common synchronization reference voltage is lost (inverters are
in free-running mode).
196
7.2 Future Work
Within the scope of the digital control for PWM inverters in UPS applications,
there are other areas that may be further investigated in order to improve the results
presented in this research. In this research, for example, standard space vector PWM
technique [126] has been used to generate the PWM switching patterns for the IGBTs at
5400 Hz. This switching frequency is common for low to medium power inverters. For
very high power applications, lower PWM switching frequency is desirable for
minimizing heat due to the losses generated in the devices and increasing overall unit
efficiency. Many PWM switching strategies optimized for low switching frequency
and/or IGBT losses have been investigated by the researchers over the years [127-132].
This topic, however, still presents vast research opportunities for improving the
performance of the PWM inverters in general. Also of interest is the effect of the lower
control sampling time to the control bandwidth and hence transient and steady state
performance of the inverter.
Another area closely related to this research is the distributed generation system.
This area has become of high interest recently due to the tendency of smaller and more
distributed power generations using alternative energy like fuel cell, solar cell, etc.[132-
136]. The results from this PhD research are directly applicable to this application, since
one of the building blocks of a distributed generation system is a PWM inverter as the
one described in this research. In particular, the requirements of the PWM inverters
developed in this research are the same as those used in a distributed generation system
under a stand alone AC supply mode of operation. The results of this PhD research,
197
however, need to be extended for other modes of operation in a distributed generation
system such as parallel operation with utility (grid interconnected mode) and transitional
mode operations.
Finally, the idea developed in this research in achieving output voltage with low
THD using the robust servo mechanism maybe used for other power converters
applications where low THD of AC signals are required. For example, the idea may be
applied to PWM rectifiers or active filters systems used in UPS applications where low
THD currents signals instead of voltages are required ([137]-[140]).
198
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APPENDIX A
MATLAB SCRIPT FOR CONTROL GAINS CALCULATIONS
212
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%% Program to calculate Control Gains using RSP Voltage Controller and %%
%% discrete Sliding Mode Current Controller for Single Unit Inverter %%
%% Author: Mohammad N Marwali %%
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
clear all
% PWM Inverter Voltage Rating and Filter Components

KVA=5e3;
inv_volt=240/sqrt(3); % L-L Inverter Cap Voltage
out_volt=120; % L-N output voltage
tr=out_volt/inv_volt; % transformer turn ratio
Cinv=55e-6; % Inverter filter capacitor
Linv=1.8e-3; % Inverter filter inductor
Rinv=0.1;
Cload=5e-6; % Output capacitor
fs=40e6/2/3704; % PWM switching frequency
% Define control sampling time

Tsamp=1/fs;
% Define fundamental frequency

ffun=60;
wfun=2*pi*ffun;
%% Define harmonics frequencies

w1=wfun; % 1st harmonic
%% Define KVA, voltages, currents, and impedance bases

KVAb=1/3*5e3; % Single phase KVA base
Vb_load=out_volt*sqrt(2); % Load voltage base
Ib_load=KVAb/out_volt*sqrt(2); % Load current base
Vb_inv=inv_volt*sqrt(2); % Inv Filter voltage base
Ib_inv=KVAb/inv_volt*sqrt(2); % Inv Filter current base
Zb_inv=Vb_inv/Ib_inv; % Inverter Filter impedance base
Zb_load=Vb_load/Ib_load; % Load impedance base
%% Compute perunit value of filter components

xCinv=1/(wfun*3*Cinv)/Zb_inv % Inverter capacitor filter
xLinv=(wfun*Linv)/Zb_inv % Inverter inductor filter
xRinv=Rinv/Zb_inv;
xLtrans=0.03 % 3% p.u transformer inductance

xRtrans=0.01 % 1% p.u transformer losses
xCload=1/(wfun*Cload)/Zb_load % Output capacitor
213
%% Per Unit Current Limit
Ilimit=3; % 300% inverter current limit
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
% Start design of discrete SM current controller
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%% Define the plant for the current controller
A=[0 xCinv*wfun ;
-1/(xLinv/wfun) -xRinv/(xLinv/wfun)];
B=[0;
1/(xLinv/wfun)];
E=[-xCinv*wfun;
0];
F=[0;
-1];
C=[0 1];
D=0;
%% Discretize the plant for the current controller
sysc=ss(A,B,C,zeros(size(C,1),size(B,2)),'inputdelay',0);
[Acurrd,Bcurrd,Ccurrd,Dcurrd]=ssdata(sysd);
CBinv=inv(Ccurrd*Bcurrd);
CA=Ccurrd*Acurrd;
CD=Ccurrd*F;
sysc=ss(A,E,C,zeros(size(C,1),size(B,2)),'inputdelay',0);
[Acurrd1,Ecurrd,Ccurrd1,Dcurrd1]=ssdata(sysd);
CE=Ccurrd1*Ecurrd;
%%% Discrete sliding mode controllers gains

Ksm_q=[CBinv(1,1) -CBinv(1,1)*CA(1,1)*[1.5 -0.5] -CBinv(1,1)*CA(1,2)*[1.5 -0.5] -CBinv(1,1)*CE(1,1)*[1.5 -0.5] ];
%% Define Discrete Sliding Mode Controller

%% x=[vinv(k-1) iinv(k-1) isnd(k-1)]
%% u=[icmd viinv iinv isnd]
%% y=vpwm
Asm=zeros(3,3);
Bsm=[0 1 0 0;
0 0 1 0;
0 0 0 1];
Csm=[Ksm_q(3) Ksm_q(5) Ksm_q(7)];
Dsm=[Ksm_q(1) Ksm_q(2) Ksm_q(4) Ksm_q(6)];
214
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
% Start design of Perfect RSP voltages controllers
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%% Define the true plant

Ao=[ 0 xCinv*wfun 0 -xCinv*wfun;
-1/(xLinv/wfun) -xRinv/(xLinv/wfun) 0 0;
0 0 0 xCload*wfun;
1/(xLtrans/wfun) 0 -1/(xLtrans/wfun) -xRtrans/(xLtrans/wfun)];
Bo=[0;
1/(xLinv/wfun);
0;
0];
Co=[0 0 1 0];
Do=zeros(size(C,1),size(B,2));
%% Define the analog servo compensator

Ch1=[0 1;
-w1^2 0];
Ch2=[0 1;
-w2^2 0];
Ch3=[0 1;
-w3^2 0];
Ch4=[0 1;
-w4^2 0];
Ch5=[0 1;
-w5^2 0];
Ch7=[0 1;
-w7^2 0];
Ch_star=[[Ch1 zeros(2,2) zeros(2,2) zeros(2,2) ];

[zeros(2,2) Ch3 zeros(2,2) zeros(2,2) ];
[zeros(2,2) zeros(2,2) Ch5 zeros(2,2) ];
[zeros(2,2) zeros(2,2) zeros(2,2) Ch7 ]
];
Bh_star=[0;
1;
0;
1;
0;
1;
0;
1;];
215
% Discretize true plant
sysc=ss(Ao,Bo,Co,Do,'inputdelay',0.5*Tsamp);
[Aod,Bod,Cd,Dd]=ssdata(sysd);
% Calculate equivalent plant+DSM current controller

C1=[eye(2) zeros(2,3)];
C2=[zeros(1,3) 1 0];
Ad=Aod-Bod*(CBinv*CA*C1+CBinv*CE*C2);
Bd=Bod*CBinv;
Cc_star=eye(size(Ch_star,1));
% Discetize and compute balanced realization of the controller

csysc=ss(Ch_star,Bh_star,Cc_star,zeros(size(Ch_star,1),size(Bh_star,2)));
[csysbc,Tbal]=ssbal(csysc);
[Acon_d,Bcon_d,Ccon_d,Dcon_d]=ssdata(csysd);
% Form the augmented equivalent plant and the servo compensator

Ad_big=[Ad zeros(size(Ad,1),size(Acon_d,2));
-Bcon_d*Cd Acon_d];
Bd_big=[Bd ; -Bcon_d*Dd];
% Define the weighting matrices

epsilon=1e-5;
state_W=0.005; %WP
fund_servo_W=5e5; %WS1
harm_servo_W=1e-2*5e5; %WH
Q1=state_W*eye(size(Ad,1));
Q2=eye(size(Acon_d,1));
Q2(1:2,:)=fund_servo_W*Q2(1:2,:);
Q2(3:8,:)=harm_servo_W*Q2(3:8,:);
Q=[ Q1 zeros(size(Ad,1),size(Acon_d,2));
zeros(size(Acon_d,1),size(Ad,2)) Q2];
R=epsilon;
% Now perform the optimal calculations of the gains

[Kd,S,E]=dlqr(Ad_big,Bd_big,Q,R);
Kd=-Kd;
% Scale the inputs by 300 to make the Bcon_d matrix nice

s_scale=600;
Bcon_d=s_scale*Bcon_d;
Kd(:,6:13)=Kd(:,6:13)/s_scale;
216
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%% Compute Variable Frequency Harmonic Servo Compensator
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
harmonic=[1 3 5 7];
Bh_star=[0;1];
for h=1:length(harmonic)
i=1;
for f=59.0:0.02:61
w=2*pi*f*harmonic(h);
Ch_star=[0 1;
-w^2 0];
csysc=ss(Ch_star,Bh_star,eye(2),0);
[csysbc,T]=ssbal(csysc);
[Acon_dx,Bcon_dx,Ccon_dx,Dcon_dx]=ssdata(csysd);
B1(i)=Bcon_dx(1)*s_scale;
B2(i)=Bcon_dx(2)*s_scale;
i=i+1;
end
f=59.0:0.02:61;
pA11{h}(2)=pA11{h}(2)+pA11{h}(1)*60;
pA12{h}(2)=pA12{h}(2)+pA12{h}(1)*60;
pA21{h}(2)=pA21{h}(2)+pA21{h}(1)*60;
pA22{h}(2)=pA22{h}(2)+pA22{h}(1)*60;
pB1{h}(2)=pB1{h}(2)+pB1{h}(1)*60;
pB2{h}(2)=pB2{h}(2)+pB2{h}(1)*60;
end
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%% Some useful matrices used in simulations etc.
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%% Define Delta-Wye Transformer Voltages and Currents Transfer Matrices

%In ABC reference frame
Kll=[1 -1 0;
0 1 -1;
-1 0 1];
217
Kln=[1 0 -1;
-1 1 0;
0 -1 1];
Trv=[-1 0 0;
0 -1 0;
0 0 -1];
Tri=1/3*[-2 1 1;
1 -2 1;
1 1 -2];
%ABC to DQ Stationary or vice versa

Ks=2/3*[cos(0) cos(0-2*pi/3) cos(0+2*pi/3);
sin(0) sin(0-2*pi/3) sin(0+2*pi/3);
1 1 1 ];
Ksinv=inv(Ks) ;
Tri_qd0=Ks*Tri*Ksinv;
Tri_qd=Tri_qd0(1:2,1:2);
Trv_qd0=Ks*Trv*Ksinv;
Trv_qd=Trv_qd0(1:2,1:2);
218
APPENDIX B
MATLAB SCRIPT FOR ROBUST STABILITY ANALYSIS OF SINGLE
INVERTER CONTROL SYSTEM
219
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
% ROBUST STABILITY ANALYSIS OF SINGLE INVERTER CONTROL SYSTEM
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
cinv_tol=0.06;
linv_tol=0.15;
cload_tol=0.06;
ltrans_tol=0.15;
rinv_tol=0.5;
rtrans_tol=0.5;
yrload_tol=1;
ylload_tol=1;
linv_nom=xLinv/wfun;
cinv_nom=1/(xCinv*wfun);
ltrans_nom=(xLtrans/wfun);
cload_nom=1/(xCload*wfun);
rinv_nom=xRinv;
rtrans_nom=xRtrans;
yrload_nom=0.8;
ylload_nom=0.6*wfun;
rinv_del=rinv_nom*rinv_tol;
rtrans_del=rtrans_nom*rtrans_tol;
yrload_del=yrload_nom*yrload_tol;
ylload_del=ylload_nom*ylload_tol;
reps=1e-1;
%% Define nominal perturbed plant
Ap=[ 0 1/cinv_nom 0 -1/cinv_nom 0;

-1/linv_nom -rinv_nom/linv_nom 0 0 0;
0 0 -yrload_nom/cload_nom 1/cload_nom -1/cload_nom;
1/ltrans_nom 0 -1/ltrans_nom -rtrans_nom/ltrans_nom 0;
0 0 ylload_nom 0 -reps*ylload_nom];
Bnom=[ 0;
1/linv_nom;
0;
0;
0];
Bdel=[ -cinv_tol 0 0 0 0 0 0 0 ;
0 -linv_tol 0 0 -rinv_del/linv_nom 0 0 0 ;
0 0 -cload_tol 0 0 0 -yrload_del/cload_nom 0 ;
0 0 0 -ltrans_tol 0 -rtrans_del/ltrans_nom 0 0 ;
0 0 0 0 0 0 0 ylload_del
];
Bp=[Bnom Bdel];
Cnom=[1 0 0 0 0;
0 1 0 0 0;
220
0 0 1 0 0;
0 0 yrload_nom 0 1];
Cdel=[ 0 1/cinv_nom 0 -1/cinv_nom 0 ;
-1/linv_nom -rinv_nom/linv_nom 0 0 0 ;
0 0 -yrload_nom/cload_nom 1/cload_nom -1/cload_nom;;
1/ltrans_nom 0 -1/ltrans_nom -rtrans_nom/ltrans_nom 0;
0 1 0 0 0;
0 0 0 1 0;
0 0 1 0 0;
0 0 1 0 0;];
Cp=[Cnom ; Cdel];
Dnom=[ zeros(3,9);
0 0 0 0 0 0 0 yrload_del 0];
Ddel=[ 0 -cinv_tol 0 0 0 0 0 0 0 ;
1/linv_nom 0 -linv_tol 0 0 -rinv_del/linv_nom 0 0 0 ;
0 0 0 -cload_tol 0 0 0 -yrload_del/cload_nom 0 ;
0 0 0 0 -ltrans_tol 0 -rtrans_del/ltrans_nom 0 0 ;
0 0 0 0 0 0 0 0 0 ;
0 0 0 0 0 0 0 0 0 ;
0 0 0 0 0 0 0 0 0 ;
0 0 0 0 0 0 0 0 0
];
Dp=[Dnom ; Ddel];
plant_nom_c=pck(Ap,Bp,Cp,Dp);
% apply Sample & Hold to the nominal plant

sysp=ss(Ap,Bp,Cp,Dp);
sysp.inputdelay=[0.5*Tsamp zeros(1,8)];
syspd=c2d(sysp,Tsamp,'zoh');
% Transform discrete plant to w-plane

sysp_w=d2c(syspd,'tustin');
[Ap_c,Bp_c,Cp_c,Dp_c]=ssdata(sysp_w);
plant_nom_w=pck(Ap_c,Bp_c,Cp_c,Dp_c);
%% CHECK ONLY : Compare original plant vs. plant+zoh

del_cinv=0;
del_linv=0;
del_cload=-1;
del_ltrans=0;
del_rinv=0;
del_rtrans=0;
del_yrload=1;
del_ylload=1;
221
del=[del_cinv 0 0 0 0 0 0 0 ;
0 del_linv 0 0 0 0 0 0 ;
0 0 del_cload 0 0 0 0 0 ;
0 0 0 del_ltrans 0 0 0 0 ;
0 0 0 0 del_rinv 0 0 0 ;
0 0 0 0 0 del_rtrans 0 0 ;
0 0 0 0 0 0 del_yrload 0 ;
0 0 0 0 0 0 0 del_ylload
];
plant_del_c=starp(plant_nom_c,del);
rifd(spoles(plant_del_c));
plant_del_w=starp(plant_nom_w,del);
%% Define Discrete Sliding Mode Controller

%% x=[vinv(k-1) iinv(k-1) isnd(k-1)]
%% u=[icmd viinv iinv isnd]
%% y=vpwm
Asm=zeros(3,3);
Bsm=[0 1 0 0;
0 0 1 0;
0 0 0 1];
Csm=[Ksm_q(3) Ksm_q(5) Ksm_q(7)];
Dsm=[Ksm_q(1) Ksm_q(2) Ksm_q(4) Ksm_q(6)];
%% Define Discrete Harmonic Servo Controller

%% x=[servo states(1:8); vpwm(k-1)]
%% u=[error viinv iinv vload isnd vpwm]
%% y=vpwm
Aservo=[ Acon_d zeros(size(Acon_d,1),1);

zeros(1,size(Acon_d,1)) 0 ];
Bservo=[Bcon_d zeros(8,5) ;
zeros(1,5) 1];
Cservo=[Kd(6:13) Kd(5)];
Dservo=[0.0 Kd(1:4) 0.0];
dsm=pck(Asm,Bsm,Csm,Dsm);
servo=pck(Aservo,Bservo,Cservo,Dservo);
% Compute combined controller system

systemnames='dsm servo';
inputvar='[err; plant{4}]';
222
outputvar='[dsm]';
input_to_dsm='[servo; plant(1,2,4)]';
input_to_servo='[err; plant(1:4) ; dsm]';
sysoutname='Hcontrol_d';
sysic;
[Acontrol,Bcontrol,Ccontrol,Dcontrol]=unpck(Hcontrol_d);
sys_con_d=ss(Acontrol,Bcontrol,Ccontrol,Dcontrol,Tsamp);
% Transform controller to w-plane

sys_con_w=d2c(sys_con_d,'tustin');
[Acontrol,Bcontrol,Ccontrol,Dcontrol]=ssdata(sys_con_w);
controller_w=pck(Acontrol,Bcontrol,Ccontrol,Dcontrol);
% Compute combined system in w-plane

systemnames='plant_nom_w controller_w';
inputvar='[vref ; w{8}]';
outputvar='[vref-plant_nom_w(3); plant_nom_w(5:12)]';
input_to_plant_nom_w='[controller_w; w(1:8)]';
input_to_controller_w='[vref-plant_nom_w(3);plant_nom_w(1:4)]';
sysoutname='clp_w';
sysic;
% calculate frequency responses of perturbation

omega=logspace(-1,5,500);
clp_g=frsp(clp_w,omega);
clpstab_g=sel(clp_g,2:9,2:9);
%% loop-at-a-time perturbation frequency response analysis

figure
for i=1:8
subplot(4,2,i)
vplot('liv,m',sel(clpstab_g,i,i));
grid
end
%% Compute structured singular value for robust stability analysis

deltaset = [-1 0;-1 0;-1 0; -1 0; -1 0; -1 0; 1 1; 1 1];
[bnds,dvec,sens,pvec] = mu(clpstab_g,deltaset);
figure
vplot('liv,m',bnds);
pert=dypert(pvec,deltaset,bnds);
%% Compute closed loop poles zero for different del_inv
del_cinv=0;
del_cload=0;
del_ltrans=0;
del_rinv=0;
del_rtrans=0;
223
del_yrload=0;
del_ylload=0;
figure
hold
for del_linv=-[0 0.5 1.0 1.4 2.0]
del=[del_cinv 0 0 0 0 0 0 0 ;
0 del_linv 0 0 0 0 0 0 ;
0 0 del_cload 0 0 0 0 0 ;
0 0 0 del_ltrans 0 0 0 0 ;
0 0 0 0 del_rinv 0 0 0 ;
0 0 0 0 0 del_rtrans 0 0 ;
0 0 0 0 0 0 del_yrload 0 ;
0 0 0 0 0 0 0 del_ylload
];
clp_del=starp(clp_w,del);
[Adel,Bdel,Cdel,Ddel]=unpck(clp_del);
sys_del=ss(Adel,Bdel,Cdel,Ddel);
pzmap(sys_del);
end
224

Dissertation 1: Mohammad Nanda R Marwali

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Dissertation 1: Mohammad Nanda R Marwali

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DIGITAL CONTROL OF PULSE WIDTH MODULATED

INVERTERS FOR HIGH PERFORMANCE

Presented in Partial Fulfillment of the Requirements for

Mohammad Nanda R. Marwali, M.S.E.E

The Ohio State University

Problem (RSP) control theory to allow elimination of specified unwanted voltage

recovery performance on load transient. This technique is combined with a discrete

sharing to output voltage/current measurement errors and mismatch wiring impedances

October 4, 1969 …………………………Born – Medan, Indonesia

1993 ……………………………………..B. S. Electrical Engineering,

Institut Teknologi Bandung

1995-2000………………………………..Graduate Research Associate

Electrical Engineering Department

Ohio State University

1997 ……………………………………..M. S. Electrical Engineering

Ohio State University

1. M.N. Marwali and A. Keyhani, “Control of Distributed Generation Systems – Part I :

No. 6, pp. 1541-1550, November 2004

Systems – Part II : Load Sharing Control,” IEEE Transaction on Power Electronics,

Vol. 19, No. 6, pp. 1551-1561, November 2004

3. A. Keyhani, M.N. Marwali, L.E. Higuera, G. Athalye, G. Baumgartner, “An

Transactions on Power Systems, Vol. 17 , No. 1, pp. 1-6, Feb. 2002

4. M.N. Marwali, A. Keyhani, and W. Tjanaka, “Implementation of indirect vector

control on an integrated digital signal processor-based system,” IEEE Transactions

on Energy Conversion, Vol.14, No. 2 , pp. 139 – 146, June 1999

Major Field: Electrical Engineering

Major Area of Specialization: Electrical Machines, Power Electronics, and Control

Table of Contents ............................................................................................................... vi

List of Figures ....................................................................................................................ix

1.1 Background .......................................................................................................... 1

2. Control of single inverter system ................................................................................ 29

2.1 Theoretical background...................................................................................... 29

2.2 Control system development.............................................................................. 45

3. Analysis and simulations of the single inverter control .............................................. 63

3.1 Robust stability analysis..................................................................................... 64

4. Experimental results of single inverter control ......................................................... 107

4.1 5 kVA experimental test bed............................................................................ 107

5. Control of parallel inverters ...................................................................................... 118

6. Simulation and experimental studies of parallel inverters control............................ 138

6.1 Simulation system implementation .................................................................. 138

7. Conclusions and future work .................................................................................... 195

7.1 Conclusions ...................................................................................................... 195

A. Matlab script for control gains calculations ............................................................... 212

1.1 Typical single UPS system configuration .................................................................. 2

1.2 IGBT PWM Inverter system ...................................................................................... 4

1.3 A typical parallel UPS configuration ......................................................................... 5

1.6 Two inverters connected to a load............................................................................ 13

1.7 Difference from average power control ................................................................... 16

1.8 Frequency and Amplitude Droop Technique ........................................................... 18

1.9 Droop Characteristics............................................................................................... 19

1.10 Power Sharing using Signal Injection Method......................................................... 22

2.1 IGBT PWM Inverter Systems for UPS .................................................................... 31

2.2 Delta-Wye Transformer model ................................................................................ 31

2.3 Equivalent circuits in the DQ0 stationary reference frame ...................................... 38

2.4 Overall control system ............................................................................................. 45

2.5 Control timing diagram ............................................................................................ 46

3.1 Representation of a linear system with uncertainties ............................................... 65

3.2 Open loop model of the nominal plant..................................................................... 67

3.3 LFTs for 1 , 1 ,1 , and 1 ....................................................... 70

3.4 LFTs for rinv , rtrans , yrload , and yl load ........................................................................ 70

3.5 Block diagram of the nominal plant......................................................................... 72

3.7 Uncertain closed loop model.................................................................................... 77

3.8 The RSP and DSM controllers ................................................................................. 79