Pulse and Digital Circuits (April/May-2012, Set-1) JNTU-Hyderabad

Code No.: R09220403/R09 B.Tech. II Year II Semester Examination

S.1

April/May - 2012 PULSE AND DIGITAL CIRCUITS

( Common to ECE, BME, ETM )

Set-1
Solutions
Max. Marks: 75

Time: 3 Hours Answer any FIVE Questions All Questions carry equal marks --1. (a) (b) (c) 2. (d) (a)

Explain perfect compensation over compensation and under compensation with respect to attenuator circuits.

(Unit-I, Topic No. 1.3) Explain why the initial voltage distribution in an attenuator is determined by the capacitors. (Unit-I, Topic No. 1.2) Explain why the final voltage distribution in an attenuator is determined by the resistor. (Unit-I, Topic No. 1.2) Why does a resistive attenuator need to be compensated. [6+3+3+3] (Unit-I, Topic No. 1.2) The ideal transfer characteristic of particular clipper circuit is shown in figure. Design the circuit using ideal diodes and draw the input-output waveforms with proper explanation, if Vi = 10 sin t. (Unit-II, Topic No. 2.1)
Vo 8V

5V 0 5V 8V Vi

Figure
(b) 3. (a) With neat diagrams, explain the use of clamper circuit in television receivers as DC restorer. [10+5]

(Unit-II, Topic No. 2.3) Design a common-emitter transistor switch shown in figure, operated with VCC = 18 V and Vbb = 12 V. The transistor is expected to operate at IC = 8 mA, IB = 0.75 mA. Assume hFE = 25, VBE (sat) = VCE (sat) = 0 V and R2 = 6 R1. (Unit-III, Topic No. 3.3)
V CC RC Vo Vi R1

R2

Vbb

Figure (b) Define storage and transition times with respect to diodes. [12+3] (Unit-III, Topic No. 3.2)

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S.2
4.

Spectrum ALL-IN-ONE Journal for Engineering Students, 2013 A self-biased binary uses n-p-n transistor have maximum values of VCE(sat) = 0.4 V and VBE(sat) = 0.8 V and VBE cut off = 0 V. The circuit parameters are VCC = 15 V, RC = 1 k, R1 = 6 K, R2 = 15 k and RE = 500 . (a) (b) (c) Find the stable-state currents and voltages Find the minimum value of hFE required for BJT to provide the above stable state values

Also determine ICBO(mm) to which ICBO raises as temperature rises where neither BJT is off. [15] (Unit-IV, Topic No. 4.1) Draw the circuit of simple current time-base generator and explain its operation with the help of neat waveform and necessary equations. Also derive expression for sweep speed error (es), by considering the effect of internal resistance of inductor (RL) and collector saturation resistance (RCS) of the transistor. (Unit-V, Topic No. 5.1) Explain why an operational integrator is used in transistorized miller sweep circuit. [12+3] (Unit-V, Topic No. 5.2) Draw and explain the circuit diagram of a six-diode sampling gate. Derive expressions for VCmin.

5.

(a)

(b) 6. (a) (b) 7. (a) (b) 8. (a) (b) (c)

(Unit-VI, Topic No. 6.3)

For the four diode gate with a divider resistance R = 100 , VS = 25 V, Rf = 20, RL = RC = 200 k. Find Vcmin and Vnmin. [10+5] (Unit-VI, Topic No. 6.2) What type of synchronization is used when the interval between pulses is less than or equal to the natural period of the waveform generator? (Unit-VII, Topic No. 7.1) With the help of neat diagram and waveforms explain the use of a monostable relaxation circuit as a frequency divider. [7+8] (Unit-VII, Topic No. 7.2) Draw the circuit of a 2-input TTL totem-pole output NAND gate with the help of four transistors. Explain why the output of this gate cannot be wire. ANDed. (Unit-VIII, Topic No. 8.2) Explain the function of multi emitter transistor used in the above circuit. What is the disadvantages of using back to back diodes in place of multi emitter transistor? (Unit-VIII, Topic No. 8.3) Explain why this logic circuit is faster than open collector logic circuit. [6+6+3] (Unit-VIII, Topic No. 8.3)

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Pulse and Digital Circuits (April/May-2012, Set-1) JNTU-Hyderabad

S.3

SOLUTIONS TO APRIL/MAY-2012, SET-1, QP

Q1. Explain perfect compensation over compensation and under compensation with respect to attenuator circuits. Answer : April/May-12, Set-1, Q1(a) M[6] Compensation in Attenuator The compensation in attenuator can be obtained by connecting the capacitors C1 and C2 across its resistors R1 and R2 as shown in figure (i). Then the attenuator is called compensated attenuator. (a)
C1

R1 + Vo y +

Vi = V

x C2

R2

Vo

C1

+ R1 Vi R2 C2

Figure (iii) When the step signal of amplitude V is applied as input to the above circuit, the resultant outputs can be determined as follows. At t = 0+, capacitors do not allow the sudden changes in its output voltage. As the input Vi varies, the output voltage varies based on the values of C1 and C2 as,

Vo

C1 Vo (0 + ) = Vin ... (1) C +C 1 2 As time t increases to , the capacitors get fully charged and works like open circuit for the D.C inputs. Then, the output voltage depends only on resistors as, R1 Vo () = Vin ... (2) R +R 1 2 The perfect compensation of the attenuator can be achieved by equating the equations (1) and (2).
Vin

Figure (i): Compensated Attenuator For analysization purpose, the above circuit can be simplified as shown in figure (ii).

C1 Vi x C2

R1 y

R1 C1 = Vin R1 + R2 C1 + C2

R2

Vo

C1 R1 = C1 + C2 R1 + R2 (R1 + R2) C1 = R2 (C1 + C2) R 1 C1 = R 2 C2 ... (3) The response will be dependent on the value of capacitor, C1. Thus, from the balanced condition (equation (3)) C1 can be given as, R2 C1 = R 1 C2 = C p

Figure (ii) The bridge in the above circuit can be balanced by satisfying the following condition.

R1C1 = R2C 2
As the balance condition do not allow the current to pass through the branch x-y, while the calculated of output this branch can be ignored. Then, the resultant circuit becomes,

When the C1 is greater than the Cp, Vo(0+) goes beyond V o( ). This phenomenon is called over compensation. On the otherhand, when C is less than Cp, Vo(0+) will be less than Vo(). This phenomenon is called under compensation.

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S.4
Input V Output Vo (t)

Spectrum ALL-IN-ONE Journal for Engineering Students, 2013 The responses of the circuit for over compensation and under compensation can be given as follows,
Input V

Perfect compensation

V o(0+)

Perfect compensation Vo t Vo (0+) t (b) Under compensation Output V o (t) Vo

t=0 (a) Over compensation

Figure (b) Explain why the initial voltage distribution in an attenuator is determined by the capacitors? April/May-12, Set-1, Q1(b) M[3] Answer : The initial voltage distribution in an attenuator is determined by the capacitors (C1 and C2). This is because at t = 0, the capacitors act as short circuits and allow very large current to pass through them. Hence no current passes through the resistors R1 and R2. Figure below illustrates the modified circuit of an attenuator,
C1 + Vi (0+) q q C2 + Vo (0+)

Figure As infinite current is delivered to both the capacitors applying Kirchhoff law to determine initial value of output voltage (for step input response of magnitude A), we get,

q q A= C + C 1 2 1 1 A= q C + C 1 2 C2 + C1 = q C C 1 2
q=

0+

(Q q =

i dt )

AC1C2 C1 + C2

... (1)

At t = 0+, The output voltage Vo(0+) is the voltage across capacitor C2, i.e., Vo(0+) =

q C2

... (2)

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Replacing the value of q in equation (2), we get, Vo (0+) = Q2. (a)

S.5

A C1C2 (C1 + C2 )C2

... (3)

A C1 Vo (0+) = C + C 1 2

The ideal transfer characteristic of particular clipper circuit is shown in figure. Design the circuit using ideal diodes and draw the input-output waveform with proper explanation, if Vi = 10 sin t.
Vo 8V

Therefore, it can be observed from equation (3) that, the initial value of output voltage is determined by the capacitors (C1 and C2) in an attenuator. (c) Explain why the final voltage distribution in an attenuator is determined by the resistor? April/May-12, Set-1, Q1(c) M[3] Answer : The final voltage distribution in an attenuator is determined by using resistors, R1 and R2. This is because at t = (i.e., steady state), the capacitors act as open-circuit and no current passes through them. Figure illustrates the modified circuit diagram of an attenuator.
R1 + Vi () R2 Vo()

5V 0 5V 8V Vi

Figure Answer : Given that, For a clipper circuit with ideal diodes, Sinusoidal voltage, Vi = 10 sin t Ideal transfer characteristic of circuit is as shown in figure (i).
Vo 8V

April/May-12, Set-1, Q2(a) M[10]

Figure From figure,

5V 0 5V 8V Vi

Vi () Current (i) = R1 + R2
Output voltage, Vo() = iR2

Figure (i)

Vi () Vo () = R +R 2 1
V ( ) R2 o = Vi ( ) R1 + R2

R2

Figure (i) represents the transfer characteristic of a two level clipped or clipped double ended-circuit. Design of Two-level-clipping Circuit From figure (i), VR 1 = 8 V VR 2 = 5 V Vi = 10 sin t
Vi 10 0 10 Vi VR1 = 8 V VR2 = 5 V R D1 D2 Vo

Therefore, it can be observed that the final voltage distribution is determined by using resistors (R1 and R2). (d) Why does a resistive attenuator need to be compensated? Answer : April/May-12, Set-1, Q1(d) M[3] The output capacitance (i.e., C2) of an attenuator tends to distort the shape of the input waveform at its output. (i.e., the output either decays or increases exponentially). This rise time of the output waveform can be eliminated by providing an appropriate compensation to the resistive attenuator.

Figure (ii): Two Level Clipping Circuit using Two Ideal Diodes and a Positive Reference Source

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S.6
Case (i) For Vi < VR2 i.e., Vi < 5 V Diode D1 is OFF and does not conduct. Where as, Diode D2 is ON and starts conducting The output voltage, Vo = VR2

Spectrum ALL-IN-ONE Journal for Engineering Students, 2013 The modified circuit diagram for Vi > 8 is as shown is figure (v).
R D1 ON Vi VR1 = 8 V VR2 = 5 V D2 OFF Vo=VR2

Vo = 5V
The modified circuit for Vi < 5 V is as shown in figure (iii).
R D1 off Vi VR1 = 8 V VR2 = 5 V D2 ON Vo

Figure (v) The input-output waveform for the circuit can be drawn as shown in figure (vi).
V Input V i VR1 VR2 0 t Output Vo

Figure (iii) Case (ii) For VR2 < Vi < VR1 (i.e.,) 5 < Vi < 8 In this case, both the diodes (D1 and D2) are OFF and do not conduct. Therefore, the output voltage Vo = Vi Vo = 10 V The modified circuit for 5 < Vi < 8 is as shown in figure (iv).
R D1 off Vi VR1 = 8 V VR2 = 5 V D2 off V o = Vi

Figure (vi) (b) With neat diagrams, explain the use of clamper circuit in television receivers as DC restorer? April/May-12, Set-1, Q2(b) M[5]

Answer :

The purpose of using clamper circuit in television receiver is to restore the D.C components of the voltage waveform such that, (a) (b) (c) Proper triggering is achieved in horizontal and vertical sweeps Brightness of the picture is controlled automatically Also for blanking Cathode Ray Tube (CRT).

Figure (iv) Case (iii) For Vi > VR1 i.e., Vi > 8 V Diode D1 is ON and conducts. Diode D2 is OFF and does not conducts. Therefore, the output voltage Vo = VR

Basically, this circuit is known as D.C restores or clampers. Figure (a) illustrates a simple D.C restorer circuit.

Vin

Vo

Vo = 8V

Figure (a)

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For short RC time i.e., during positive peak of input waveform, the diode operates in forward bias region which charges up the capacitance very quickly. On the other hand, for large RC times i.e., during negative input waveform, the diode operates in reverse bias and the capacitance discharges through the resistor R. Since the time-period of the input waveform is very much less than the RC time for discharge, electrons are trapped on the right side of capacitance C. This trapping of electrons is carried out such that a negative D.C voltage is developed across the capacitor during each positive peak. It continues to generate capacitance until the voltage generated across capacitance becomes equal to the absolute value of positive peak at the input voltage waveform. Hence, the D.C potential at the right side of C consists of negative polarity and an amplitude (with respect to ground) which is equal to the amplitude of input positive voltage waveform. In this situation, the positive peak of input waveform is clamped with respect to ground potential and a constant dc voltage of negative polarity is restored at the right side of C. Figure (b) illustrates the voltage waveforms of the clamping circuits.
ov Output with D (iii)

S.7

Figure (b)(i) illustrates an input, in which the bottom trace line is slightly below the zero-volt level. This states that a small amount of negative D.C component is available at the left side of the capacitance. The waveform of figure (b)(ii) illustrates the normal operation of the circuit without employing diode (D). In this case, D.C level will be at the zero volt line. This is because the coupling capacitor (C) blocks the output dc voltage from one stage to other and hence no D.C component is observed at the output. Figure (b)(iii) i.e., the top trace line is generated when the diode is connected in the circuit. In this case the zerovolt line is located very much above the D.C level line and generates a large negative dc component in the voltage. This negative D.C component is equal to the magnitude of positive peak of the input sine wave signal. As a result, D.C components of the signal voltage is restored and its magnitude is automatically controlled by the amplitude of A.C signal voltage. Q3. (a) Design a common-emitter transistor switch shown in figure, operated with VCC = 18 V and Vbb = 12 V. The transistor is expected to operate at IC = 8 mA, IB = 0.75 mA. Assume hFE = 25, VBE (sat) = VCE = 0 V and R2 = 6 R1. (sat)
VCC

2 V/cm

Output with D ov (ii)

RC Vo

ov input (i) Vi R1

Figure (b) Irrespective of the presence or absence of charge across the capacitance, change in voltage level at one side of the signal, changes the voltage level at other side by equal amount and in the same direction. This balancing in voltage levels ensures the conservation of charge in the capacitor. The long RC time for discharging of C through R holds the voltage on the right side of C, such that the diode is forward-biased and hence recharges the capacitor C only when the maximum positive excursion of the signal is greater than the absolute value of the voltage available on the right side of C. The vertical location of a horizontal line which is at equal distance from positive and negative peaks represents the level of D.C voltage components of a symmetrical waveforms (such as sinusoidal waveforms).
R2

Vbb

Figure Answer : Given that, For a Common Emitter (CE) transistor, VCC = 18 V Vbb = 12 V IC = 8 mA IB = 0.75 mA April/May-12, Set-1, Q3(a) M[12]

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S.8
hFE = 25 VBE(sat) = VCE(sat) = 0 V R2 = 6 R1 RC = ? R1 = ? R2 = ?
VCC=18 V RC=? IC=8 mA IB=0.75 mA R1 V(1)=18 V VBE =0 + + R2=6R1 V(0)=0 V Vbb = 12 V G VCE=0 Vo

Spectrum ALL-IN-ONE Journal for Engineering Students, 2013

18 2 = R R 1 1 18 2 R1 16 R1 16 R1 16 R1
16 0.75 10 3

0.75 103 =

0.75 103 =

R1 =

= 21.3 k

R1 = 21.3 k
But, R2 = 6 R1 R2 = 6 21.3 103 R2 = 127.8 k

Figure (1) Let us assume, Vi = V(0) = 0 V for logic 0 Vi = V(1) = 18 V for logic 1. On applying KVL to the output circuit, we get, RC =
VCC VCE (sat) IC 18 0 8 10
3

R2 = 127.8 k
Thus, the common emitter transistor with designed values is a shown in figure (2).
VCC=18 V RC=2.25 k

RC =

RC = 2.25 k

RC = 2.25 k
From figure, Base current (IB) = 0.75 103 =
V (1) V (0) VBE ( sat ) R1 VBE ( sat ) ( Vbb ) R2

R1 =21.3 k Vi

IB=0.75 mA VBE(sat)=0V

IC= 8 mA

VCE(sat) =0 + +

18 0 0 0 (12) R1 R2
(Q R2 = 6R1)

R2 =127.8 k

0.75 103 =

18 12 R1 6 R1

Vbb= 12 V

Figure (2)

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(b) Define storage and transition times with respect to diodes. Answer : For answer refer Unit-III, Q6, Topics: Storage Time, Transition Time. Q4.

S.9
April/May-12, Set-1, Q3(b) M[3]

A self-biased binary uses n-p-n transistor have maximum values of VCE(sat) = 0.4 V and VBE(sat) = 0.8 V and VBE(cut-off) = 0 V. The circuit parameters are VCC = 15 V, RC = 1 k, R1 = 6 k, R2 = 15 k and RE = 500 . (a) (b) Find the s table state currents and voltages Find the minimum value of hEE requried for BJT to provide the above stable state values

(c) Also determine ICBO(max) to which ICBO raises as temperature rises where neighter BJT is off. April/May-12, Set-1, Q4 M[15] Answer : Given that, For a self-biased binary circuit employing npn transistor, VCE(sat) = 0.4 V VBE(sat) = 0.8 V VBE(cut-off) = 0 V VCC = 15 V RC = 1 k R1 = 6 k, R2 = 15 k, RE = 500 . (a) Stable state currents = ? (b) Minimum value of hfe = ? (c) ICBO(max) = ? Figure (i) illustrates the circuit diagram of a self-biased binary.

+VCC=15 V

RC=1 k

R1 =6 k

R1 =6 k

RC=1 k

Q1 R2 =15 k

Q2 R2 =15 k RE =500 G
Figure (i): Self Biased Binary Circuit

Consider that transistor Q1 is OFF and Q2 is ON. Since Q2 is in saturation, we get, VCE (sat) = VCE2 = 0.4 V VBE (sat) = VBE2 = 0.8 V

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S.10
(a) Computing Stable State Currents and Voltage

Spectrum ALL-IN-ONE Journal for Engineering Students, 2013

To calculate different voltages two equivalent circuits are illustrated in figure (ii) and (iii) where the transistor Q1 is OFF and Q2 is ON.
+VCC=15 V Q1 =off (VBE1 =0V) given Q1 RC= 1 k + + VBE1 VEG VBG1 G R2 =15 k + Q2 IB2 RE=500
IC2 VBE2 = 0.4V

R1 =6 k

+ VEG

VCG 2

Figure (ii): Equivalent Circuit from Base of Q1 to Collector of Q2 As, transistor Q1 is OFF, currents IC1 = IB1 = 0 mA.
Q1 off +VCC=15 V RC=1 k R1 =6 k + Q1 VCG1 VEG G + IB2 Q2=ON + VBE2 R2 =15 k RE =500

+ VEG

VBG2

Figure (iii): Equivalent Circuit from Collector of Q1 to Base of Q2 Now, Assuming thevenins equivalent across collector of Q2 and ground as illustrated in figure (iv).

When VCC Ground (G) is short

+VCC=15 V

RC=1 k IB1 =0 R1 =6 k C2 I R2 =15 k RTH G

Figure (iv)

VOC

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From figure (iv), we get, VOC1 = I (R1 + R2) VOC1 =

S.11

VCC ( R1 + R2 ) ( R1 + R2 + RC )
15 ( 6 10 3 + 15 10 3 + 1 10 3 ) 15 22 10 3 ( 21 10 3 ) (6 10 3 + 15 10 3 )

= 14.32 V

VOC1 = 14.32V
Thevenin resistance RTH = (R1 + R2)|| RC when VCC is short, =

( R1 + R2 ) RC ( R1 + R2 ) + RC Q R1 + R2 3 3 = 6 10 + 15 10 = 21103

(21 10 ) 1 10 (21 103 ) + (1 103 )

3 3

= 954.5

RTH = 954.5 or 0.95 k

Similarly, the thevenins equivalent circuit across base of transistor Q2 and ground is illustrated in figure (v).

VCC= + 15 V RC=1 k I R =6 k 1 I R2=15 k RTH I G

Figure (v)

B2

VOC

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S.12
From figure (v), we get,

Spectrum ALL-IN-ONE Journal for Engineering Students, 2013 Now, applying KVL to the base-emitter loop, IB2 (8.75 103) 0.8 500 (IB2 + IC2) + 10.23 = 0 8.75 103 IB2 0.8 500 IB2 500 IC2 + 10.23 = 0 9250 IB2 500 IC2 + 9.43 = 0 =
15 ( 6 10 3 ) + (15 10 3 ) + (1 10 3 ) 15 22 10 3 (15 10 3 ) 15 10 3

VCC R2 VOC2 = ( R1 + R2 + RC )

9250 IB2 + 500 IC2 = 9.43

... (1)

Now, applying KVL to the collector emitter loop, IC2 (0.95 103) VCE2 RE ( IB2 + IC2) + 14.23 = 0 IC2 (0.95 103) 0.4 500 ( IB2 + IC2) + 14.23 = 0 1450 IC2 500 IB2 + 13.83 = 0 1450 IC2 + 500 IB2 = + 13.83 ... (2) Multiplying equation (1) by 1450 and equation (2) by 500, we get,
13412500 IB2 + 725000 IC2 = 13673.5 250000 IB2 + 725000 IC2 = 6915 ( ) 13162500 IB2 ( ) ( ) = 6758.5

= 10.23 V VOC2 = 10.232 V And the thevenins equivalent resistance RTH is, RTH = R2 || (R1 + R2)

( R1 R2 ) = (R + R ) 1 2 15 103 (21 103 ) = 15 103 + 21103 Q R1 + R2 2 3 = 6 10 + 15 10 = 21103 315 106 = 36000

= 8.75 k

IB2 =

6758.5 13162500

IB2 = 0.52 mA and IC2 = 9.36 mA Calculating different voltage (from figure (vi)), (emitter to ground) (i) VEG = (IB2 + IC2)RE = (0.52 103 + 9.36 103) 500 = 4.94 V

RTH = 8.75 k
Therefore, The thevenins equivalent of transistor Q2 is illustrated in figure (vi).
0.95 k
I C2

VEG = 4.94 V
Emitter - ground voltage (VEG) is 4.94 V. (ii) VCG2 = VCE2 + VEG = 0.4 + 4.94 = 5.34 V

8.75 k IB2 + 10.23 V + VBE2 =0.8

+ VCE2 = 0.4 V + 14.32 V

VCG 2 = 5.34 V
(iii) VBG2 = VBE2 + VEG = 0.8 + 4.94 = 5.74 V

(IB2 +I C2 )

RE =500

Figure (vi)

VBG 2 = 5.74 V

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(iv)

S.13

R2 VBG1 = VCG2 R + R 1 2 15 103 6 103 + 15 103 = 5.34 0.714 = 3.81 V

= 5.34

ICBO(max) ICBO(max) can be computed by the circuit as shown in figure (vii),

VCC=15 V RC=1 k

(c)

R1 = 6 k Q1 A

VBG1 = 3.81V
(v) VBE1 = VBG1 VEG = 3.81 4.94 = 1.13 V

RE =500

RTH

R2=15 k

VBG1 = 1.13 V
In case of cut-off, VBE1 = 0 (given) but calculating we obtained VBE1 = 1.13 V. Thus, it ensures that the transistor Q1 is OFF. (vi) VCG1 =
G

VCC R1 V R + BG 2 C RC + R1 ( RC + R1 )
(By using super-position)

15 (6 10 3 ) 5.74 (1103 ) + (1 103 + 6 103 ) (1 103 + 6 103 )

90 103 5.74 103 + 7 103 7 103 = 12.86 + 0.82 = 13.68 V

=

Figure (vii) Applying thevenins equivalent across terminal A and ground, Thus, The thevenins voltage VA = VB1 with respect to ground is, VTH = VB1 = 3.81 V Thevenins resistance by considering the terminal A and ground G is, RTH =

( R1 + RC ) R2 R1 + RC + R2 (6 103 + 1 103 ) 15 103 22 103

VCG1 = 13.68 V
Therefore, the stable-state voltage and currents are, VCG1 = 13.68 V IC1 = 0 mA IC2 = 9.36 mA VCG2 = 5.34 V IB1 = 0 mA VBG1 = 3.81 V IB2 = 0.52 mA VBG2 = 5.74 V VEG2 = 4.94 V hFE(min) When transistor Q2 is ON, IC2 = 9.36 mA

RTH = 4.78 k
Figure (viii), illustrates the thevenins equivalent used to obtain ICBO(max) VBE(cutoff) = 0V, VEG = 4.94 V
E ICBO(ma x) A RTH =4.78 k VEG=4.94 V RE =500

IB2 = 0.52 mA
+

I C 2 9.36 10 3 hFE(min) = I = B2 0.52 10 3

= 18
hFE (min) = 18

V =3.81 V TH G

Figure (viii)

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S.14
VB1 = VEG = 4.94 V for ICBO(max) ICBO(max) = =

Spectrum ALL-IN-ONE Journal for Engineering Students, 2013

VB1 VTH RTH

4.94 3.81 4.78 103

1.13 4.78 10 3

= 0.236 mA
I CBO (max) = 0.24 mA

Draw the circuit of simple current time-base generator and explain its operation with the help of neat waveforms and necessary equations. Also derive expression for sweep speed error (es), by considering the effect of internal resistance of inductor (RL) and collector saturation resistance (RCS) of the transistor. Answer : April/May-12, Set-1, Q5(a) M[12] Operation of Simple Current Time-base Generator For answer refer Unit-V, Q22. Expression for Sweep Speed Error (es) In the simple circuit of a time-base generate, the supply voltage VCC is applied to the inductor inorder to generate current i.e., iL = iL =

Q5.

(a)

1 VCC dt L

t VCC ... (1) L An exponential decreases of inductor current at t > Ts decreases the collector voltage such that it settles down at VCC under steady-state conditions. If L and RCS indicate a physical yoke and collector saturation resistance of the transistor respectively, then the expression for current (iL) is given by,

VCC iL = RL + RCS

( RL + RCS )t L e 1 2 ( R + RCS )t 1 ( RL + RCS )t + t ...... 1 1 L L L 2

iL =

VCC RL + RCC VCC RL + RCS

( RL + RCS )t 1 ( RL + RCS ) 2 t 2 1 1 + 2 L L2 ( RL + RCS )t 1 ( R L + RCS ) 2 t 2 L 2 L2

1 ( R L + RCS )t 1 2 L2

VCC = R +R L CS
=

VCC ( R + RCS )t L RL + RCS L

iL =

(VCC )t 1 ( RL + RCS )t 1 2 L L

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For current increasing linearly to the maximum value of IL, the slope or sweep speed error (es) is expressed as, Q8. (a)

S.15

IL VCC es = RL + RCS
( R + RCS ) I L es = L VCC

Draw the circuit of a 2-input TTL totempole output NAND gate with the help of four transistors. Explain why the output of this gate cannot be wire. ANDed. April/May-12, Set-1, Q8(a) M[6]

Answer : Two-input TTL NAND Gate

+V = + 5V CC R R 1 R 2 Q 4

In order to maintain linearly at the output, the voltage across the circuit resistance is maintained small when compared to supply voltage (VCC). (b) Explain why an operational integrator is used in transistorized miller sweep circuit. April/May-12, Set-1, Q5(b) M[3]
R I 1 2 Q 1 I

D 2

1 Output

Answer : Q6. (a)

For answer refer Unit-V, Q15. Draw and explain the circuit diagram of a six-diode sampling gate. Derive expressions for VC(min). April/May-12, Set-1, Q6(a) M[10] For the four diode gate with a divider resistance R = 100 , VS = 25 V, Rf = 20, RL = RC = 200 k. Find Vc(min) and Vn(min). April/May-12, Set-1, Q6(b) M[5] What type of synchronization is used when the interval between pulses is less than or equal to the natural period of the wave form generator? Explain it briefly. April/May-12, Set-1, Q7(a) M[7]

3 Totem Pole output

Figure: Two Input NAND Gate with Totem-pole Output When the output changes from the low to the highstate, the output transistor of the gate goes from saturation to cutoff. Q4 is the external. With an active pull-up circuit replacing the passive Pull-up resistor R4, the propagation delay is reduced. This configuration as shown in the figure is called a totem-pole output because transistor Q3 sits upon Q4. These two transistors form a totem-pole. These transistors are used because a low output impedance is produced. When the output is in the low state, Q2 and Q4 are driven into saturation. Transistor Q3 is cutoff. The reason for placing the diode in the circuit is to provide a diode drop in the output path and thus ensure that Q3 is cutoff when Q4 is saturated. When the output changes to the high state, because one of the inputs drops to the low state, transistors Q2 and Q4 go into cutoff. The output current, IL flows through R4 (130 ) and diode D1. Therefore, the HIGH output voltage is given as, VOH = VCC VCE(sat) VD IL (130 ) Where, VD forward drop across diode D1, about 0.7 V VCE(sat) saturation voltage of Q3, about 0.1 V.

Answer : (b)

For answer refer Unit-VI, Q22.

Answer : Q7. (a)

For answer refer Unit-VI, Q20.

Answer :

Pulse synchronization is used when the interval between the pulses is less than or equal to natural period TP < T0 of a sweep generator. Pulse Synchronization For answer refer Unit-VII, Q2. (b) With the help of neat diagram and waveforms explain the use of a monostable relaxation circuit as a frequency divider. April/May-12, Set-1, Q7(b) M[8]

Answer :

For answer refer Unit-VII, Q5, Topic: Monostable Multivibrator used as Frequency Divider.

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B.Tech. II-Year II-Sem.

S.16

Spectrum ALL-IN-ONE Journal for Engineering Students, 2013 Thus, when one or more input is low, the transistor Q2 and Q3 do not conduct, resulting a current flow through the base of transistor Q4 via resistor R2. This causes transistor Q4 to saturate and the output is high. If both the inputs are high, the gate-collector of transistor Q1 conducts. As a result small base current is drawn from the transistor Q2 which saturates and produces low output voltage i.e., when no input is low, the transistor Q1 do not conduct resulting in a small current flow through based transistor Q2 and resistor R1. Also transistor Q3 saturates and produces a zero collector voltage.

The truth table of Totem-pole TTL NAND gate is as given below. INPUTS I1 0 0 1 1 I2 0 1 0 1 Q1 OFF OFF OFF ON Q2 OFF OFF OFF ON Q4 OFF OFF OFF ON Q3 OUTPUT ON ON ON OFF 1 1 1 0 2.

Table The output of a 2-input TTL totem-pole output NAND gate cannot be wire ANDed, because of the low output impedance, current spike problem and rapid change in the output of stray capacitance which are caused when either of the transistors Q3 or Q4 conduct simultaneously. These may ultimately cause damage to both transistors over a certain period of time. Hence, the totem-pole output cannot be tied or connected together to perform AND operation at the output. (b) Explain the function of multi emitter transistor used in the above circuit. What is the disadvantages of using back to back diodes in place of multi emitter transistor? Answer : April/May-12, Set-1, Q8(b) M[6] TTL technology employs multi-emitter transistor to serve the input devices. The purpose of using multi-emitter transistor in circuits is to speed-up the performances of the devices or circuits. In TTL totem-pole NAND gate multi emitter transistor is used at the input and the number of inputs generally used are two or more. Figure below illustrates a 2-input NAND circuit with totem-pole output stage,
R3 R1 R2 QS X0 X1 Q1 Q2 R4 Q4 D y

Thereby, the voltage generated at Q2 is too small to make transistor Q4 conduct. So, either transistor Q3 or transistor Q4 conducts but not both at the same time. But when transistor Q2 switches to non-conducting state, transistor Q4 switches to conducting before transistor Q3 turns off, resulting in a short circuit between the supply voltage and ground. Therefore, inorder to control the problem of current spikes a small resistance R4 of about 100 is added in series with the transistor Q3 and Q4 as shown in figure. Disadvantages Disadvantages of using back-back diodes instead of multi-emitter transistor are given below, 1. 2. 3. 4. 5. Low switching speed. Use of diodes in place of multi-emitter transistor increases the cost of the system. As diodes are connected back-back, it consumers large amount of space on an IC. Fabrication of large circuits becomes complex. It requires high driving source. (c) Answer : Explain why this logic circuit is faster than open collector logic circuit. April/May-12, Set-1, Q8(c) M[3]

The open collector logic circuit consists of only pulldown transistors in its output stage. The operation of the gate depends on the external pull-up resistor on the otherhand, the operation of totempole circuit does not depend on the external pull-up resistor. In open collector logic circuit when the output changes from low to high, the capacitance of the cable charges through the pull-up resistor. If the value of resistance is high (i.e., in k), the output voltage varies slowly which result in high time constants. Hence, the switching speed of the open collector logic circuit is slower than the totem-pole logic circuit.

Figure The various functions of multi-emitter transistor in an totem-pole circuit are given below, 1. If any of the two inputs is set low, then the base current flows through the transistor Q1 and resistor R1, thereby resulting in a high output where the voltage acquired at both the collector and emitter of transistor Q1 is identical and no base current passes through transistor Q2.

B.Tech. II-Year II-Sem.

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