Canadian Journal on Computing in Mathematics, Natural Sciences, Engineering and Medicine Vol. 2 No.

8, November 2011

Design of Digital Systems, in Fractal Form, Using the Digital Basic Cell DBC440
Luis Jos Quiones Rodrguez, Jos Javier Aguasvivas Santana and Yentrax Domnguez Carrasco Abstract. It is proposed the development of an Integrated Circuit called Digital Basic Cell 440 (DBC440), which can be configured into any logic gate using the cells called DBC. It is also proposed a design method for the digital logic circuits using the JQ1 table and in the same time, it has been developed a simulator capable of generating the true table, the simplified logic function and the optimized logic diagram. This method allows designing logic circuits without using the boolean algebra or other function simplifying method as the Karnaugh maps. In this document are shown the results of the realized tests to the prototype of this Integrated Circuit as also a step by step design example and a practical application example. The definitive integrated circuit will be developed in 0.6 micrometers technology in a die of 1.2 x 1.2mm. Keywords: Digital, DBC440, simulation and JQ table. fractal, integrated, new chip DBC440 to realize the digital logic circuits using only the DBC, in the form of fractal trees. This paper is organized in the following way: The section II, shows how can be obtained the DBC440 from Transmission Gates and Not Gates, it also shows the Layout of the realized prototype. The section III presents the proposed logic symbol for the DBC (3.1) and the integrated circuit with DBC (DBC 440) (3.2). The section IV shows how every logic gate can be obtained performing different combinations of the DBC cell. The section V shows the systematic way in the design procedure using the DBC and the JQ table (5.1), the procedure to optimize the tree using the simulator (5.2) and a practical example of application to monitor the battery cells water level (5.3). Finally, the section VI contains the conclusion, the acknowledgements and the references used in this paper.

I. Introduction II. Design Of The DBC The DBC cell is of big utility for the development of the majority of the digital systems. This is due the design of applications requiring great diversity of logic gates could be simplified and optimized thanks to the use of the cells of this new integrated circuit. This Chip DBC440 can be used in the development of functions of various outputs and multiple input variables. Thanks to the new proposed method in this paper, the cells will allow the design of digital circuits in form of fractal trees [1] using the DBC cells. Thanks to the versatility of this gate, the proposed design and the simulation software, the design process of the digital systems would be more economic. Using the cells included in the prototype of this new chip it had tested the correct performance of every possible logic function. The performance had been verified through the analysis done to the boolean basic equation using the correspondent input values. Art State. With the new methodology proposed for the design and the application of the new chip it had been realized various experiments in the laboratory, confirming the correct performance of the new design method and the utility of the
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2.1

OBTAINING THE DBC THROUGH TRANSMISSION GATES AND NOT GATES

THE

The new gate cell can be obtained of different manners, depending in the technology to use and the convenience. In this case it is shown how to obtain them interconnecting two Transmission Gates (TG), of CMOS technology, with a Not Gate (inverter). To obtain the DBC through TG it is precise first to know how they work.

Figure 2. (a) Transmission Gate (b) Behavior for W = 0. (c) Behavior for W = 1. The transmission gate Works as a switch governed by a W control signal, that is, the value of the control bit W determines if the path between the left and right sides (A y B) is open or closed. See Figure 2 (b) and 2(c) [2].

This will be discussed in section 5.1.

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Canadian Journal on Computing in Mathematics, Natural Sciences, Engineering and Medicine Vol. 2 No. 8, November 2011 The DBC can be built with two TG and a NOT gate, how it is shown in Figure 3. When W=1, the output Z=Y. This procedure can be algebraically synthesized by means of a logic function of Boolean algebra that can be obtained from the true table.

2.2 INTERNAL DIAGRAM OF THE DBC440 USING CMOS

Figure 3. Building the DBC through logic gates. (a) Result for W = 0 (b) Result for W = 1 [3]. The logic equation for this circuit is obtained from the following true table, wher the Z output corresponds to the previously expressed.

The proposed circuit for the construction of the DBC is shown in the Figure 4, as it can be observed, this design has twelve MOS transistors interconnected (NOT gates and Transmission Gates). The model of these transistors belongs to the BSIM3 VERSION 3.1, created by the University of Berkeley.

Figure 4. Internal circuit schematic of one DBC cell, designed in CMOS technology. Table 1. True table for function Z.

WX Y

2.3 LAYOUT OF THE DBC The layout for the integrated circuit prototype DBC440 is shown in the Figure 5. This was designed in the University of Puerto Rico, Mayaguez Campus and fabricated in MOSIS, using the AMIS (ON-SEMI) technology that designs in the 0.6 micrometers scale. The prototype of the integrated circuit has a total of four DBC cells.

Figure 1. Karnaugh Map for the true table function. Depending on the logic value of W, the output Z can be equal to X or Y (Table 1). When W=0, the output Z=X. 210

Canadian Journal on Computing in Mathematics, Natural Sciences, Engineering and Medicine Vol. 2 No. 8, November 2011

Figure7. Proposed chip called DBC 440.

IV.LOGIC OPERATIONS WITH THE DBC As it was explained previously, through the Boolean manipulation of the DBC440 equation, it can be obtained different configurations of known logic gates. Figure5. Layout of the circuit designed with the Virtuoso software from CADENCE.

III.Design of the DBC440 3.1 Logic symbol of the DBC440 The proposed DBC is symbolized schematically with a rhombus as is shown in Figure 6. Having three inputs that are X, Y, W and one output Z.

Table 2.1 Table of the logic functions and their equivalents with the DBC [5].

3.2 INTEGRATED CIRCUIT WITH THE DBC (DBC 440) Figure 6. Symbol of the DBC. For the construction, it has been decided to create a chip with six (6) internal DBC. This chip will be called DBC440, will have 28 pins and will have a Dual In Line Package (DIP), similar to the commercially used for the logic family 40XX [4]. The proposed chip cells will be arranged as follows:

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Canadian Journal on Computing in Mathematics, Natural Sciences, Engineering and Medicine Vol. 2 No. 8, November 2011 Design a Logical Combinational Circuit of three variables to generate the following logic function: f (A, B, C)= (2, 3, 4, 6). Step 2. True table of inputs and outputs

Table 3. Table of three inputs and one output for the function: f(a, b, c) = (2, 3, 4, 6). Step 3. Draw a digital fractal with the DBC in the shape of fractal tree with 2/2 DBC. Table 2.2 Table of the logic functions and their equivalents with the DBC [5]. For this example it had been used 3 variables (A, B, C); therefore, the number of DBC will be: #DBC = 2/2 = 4 DBC. From the fractal tree it has:

Table 2.3 Table of the logic functions and their equivalents with the DBC [5].

Where it can be observed that the Y and X variables of the superior cells stay unconnected. To know what to connect to each variable is proceeded to realize the next step where is added the fourth DBC in NOT configuration. This cell correspond to the A variable.

5.1 Design example with DBC cells using the JQ TABLE Step 1. Problem statement Step 4. Add variables V. DESIGN WITH DBC CELLS From the true table it can be obtained the values of (X, Y) taking into account the following table called JQ: 212

Canadian Journal on Computing in Mathematics, Natural Sciences, Engineering and Medicine Vol. 2 No. 8, November 2011

Table 4. JQ table For this exercise, we have then the following analysis: 4.1) It is analyzed for the function F the first value of J (0) and the first value of Q (1). Therefore, the input X1 = A. 4.2) The second value of J = 0 and the second value of Q = 0. Therefore, the input X2 = 0. 4.3) The third value of J = 1 and the third value of Q = 1. Therefore, the input Y1 = 1. 4.4) The fourth value of J = 1 and the fourth value of Q = 0. Therefore, the input Y2 = . So on this process can be repeated when we have a major number of variables. Step 5. Built the optimized logic schematic with the DBC. It will be realized the optimization as long as the X and Y inputs of the DBC have the same value (0 1) or exist one DBC behaving as a buffer or transference gate. Figure 10. Shows the circuit, with DBC, generated and optimized automatically by the simulator. The same can be used to test the performance of the circuit with the switched in the inputs, assigning all the possible combinations for the Z output. 5.3 APPLICATION EXAMPLE: The circuit of the Figure 11 it was designed to monitor the water level of the deep cycle batteries, used in the emergency power systems (UPS and converters) and industrial applications. Figure 8. Finished circuit 5.2 EXAMPLE OF DESIGN USING THE SIMULATOR: The circuit has two principal blocks, and for censing the liquid level, with LED indicators, which turns on when one of the cells in bellow the optimum level and the second to produce an audible signal when any of the cells lack of the needed water level.

Figure 9. It has the true table. Generated by the software, automatically, for the three variables and the Z function that is desired to obtain, which corresponds to the previous design example.

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Canadian Journal on Computing in Mathematics, Natural Sciences, Engineering and Medicine Vol. 2 No. 8, November 2011 VI. Conclusions and remarks In this paper it has been proposed the design of a new chip, the DBC440, for the design of Digital Systems, in fractal tree shape. In the same time, it is proposed a new method for the construction of digital systems using the new chip. It is presented an Step by Step example of the design method, for the comprehension of the same, the which was proved satisfactorily with the prototype chip. On the other hand, it is presented an application example to measure and advice when the level of water in the battery cells of deep cycle is below the optimum level. This chip can be applied in a variety of circuits in the areas of power, networks, mobile devices, controls, etc. Figure 11. Battery water level meter In the Figure 12 it is shown, for mayor versatility, the DBC disposition in fractal tree shape, for the case of eight input variables.

Acknowledgments
To PhD Ligia Amada Melo, Minister of Superior Studies, Science and Technology (MESCYT, from its spanish acronym); To the FONDOCYT, organism from the MESCYT that financed this research; To PhD Diogenes Aybar, Vice minister of Science and Technology of the MESCYT; To PhD. Rogelio Palomera, International Consultant of the Project from the University of Puerto Rico, Mayaguez campus; To PhD William Camilo Reinoso, dean of the Informatics and Technology Faculty of UNAPEC; To the APEC University, that supervised the research through the Direction of Research, Evaluation and Publications, coordinated by the PhD Teresa Hidalgo; To PhD Emin Rivera, who had worked hard to accelerate the requests from the research team to the university. To the MSc Ariel Quinones, who developed the software to simulate the design of the logic circuits with the DBC. To the TRIPOWER JQ Company, which provided the facilities for the practices realization.

Bibliography Figure 12. Construction of the DBC circuit with eight variables. The A variable is built with an independent DBC cell that feeds the X and Y variables of the first column of DBC (the which have B in their W input) according to the JQ Table results. It is opportune to clarify that depending on the function to generate, with the optimization process the majority of the DBC will be eliminated and the final diagram will have a reduced number of DBC in relation with the standardized disposition of fractal tree from Figure 12. [1] Mandelbrot, Benoit. "Introduccin." In Los objetos fractales, by Benoit Mandelbrot, 13-26. Espaa: Tusquet Editores, S.A., 2006. [2] Mano, Morris. "CMOS Transmission Gate Circuits." In Digital Design Second Edition, by Morris Mano, 430-433. New Jersey: Prentice-Hall, Inc., 1991. [3] Uyemura, John P. "Compuerta lgica de transmisin." Diseo de sistemas digitales. Un enfoque integrado, by John P. Uyemura, 314-320. Mxico: International Thomson Editores, S. A. de C. V., 2000. [4] Diseo Digital. Mxico: Prentice-Hall Hispanoamericana, S.A., 1987.

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Canadian Journal on Computing in Mathematics, Natural Sciences, Engineering and Medicine Vol. 2 No. 8, November 2011 [5] Mano, Morris. "Compuertas lgicas digitales." In Diseo Digital, by Morris Mano, 57-61. Mxico: Prentice-Hall Hispanoamericana, S.A., 1987.

Biography

INSERT Authors Photo

Luis Jos Quiones Rodrguez Profesor de la escuela de Ingenieria de la universidad UNAPEC. Nacido en la Republica Domincana.

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