Commun Nonlinear Sci Numer Simulat xxx (2013) xxxxxx

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Commun Nonlinear Sci Numer Simulat

journal homepage: www.elsevier.com/locate/cnsns

A new auto-switched chaotic system and its FPGA implementation

Mohamed Salah Azzaz a, Camel Tanougast b,, Sad Sadoudi a, Rabiai Fellah a, Abbas Dandache b
a b

Laboratory of Communications Systems, EMP of Algies, Algeria LICM, University Paul Verlaine of Metz, France

a r t i c l e

i n f o

a b s t r a c t
This paper presents a 3D chaotic system which is constructed by an auto-switched numerical resolution of multiple three dimensional continuous chaotic systems. The designed chaotic system provides complex chaotic attractors and can change its behaviors automatically via a chaotic switching-rule. Some complex dynamical behaviors are investigated and analyzed. The originality of the proposed architecture is that allows to solve the problem of the nite precision due to the digital implementation while provides a good tradeoff between high security, performance and hardware resources (low power and cost). Hardware digital implementation and FPGA circuit experimental results demonstrate a promising technique can be applied in efcient embedded ciphering communication systems. Moreover, the proposed chaotic system should be very useful for the consideration of reducing negative inuence of dynamical degradation in real-time embedded applications. 2012 Elsevier B.V. All rights reserved.

Article history: Received 4 March 2012 Received in revised form 17 November 2012 Accepted 19 November 2012 Available online xxxx Keywords: Chaotic system Dynamical analysis Statistical texts Digital implementation Auto-switched FPGA circuit

1. Introduction Chaotic systems have attracted increasing interest for theoretical research and practical implication [14]. Indeed, chaotic signal is characterized by sensitive dependence on initial conditions, complex similarity to random behavior and continuous broad-band power spectrum. With regard to the possibility for the self-synchronization of chaotic systems, the application of chaos in cryptography has become a focal topic for research [59]. Therefore, several schemes have been developed to exploit this property of chaotic systems for secure communications. Encryption based chaos has been suggested as new and efcient way to deal with the problem of fast and highly secure embedded applications and communications. For example, several works have been proposed such as the chaotic masking [10], the chaotic switching modulation [11], dynamic feedback modulation of information signal [12], and so on. Generally, the strategy of these techniques consists in implementing a cipher key generator based on a data chaotic generator used for encrypting a plaintext. Despite the chaotic signals obtained with these systems are non-periodic, uncorrelated and appear random in the time domain, they are characterized by specic attractors which can be used by cryptanalysis attacks through a key space analysis. Indeed, most of them were implemented by means of low-dimension discrete chaotic systems [13,14]. It results that their simple structures lead to a secret key space too small corresponding at no longer safe to the information masked by the simplex low dimension chaotic system [15]. Consequently, these chaotic generators are easily attacked by a simple display of their attractors. In this context, it becomes important to hide them by developing the robustness associated with these generators in order to increase the complexity of a cryptanalysis attack from the visualization and identication of the chaotic signals used as cipher keys. To overcome these drawbacks, chaotic systems with multiple attractors have received increasing attention in recent years because of their great impact on both theoretical analysis and engineering applications such as mentioned in data encryption [2]. Indeed, the
Corresponding author.
E-mail addresses: mohamed.azzaz@umail.univ-metz.fr (M.S. Azzaz), Camel.Tanougast@univ-metz.fr (C. Tanougast). 1007-5704/$ - see front matter 2012 Elsevier B.V. All rights reserved. http://dx.doi.org/10.1016/j.cnsns.2012.11.025

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chaotic Pseudo-Random (PR) sequences obtained from auto-switched chaotic systems are theoretically proved with good randomness, innite period and unpredictability on long term [1,3,4]. Consequently, these chaotic systems provides more complex behaviors and has the characteristics of high capacity, high security and high efciency. A digital implementation of chaotic systems presents certain advantages and provides accuracy and a signicant hope for integration in embedded applications, especially for data encryptions and secure communications between embedded systems. Unlike analogue implementations [16,17], which exhibit various practical difculties in ensuring information recovery and dealing with the problem of chaotic synchronization (since the component values vary with age and temperature, etc.), a digital implementation avoids the parameter mismatch between transmitter and receiver. Recently, many digital implementations of chaotic systems have been proposed and implemented in FPGA (Field Programmable Gate Array) technology [18,19,15,20,21]. This programmable hardware fabric takes an increasingly important place in the design of digital systems. This is due to the excellent trade-off between computational power and the processing exibility which it provides. Hence, several behavioral structures of chaotic systems which are used for designing chaotic hardware key generation suitable for data encryption systems. Meanwhile, other chaotic PR sequence generators have been proposed in the literature [2225,1] and several high-dimension chaotic systems also have been implemented in FPGA technology [3,26,27]. However, to perform a hardware implementation with good statistical properties is still a great challenge. Other works have suggested switched chaotic digital systems [3,26,1,4]. Usually, these systems are based on a four-dimensional (4D) chaotic system where one component is used as a symmetrical axis corresponding to a switched function depending on specic parameters. In these approaches, the switching rule corresponds to controlled state variables of one dimension of the chaotic system in order to change its behavior randomly. In this paper, we consider a new chaotic system which is constructed by an auto-switched of four continuous chaotic systems. The main differences and advantages in comparison with previous works [3,26,1,4,28], is that we consider an autoswitch between several three-dimensional (3D) chaotic systems and from one chaotic component signal. The designed system provides complex chaotic attractors. It can change its behaviors automatically via a chaotic switching-rule in order to improve the statistical properties and the complexity of chaotic sequences while maintaining the adaptation of one self-synchronization as dened in [58,29,9]. The obtained auto-switched chaotic system (with FPGA implementation) can be useful for the consideration of reducing negative inuence of dynamical degradation in real-time embedded applications. More precisely, when chaotic systems are implemented in digital form (nite computing precision), it is doubtful whether or not they can still preserve the desired dynamics of the continuous chaotic systems [30,31]. The most well known problem of the degradation is the existence of many short-length chaotic orbits, which may weaken the statistical properties of digital chaotic ciphers, and then reduce the security of the communication systems. The dynamical degradation problem is one of the most severe impediments that have prevented chaotic communication progressing from theory to practical applications [30]. Moreover, in the information and communication security elds, system designers are faced with many challenges in both the trade-off cost/performance/power and architecture design. This is especially true for embedded system designs, often operating in non-secure environments, while at the same time being constrained by such factor as computational capacity, memory size and power consumption. Thus, one challenge is the design of hardware architecture in order to obtain the appropriate, best throughput rate, high randomness and large key space, and it will be much more useful in various chaosbased embedded applications. This paper proposes a disciplined and novel approach to efcient design and implement on a digital FPGA circuit of a new auto-switched chaos-based structural hardware architecture for generating digital chaotic models, and allowing complex attractors and best statistical properties. The purpose is to design new chaotic systems from an auto-switching technique to mix several distinct 3D chaotic attractors. The result is a very complex system that is more safer than previous proposed systems [3,26,1,4,28]. The interest of our solution is to propose a complex chaotic system allowing an unidentiable cipher key generator by an analysis of its attractors, while proposing optimized architecture and hardware implementation giving a very useful and attractive trade off between high speed, low area cost and secure data communications for embedded applications. Unlike perform the RungeKuttas numerical method to resolve the nonlinear differential equations model [32], we investigate and implement the Eulers numerical resolution to ensure and promise an efcient way to provide good performance in terms of throughput and resources cost required for highly secure communications. Our proposed logic Register Transfer Level (RTL) architecture is based on pipelined Eulers (EU) numerical method to resolve several 3D chaotic differential equations characterizing some chaotic systems. Therefore, this proposed RTL architecture can be used as more complex hard key chaotic generator in embedded self-synchronizing stream cipher encryptions. The rest of this paper is organized as follows. In Section 2, a description of the chaotic auto-switched model is presented. In this section, the basic dynamical properties of the presented auto-switched system are investigated. This section also describes our proposed hardware architecture to implement the proposed auto-switched chaotic system including ModelSim architectural simulation results. The hardware implementation results on Virtex-II Xilinx FPGA technology and performance evaluations are given in Section 3. Thereby, the performance and real-time measurements are reported and proved the feasibility and the efciency of our proposed chaotic auto-switched system. In Section 4, the chaotic dynamical behaviors of our new scheme is evaluated through statistical tests in order to prove that the proposed complex chaotic system exhibits truly random sequences suitable as cipher keys for the data encryption. Finally, Section 5 concludes the paper.

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2. Proposed digital auto-switched chaotic system Chaotic systems with multiple attractors have received increasing attention in recent years because they have the characteristics of more complicated evolution processes, high randomness and large key space, and it will be much more useful in various chaos-based communication systems such as cryptography. We propose a new auto-switched chaotic structural hardware architecture which provides multiple complex attractors and based on a chaotic switching Eulers numerical resolution [33] between different 3D quadratic autonomous chaotic systems. The aim of the approach is to investigate generated alternate chaotic models by exploring the switching of well know chaotic systems driven by chaos signals. Thereby, it results a promised high level security in digital chaotic communication while ensures the preservation of the chaotic regimes. To achieve this, we have simultaneously implemented in the logic hardware way and based on several digital chaotic systems which are auto-switched. In our case study, we demonstrate our original approach by using the four following 3D quadratic autonomous chaotic systems: Lorenz, L, Chen and Liu-Chen chaotic systems. 2.1. Modeling This subsection briey describes our proposed switching 3D chaotic systems for creating complex chaotic behaviors (complex attractors) with a best statistical properties. Hereafter, we consider the system of Lorenz is a well known example of a chaotic system. The Lorenzs three-variable model provides a practical test case with qualitatively realistic properties. It is represented by the following nonlinear equation system [34]:

8 > < x_1 ry1 x1 y_1 x1 z1 rx1 y1 > : _ z1 x1 y1 bz1

The standard parameter values for the Lorenzs chaotic attractor are: r 10; r 8=3 , b 28. Similarly, we consider the Chen system introduced by Chen in 1999 [35], a dual system of the Lorenz system, and described by:

8 > < x_2 ay2 x2 y_2 c ax2 x2 z2 cy2 > : _ z2 x2 y2 bz2

The Chen system presents chaotic behavior for the following value parameters: a 35; b 3; c 28. The transition system coined by L and Chen bridges the gap between the Lorenz and Chen systems called L system, and its dynamical equations are [36]:

8 > < x_3 ay3 x3 y_3 x3 z3 cy3 > : _ z3 x3 y3 bz3

This system displays a 2-scrolls chaotic attractor when a 36; b 3; c 20. Moreover, Liu and Chen [37] introduced the following Ordinary Differential Equation (ODE) system:

8 > < x_4 ax4 d1 y4 z4 y_4 cy4 d2 x4 z4 > : _ z4 bz4 d3 x4 y4

This nonlinear system presents a chaotic behavior when the following condition ab ac bc 0 is met. It can create a complex 2-scrolls attractor from the following value parameters: d1 1; d2 1; d3 1; a 5; c 10; b 3:4. The state variables of the proposed chaotic system are x; y and z (see Fig. 3). When the state variables of the switched system respects the following conditions (x > 0 and z > 0), the proposed switched system runs on a Lorenz system which is characterized by Eq. (1). When the conditions are x > 0 and z < 0, it runs on the Chen system (Eq. (2)). By contrast, when the conditions become x < 0 and z > 0, it runs on the L system (Eq. (3)) while when x < 0 and z < 0, it runs on the Liu-Chen system given by equation set (4). 2.2. Basic property analysis This subsection further investigates the dynamical behaviors of the proposed auto-switching chaotic system, including symmetry, dissipativity, equilibria and stability, Lyapunov exponents and bifurcation diagram. 2.2.1. Symmetry The subsystems of Eqs. (1)(4) are symmetrical about the z-axis for its invariance under the coordinate transform x; y; z ! x; y; z, but the proposed auto-switched system is not symmetrical about the z-axis. The symmetry property
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of the auto-switched chaotic system is changed by the state variables x and z, and the chaotic switching rule as despite in Fig. 3. 2.2.2. Dissipativity and existence of attractor For a dynamic system, the divergence of a 3-dimensional ow is dened by:

rV

_ _ @y _ @z @x @x @y @z

To ensure that the proposed auto-switched dynamic system is dissipative, it is required that rV < 0. For our dissipation analysis, we consider the following study cases:  For x > 0 and z > 0:

rV

_ _ @y _ @z @x a 1 b @x @y @z

In this plane, the proposed auto-switched system runs as Lorenz system with becomes:

r 10; r 8=3 and b = 28. The divergence

rV r 1 r 10 1 8=3 rV 41=3 < 0

 For x > 0 and z < 0:

rV

_ _ @y _ @z @x a c b @x @y @z

In this plane, the auto-switched system runs as Chen system with a 35; b 3 and c 28. The divergence becomes:

rV a c b 35 28 3 rV 10 < 0
 For x < 0 and z > 0:

rV

_ _ @y _ @z @x a c b @x @y @z

In this plane, the auto-switched system runs as L system with a 36; b 3 and c 20. The divergence becomes:

rV a c b 36 20 3 rV 19 < 0
 For x < 0 and z < 0:

rV

_ _ @y _ @z @x a c b @x @y @z

In this plane, the auto-switched system runs as Liu-Chen system with a 5; b 3:4 and c 10. The divergence becomes:

rV a c b 5 10 3:4 rV 8:4 < 0

Therefore, the above analysis proves that our auto-switched system is dissipative. The exponential contraction rate is calculated as follows:

dV rV V ) V V 0 erV ht dt

Each volume containing the system trajectory shrinks to zero as t ! 1 at an exponential rate of rV . System orbits are ultimately conned into a specic limit set of zero volume, and the asymptotic motion settles onto an attractor. Thereby, the existence of attractor is proved.
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2.2.3. Equilibria and stability The number of the equilibrium points and their stabilities determine the behavior of the system. The equilibria of the _ 0; 0; 0 in the ODE equations characterizing the switched system _; y _; z auto-switched system can be found by setting x and by solving for x; y; z. Therefore, we consider the following cases:  For x > 0 and z > 0:

8 > < 10y x 0 xz 8=3x y 0 > : xy 28z 0

The xed points are:

8 > < x 15; y 0; z 7 x 23:48528; y 8:48528; z 20 > : x 6:51471; y 8:48528; z 20

The point x; y; z 15; 0; 7 does not included in the plane (x > 0 and z > 0). Thus, the xed points are:

x 23:48528; x 6:51471;

y 8:48528; y 8:48528;

z 20 z 20

 For x > 0 and z < 0:

8 > < 35y x 0 7x xz 28y 0 > : xy 3z 0

The xed points are:

10

8 x 20; y 0; z 40 > > > > > < x 22:28942; y 2:28942; > x 18:85528 i1:98270; > > > > : x 18:85528 i1:98270;

z 38:25283 z 20 z 20

y 1:14471 i1:98270; y 1:14471 i1:98270;

11

There are two complex conjugate points 18:85528 i1:98270; 1:14471 i1:98270; 20 R R, which means that the xed points are:

x 20;

y 0;

z 40 y 2:28942; z 38:25283

x 22:28942;
 For x < 0 and z > 0:

12

8 > < 36y x 0 xz 20y 0 > : xy 3z 0

The xed points are:

13

8 > < x 17; y 0; z 10 x 24:74596; y 7:74596; z 10 > : x 9:25403; y 7:74596; z 10

The point x; y; z 17; 0; 10 does not included in the plane (x < 0 and z > 0). Therefore, the xed points are:

14

x 24:74596; x 9:25403;

y 7:74596; y 7:74596;

z 10

z 10

15

 For x < 0 and z < 0:

8 > < 5x yz 0 3:4y xz 0 > : 10z xy 0

16

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The xed points are:

8 x 20; y 0; > > > > > > < x 25:83095; x 25:83095; > > > > x 14:16904; > > : x 14:16904;

z 20 y 4:12310; z 27:07106 y 4:12310; z 12:92893 y 4:12310; y 4:12310; z 12:92893 z 27:07106 17

In summary, the proposed auto-switched system has eleven xed points which are: 23:48528; 8:48528; 20; 6:51471; 8:48528; 20; 20; 0; 40; 22:28942; 2:28942; 38:25283; 24:74596; 7:74596; 10; 9:25403; 7:74596; 10; 20; 0; 20; 25:83095; 4:12310; 27:07106; 25:83095; 4:12310; 12:92893; 14:16904; 4:12310; 12:92893; 14:16904; 4:12310; 27:07106. The above analyses show that the equilibrium points of the nonlinear system are saddle-focus nodes. 2.2.4. Lyapunov exponents and bifurcation analysis The Lyapunov exponents spectrum and the corresponding bifurcation diagram of state variable x with respect to parameter b are shown in Figs. 1 and 2, respectively. The other parameters of the four systems (Lorenz, Chen, L and Liu-Chen) are xed while b is variable. According to Fig. 1, the Lyapunov exponents of the auto-switched system are L1 1:272415; L2 0:208057 and L3 46:5341. The fractal dimension commonly known as Kaplan-Yorke dimension P P 1 DKY can be calculated, by detecting the largest integer j for the conditions ji1 ki P 0 and ji 1 ki < 0, as follows:

DKY j

Pj

jLj1 j

L i1 i

L2 j L1jL 3j

18

DKY 2

1:2724150:208057 j14:257718j

2:0746513:

Fig. 1. Spectrum of Lyapunov exponents of the parameter b.

Fig. 2. Bifurcation diagram of the new auto-switched chaotic system versus parameter b.

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The purpose of the bifurcation diagram is to display qualitative information about equilibria, obtained by varying parameters appearing implicitly in the new switched system. Fig. 2 gives the bifurcation diagram of the proposed auto-switched system versus parameter b. When we are scanning the various phase portraits for various values of the parameter b, we can see an abrupt appearance of chaotic behavior near b 0:1. If we increase b further, we nd many small windows corresponding to heteroclinic orbits. If we increase b further more then 3.5, the proposed switched system enter in the turbulence region. Since the values of state variables x; y and z vary randomly with the variable time t for simultaneously the three dimensional autonomous chaotic systems of Lorenz, L, Chen and Liu-chen, the auto-switched system transforms its behavior randomly from one to another among the four systems as t ! t 1 , leading to a more complex chaotic system with a complex chaotic behavior. In fact, the result of this switching allows to obtain new chaotic signals. Therefore, these results show and verify theoretically the chaotic property of the proposed auto-switched system. 2.3. Digital architecture Unlike the use of VHDL (VHSIC Hardware Description Language) automatic code generation by using available software tools (for example, DSP-Builder tool in Matlab/Simulink) [3,26,38,39,1,4,28], we design a data-path processing architecture with a structural description in the manner depicted by Fig. 3 and obtained with an optimal VHDL description. Indeed, the low level aspect of this method keeps the user closely the realities of the physical implementation. Thus, the result in terms of performance and density of resources used remains in of the designer reach. The proposed specic architecture realizes the real-time numerical resolution of the continuous nonlinear differential equations based on a nite data precision. One method for producing a numerical solution of an ODE is known as Eulers explicit or forward Eulers method [33]. Usually, a simple ODE is the explicit scalar rst-order initial value problem:

dy f x; y dx yx0 y0

19 20

Given a solution value xk ; yk , the Eulers method estimate the solution at the next abscissa by the following equation:

Fig. 3. Pipelined and switched RTL architecture of the proposed digital auto-switched chaotic system.

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yk1 yk hf xk ; yk

21

where the step size is denoted by h. An overview of the proposed (RTL) logic architecture for digital implementation of the proposed Switched Euler (SEU) method is given in Fig. 3. It should be noted that the continuous chaotic signals are real, which is why the embedded proposed architecture treats a nite resolution of numbers using a binary representation. This logic implementation allows to solve simultaneously the three dimensional autonomous chaotic systems of Lorenz, L, Chen and Liu-chen from the pipelined RTL architecture. The proposed architecture consists of the structural feedback of the three main blocks denoted as F, G and H. These three functional units realize the results of the output of the switching rule between the chaotic generators through three multiplexers placed at the beginning and the end of the architecture as depicts in Fig. 3. Therefore, we can set Eqs. (1)(4) as follows:

8 > < F 1 ry1 x1 G1 x1 z1 rx1 y1 > : H1 x1 y1 bz1 8 > < F 2 ay2 x2 G2 c ax2 x2 z2 cy2 > : H2 x2 y2 bz2 8 > < F 3 ay3 x3 G3 x3 z3 cy3 > : H3 x3 y3 bz3 8 > < F 4 ax4 d1 y4 z4 G4 cy4 d2 x4 z4 > : H4 bz4 d3 x4 y4

22

23

24

25

The implemented switching rule varies with the parameter sw. The switching rule is dened by the following logic conditions:

8 F1 > > > <F 2 F > F3 > > : F4 8 G1 > > > <G 2 G > G3 > > : G4 8 H1 > > > <H 2 H > H 3 > > : H4

if sw 00 if sw 01 if sw 10 if sw 11 if sw 00 if sw 01 if sw 10 if sw 11 if sw 00 if sw 01 if sw 10 if sw 11 28 27 26

2.4. Simulation results The proposed architecture has been simulated for the correct functional operation with test vectors returned by a software implementation. This validation consists to model and describe directly the (SEU) method with the VHDL. For the proposed digital implementation, we have adopted a xed point representation of real data on 32 bits (16Q 16) i.e. all data are xed point format with 16 bits integer and 16 bits fraction. To test the effectiveness of our solution, we have simulated our RTL architecture of the proposed chaotic switched generator with ModelSim simulator tool [40]. The results obtained are presented in Figs. 4 and 5.
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Fig. 4. Chaotic signal results obtained from ModelSim simulation of the proposed pipelined and switched RTL architecture.

Fig. 5. Complex chaotic attractors obtained from the ModelSim simulation results (data coding with 32 bits wordlength).

3. Real-time FPGA implementation The RTL description of the proposed architecture has been implemented on Xilinx Virtex-II FPGA (2VP30FFG896-7) [41] through the Virtex-II Pro Development platform [42] using VHDL structural description. ISE 10.1i of Xilinx [43] tool has been used for this digital implementation allowing to obtain the logic resource requirements and the associated real-time constraints. The synthesis results after place and route show the performance analysis of our implementation in Table 1. This table depicts the hardware resources in terms of the logic Slice or the Slice Flip-Flops and LUTs numbers and the power consumption. The performance of our RTL hardware architecture depend on the congured size of the xed-point data. It results
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M.S. Azzaz et al. / Commun Nonlinear Sci Numer Simulat xxx (2013) xxxxxx Table 1 FPGA implementation results with a Virtex-II-Pro FPGA for the proposed alternate auto-switched chaotic system (XC2vp30ff896-7). Area slices Number of slice ip ops Number of 4 input LUTs Number of MULT18X18s Maximum frequency (MHz) Throughput (Mbps) Latency (ns) Mbps/slice Power (mW) 1695 622 3251 78 38.86 1240 51.5 0.73 3.21

that our logic implementation on a Xilinx Virtex-II [42] device requires only 1695 CLB-Slices, 78 multipliers and no block RAMs. Unlike the approach presented in [3,26,38,39,1], our proposed approach using xed-point arithmetic allows a very useful and attractive trade off between high speed, low area cost and data transmission security. To evaluate the performance of the proposed auto-switched chaotic system, some evaluation metrics are considered. The metrics used for this evaluation are the Throughput rate and the Time latency. The Throughput rate is dened as the number of bits key in a unit of time for a stream key. In our case and from the performance results (see Table 1), we have achieved a maximal Throughput of 1.24 Gbps. Similarly, we have obtained a Time latency of 51.5 ns. Furthermore, our implementation requires only 3.21 mW of power consumption. These implementation results demonstrate that the proposed auto-switched chaotic generator can be implemented in real-time in optimized way on FPGA technology while enhancing the complexity of a cipher key chaotic generator suitable for increase the robustness of data encryption. The x; y and z real-time chaotic signals obtained from the proposed auto-switched chaotic system after digital implementation are given in Fig. 6(a)(c), respectively. In practice, once the chaotic signals (x, y and z) with 32 bits wordlength are obtained, they are truncated on 18 bits and converted to analog format using a Digital to Analog converter (DAC) and this process is repeated. Then, the real-time chaotic signals obtained in analogue form for real measurements at the output of the DAC are visualized on an oscilloscope. Note that our proposed architecture offers two different manners to use the obtained

Fig. 6. Real-time measurements of the auto-switched chaotic signals suitable as cipher key generators (vertical scale = 1 volt and the base time = 1 ms (a), (b) and 2.5 ms (c)).

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Fig. 7. Real-time measurements of the obtained digital auto-switched chaotic attractors (data coding with 18 bits wordlength).

Table 2 Statistical test results. Test terms Frequency test (v1 ) Serial test (v2 ) Poker test (v3 ) Our proposed system 0.192 1.076 2.037 9.120 21.232 46.903 1.876 6.791 10.205 11.789 No long run 0.290 System proposed by Qi et al. [3] 1.6200 1.9820 9.3699 12.518 32.528 59.845 9.2380 10.754 11.932 12.257 No long run No test Required values <3.8415 <5.9915 <14.067 <24.996 <44.985 <82.529 <9.4880 <12.592 <15.507 <18.307 No long run 1:96 < v5 < 1:96 m3 m4 m5 m6 k3 k4 k5 k6 k > 34 Parameters

Runs test (v4 )

Autocorrelation test (v5 )

real-time chaotic signals. Indeed, it permits to use them in their analog form at the output of the DAC or in their digital form directly at the output of the FPGA circuit. The attractors of the designed system in the phase planes xy and xz are given in Fig. 7(a) and (b), respectively. These Snapshots are captured from the oscilloscope [44]. 4. Statistical tests A large number of statistical tests and whole test suites have been proposed to assess the statistical properties of Random Number Generation (RNG). In this section, we present the behavioral analysis through test results of the PR sequence generator obtained from the proposed auto-switched chaotic system. Here, we consider a binary sequence of length n 20; 000 bits generated by our proposed switched model, which is used as outputs from the proposed auto-switched chaotic PR sequence generator subject to each of the tests. Five statistical tests are used for determining whether the binary sequence possesses some specic characteristics that a truly random sequence exhibit. These ve tests are the Mono bit, Poker, runs, Long run and autocorrelation tests [45]. If one of the tests fails, the proposed auto-switched chaotic generator fails. The results of all ve tests for our obtained sequence are shown in Table 2. From these results, we can see that the proposed generator successfully passes all the statistical tests. Moreover, the statistical properties of the proposed auto-switched chaotic PR sequence are better than the switched chaotic PR sequence presented by Qi et al. [3]. Therefore, these results demonstrate that the proposed alternate chaotic model is very useful for the consideration of reducing negative inuence of dynamical degradation due to digital hardware implementation while preserving the chaotic regimes. 5. Conclusion This paper proposes a new approach for designing alternate digital auto-switched chaotic systems suitable and useful for highly secure communications and embedded applications. The proposed chaotic system is based on chaos switching rule between several digital chaotic systems and promises new complex chaotic behaviors with multiple attractors. To demonstrate the interest of our approach, we have successfully implemented in the FPGA technology a pipelined switched Eulers
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numerical resolution which switches between multiple resolved 3D continuous nonlinear differential equations. Our RTL architecture based on a xed point data representation solves the problem of the nite precision due to the digital implementation. The hardware implementation results provide a good trade-off between high security, performance and hardware resources (low power and area cost) and take into account the consideration for reducing negative inuence of dynamical degradation. Our chaotic system generates complex attractors and provides truly random keys characterized by good statistical proprieties, high throughput rate and good performance in term of resources required for real-time secure embedded applications. Indeed, experimental test results obtained of the designed chaotic generator clearly demonstrate that the generated keys exhibit attractive statistical properties and robustness in front of several tests like Mono bit, Poker, runs, Long run and autocorrelation tests. It results that the proposed chaotic system allows to generate a large cipher key space. Moreover, these results provide further understanding on the robust chaotic ability of digital chaotic systems. Therefore, the proposed scheme is useful for complex chaotic cipher key generation and suitable for the design fast and secure symmetric data encryptions, while increasing its resistance to various attacks such as the statistical and key analysis attacks. For instance, the proposed auto-switched chaotic system can replace the low complex switched chaotic system [46] as a new and efcient way to deal with the problem of fast and highly secure symmetric image encryption scheme. Therefore, the real-time results obtained validate the proposed hardware solution applied in the digital chaos generation and allows wide applications of the complex random systems in the eld of real-time low-cost secure embedded communications (video, audio, image, internet, etc.). Finally, our technique exhibits attractive performance and can be extended for an auto-switching rule between several n-dimensional continuous chaotic systems in order to the design and investigation of new complex chaotic attractors from existing chaotic generators. References
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Please cite this article in press as: Azzaz MS et al. A new auto-switched chaotic system and its FPGA implementation. Commun Nonlinear Sci Numer Simulat (2013), http://dx.doi.org/10.1016/j.cnsns.2012.11.025