Using System Generator to program Xilinx Spartan I

Introduction The parallel computing power of the field programmable gate array (FPGA) is extremely useful in the modern world of demanding applications like digital signal processing and video editing. However, configuring this power can be difficult. So MatLab has created a package called System Generator which allows Xilinx chips to be programmed with the common MatLab programming environment Simulink. This tutorial will walk you through the basic steps of using Simulink to program a Xilinx III starter board. Overview To program the FPGA, you will be using two distinct software packages in Matlab and Xilinx ISE. Matlab is the software where the brunt of the programming will take place, and ISE is where the program will be configured to run on the FPGA. The main bridge between the two packages is System Generator which is added as a part of Matlab to convert the Simulink math code to VHDL code that the ISE recognizes. Simulink The starting place for this programming progress is in MatLab. So once the programming package is open, create a new model by clicking the File tab and dragging to the New tab and then the Model Tab.

Once you have a new model, click on the Simulink icon and the Simulink GUI pops up.

The System Generator has its own Simulink models that are in three tabs called the Xilinx blockset.

The first thing to add to any new model is the System Generator block. This is what tells MatLab that you are using this project to program a FPGA. The block is found in the Xilinx block-set under basic elements. It can just be dragged over to the new model as shown.

The next key parts of the model are the Gateway in and out blocks. This is what allows actual inputs and outputs to be added to the project. They are in the same location as the System Generator.

The actual pins the gateways correspond to will be configured in Xilinx ISE, but the actual number of bits the gateway will be is configured in Matlab. To do this, just double click on the gateway in icon in the model and the following GUI pops up.

The main areas of concern are the output type. So depending on the application, the number of bits will be chosen here. The binary point is not crucial for simple programming, but it has to be smaller then the number of bits. For testing purposes, the gateway will be configured to 1 bit input with the binary point at 0. Once the model has the System Generator and gateway pins, it is ready for programming. For this tutorial, a simple inverter will be created. So the inverter gate is located in the Xilinx block-set and is dragged to the model just like the gateway blocks. The blocks are then connected simply by dragging wire between the input and outputs of the blocks.

Then once the model is built and the gateways are configured, the VHDL code needs to be created. This is accomplished by double clicking the system generator icon in the model.

Then click generate and the code will be created in the directory specified (the clock pin may be set here if desired = T9).

Xilinx ISE 8.2i Now that the code has been created for the program, all that left to do it put it on the chip. To do this, a new project must be created in Xilinx ISE. This is accomplished by clicking on the ISE project file generated by System Generator.

Once the file is open, only thing that needs to be done is to assign the pins to the output ports on the FPGA board. So click to expand (+) the user constraints in the processes window and double click on create area constraints.

This will start to assemble the program, but will ask to add a UCF file halfway though implementing the design. After clicking yes, the PACE window will open as follows.

In this window, al the pins from the Simulink gateways show up as I/O pins. To route them out of the board, all that need to be done is type in the I/O pin number (the pins numbers can be found written on the board for switches and LEDs and in the users guide pg 49-51 for the I/O connectors). Set the input pin to K13 and the output to K12. From this point, the project is complete and ready to be assembled and implemented as a normal Xilinx program. To do this expand Generate Programming File under the Processes tab and double click on Configure Device (impact). Click FINISH on the pop-up Welcome to IMPACT. Two Xilinx icons appear on the screen along with the Assign New Configuration File pop-up. Open filename_cw.bit. For the next pop-up just cancel. Now highlight the first Xilinx icon and right click and Program. This should download your program to the Xilinx board. Demonstration the operation of your program with SW7 and LD0. See Xilinx tutorial for more info. Weve created companion boards to go with the Xilinx boards. Since the FPGA only has digital inputs and outputs separate A/D and D/A chips are needed in order to work with analog signals.

On the bread boards are 2 12 bit A/D converters and 1 D/A converter. The data sheets for each are available from the lab website. Pin 10 is the input to the A/D and pin 16 is the output of the D/A. The goal of the next part of the lab is to determine how fast the boards are sampling and observe the aliasing effects. Copy from the wismer/public/ELEC472/SPRING07/lab5 directory the ADC_DAC.mdl and the adc_dac_cw.ucf files. Open the .mdl file in Simulink. These are the basic blocks to interface the Xilinx boards with A/D, D/A chips. Click on some of the blocks to get a sense of how the gateways, inputs and outputs are connected. In simulink generate an .ISE file by double clicking the System Generator block and clicking Generate. In the current directory double open the .ISE file by double clicking on it. After the project has opened you need to include the .ucf file which has the mapping from the A/D bits to the Xilinx pins. In Sources expand filename_cw and in Processes click Add Existing Source and open adc_dac_cw.ucf. Now you can Generate Program File and Configure Device (iMPACT) as before. Once youve downloaded the program into Xilinx connect your signal generator to the A/D input. Show the input and output on your scope. Vary the frequency of the sine wave until aliasing starts to occur. How fast does your system sample? Increase the frequency above the sampling frequency to observe the effects of aliasing. In simulink modify the system by amplifying your signal by 2. Use the multiplication block. Demonstrate this system to me. Special thanks to Jake Krizan, 2008