Queens Power Group www.QueensPowerGroup.

com

Topology and Analysis of a New Resonant Gate Driver

Presented and Authored By: Zhiliang Zhang Co-authors: Zhihua Yang, Sheng Ye and Dr. Yan-Fei Liu

9/3/2006

Outline Introduction Proposed Resonant Gate Driver and Operation Loss Analysis and Optimization Design Experimental Results Conclusion

9/3/2006

 Introduction Proposed Resonant Gate Driver and Operation Loss Analysis and Optimization Design Experimental Results Conclusion

9/3/2006

Conventional MOSFET Driver

MOSFET Driver Power MOSFET Hard Switching Waveforms

Discharge Path

Switching Loss

MOSFET, or BJT transistors

Gate Loss

Pgate = QgVGS f S

Pswitching

VDS I D (t rise + t fall ) f s 2

4

9/3/2006

Switching Loss: Common Source Inductance

iDL LD VD iD CDS

Common source inductance

M1 RG G VDrive CGS S LS D CGD

gfs(vGS-Vth)

Buck converter with parasitic inductors

Equivalent circuit of MOSFET switching transition (turn-on)

9/3/2006

Switching Loss: Common Source Inductance

Ls=0
20

Ls=2nH

iD (A)

15

9ns
vDS (V) vGS (V)

18ns

10

10

20

30 Time (ns)

40

50

VD=12V, IL=20A, fs=1MHz, MOSFET: IRF7821

Switching loss increases significantly due to common source inductance!

9/3/2006 6

Resonant Gate Drive Techniques

Limitations of voltage source driver:
No gate charge energy recovered Low switching speed and high switching loss due to common source inductance

Resonant gate driver techniques:

9 Many good circuits proposed since 1990s, but generally unused 9 Existing methods emphasize gate energy savings, but ignore potential switching loss savings
9/3/2006 7

 Introduction Proposed Resonant Gate Driver and Operation Loss Analysis and Optimization Design Experimental Results Conclusion

9/3/2006

Proposed Dual Channel HighSide and Low-Side Gate Driver

Q1 Vin Cg1 Cg2 Lf Q2 Cf RLd

+
Vo

Vc S1 D1 Lr iLr S3 Cb S4 S2

C1

Resonant Gate Driver

Key waveforms

9/3/2006

Before t0
Q1 Vin Cg1 Cg2 Lf Q2 Cf RLd

+
Vo

Vc S1 D1 Lr iLr S3 Cb S4 S2

C1

Key waveforms

9/3/2006

10

Turn-off Q2: [t0, t1]

Q1 Vin Cg1 Cg2 Lf Q2 Cf RLd

+
Vo

Vc S1 D1 Lr iLr S3 Cb S4 S2

C1

Key waveforms

9/3/2006

11

Turn-on Q1: [t1, t2]

Q1 Vin Cg1 Cg2 Lf Q2 Cf RLd

+
Vo

Vc S1 D1 Lr iLr S3 Cb S4 S2

C1

Key waveforms

9/3/2006

12

 Introduction Proposed Resonant Gate Driver and Operation Loss Analysis and Optimization Design Experimental Results Conclusion

9/3/2006

13

Driver Loss Analysis

The conduction loss of S1-S4 Pcond _ s1 s 4 = 2 I s1 _ RMS 2 Rds (on) + 2 I s 2 _ RMS 2 Rds (on)
Rds(on) is the on-resistance of S1-S4

The resonant inductor loss Pind = Pcopper + Pcore The loss of MOSFET mesh resistance RG

PRG = 2 RG1I 2 Lr _ pk t sw1 f s + 2 RG 2 I 2 Lr _ pk t sw2 f s

tsw1 and tsw2 are the switching time, ILr_pk is the peak current of resonant inductor

The loss of gate charges of switches S1-S4

PGate = 4 Qg _ s Vgs _ s f s
9/3/2006 14

Vcc Selection of Resonant Gate Driver

Vc=5V Vc=12V

Vc=12V Preferred

Control FET& Synchronous FET

Vin=12V; Io=20A; fs=1MHz; Q1: IRF7821(30V, RDS(on)=9m@VGS=6V); Q2: FNS7088(30V, RDS(on)=3.5m@VGS=6V); S1-S4: FDN335N(20V N-channel, RDS(on)=0.07@VGS=4.5V); Lr=2.2uH.

9/3/2006

15

Gate Charge Current IG Selection

1. Switching loss Pswitching(IG) as function of driven current IG is calculated

IG=1A

2. Total loss Pcircuit(IG) of the resonant gate drive circuit as function of driven current IG is calculated

3. The Objective function is established by adding switching loss and the resonant gate driver loss together

F ( I G ) = Pcircuit ( I G ) + Pswitching ( I G )

9/3/2006

16

Conventional Driver vs. Resonant Driver

Loss (W)

on

of f

uc tio

ci ru

Tu r

n-

Tu r

Co nd

RG

Vin=12V; Vo=1.5V; Io=20A; fs=1MHz; Control FET: IRF7821(30V, RDS(on)=9m@VGS=6V) Syn FET: FNS7088 (30V, RDS(on)=3.5m@VGS=6V)
9/3/2006 17

G at

e/

Bo

dy

di o

n-

de

 Introduction Proposed Resonant Gate Driver and Operation Loss Analysis and Optimization Design Experimental Results Conclusion

9/3/2006

18

Experimental Results: Fast Switching Speed

Fast speed No miller plateau

Gate drive signal and drain-source voltage (control FET)

Resonant inductor current and drainsource voltage (Synchronous FET)

Vin=12V; Io=20A; fs=1MHz; Control FET: IRF7821;Syn FET: FNS7088

9/3/2006 19

Experimental Results: Reduced Dead Time

Resonant gate driver

Conventional gate driver (TPS2832 TI)

Vin=12V; Vo=1.5V; Io=20A; fs=1MHz; Control FET: IRF7821;Syn FET: FNS7088

9/3/2006

20

Experimental Results: Loss Savings

Ploss (W)

4.5W Loss Reduction @Vo=1.5V/20A(15% of the output power)

9/3/2006 21

 Introduction Proposed Resonant Gate Driver and Operation Loss Analysis and Optimization Design Experimental Results Conclusion

9/3/2006

22

Conclusion
A New Resonant Driver Proposed
9 9 9 9 9 9 Switching Loss Reduction Immunity to Common Source Inductance Gate Energy Recovery ZVS for Driver Switches High Cdv/dt Immunity (Low Impedance) Reduced Body Diode Conduction Time

Loss Analysis and Design Procedure Presented 4.5W Loss Reduction @Vo=1.5V/20A/1MHz(15% of output power)
23

9/3/2006

Thank You For Your Time

Other Resonant Gate Drive Material at:

www.QueensPowerGroup.com

9/3/2006

24