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CHAPTER 7: SEQUENTIAL CIRCUITS FLIP-FLOPS FLIP FLOPS, REGISTERS, REGISTERS AND COUNTERS

What will we learn?

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Logic circuits that can store information

Latches, which store a single bit Flip-Flops, which store a single bit Registers, which store multiple bits

Shift registers i t Counters Design Examples

Sequential Circuits
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Combinational Circuits

circuits without feedback output = f (current ( inputs) )

Sequential Circuits

circuits with feedback output = f (current inputs, past inputs, past outputs) how can we feed the past inputs and outputs into the circuits?

b i f basis for b building ildi memory i into l logic i circuits i i

Circuits with feedback

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How to control feedback?

what h t stops t values l f from cycling li around d endlessly dl l

x1 x2 x3 . . . Sequential Circuit . . .

y1 y2 y3

xn

ym

Control of an alarm system

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Sensor Reset

S t Set Memory element On Off Alarm

the simplest p case of a sequential q circuit

Alarm is on when the sensor generates the Set signal in response to some undesirable events Once the O h alarm l i is on, i it can only l b be turned d off ff manually ll through h h a reset button

Memory is needed to remember that the alarm has to be active until the reset signal arrives

A simple memory element

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Th most rudimentary The di memory element l

Two inverters form a static memory cell

Assume A=0 and B=1 B=1, then the below circuit will maintain these values indefinitely (as long as it has power applied) The state is defined by the value of the memory cell Two states
A B

How to get a new value into the memory cell?

selectively break feedback path load new value into cell

A controlled memory element

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Load

Data TG1

Output

TG2

A memory element with NOR gates

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C Construct t t a memory cell ll using i ordinary di l logic i gates t

Two NOR gates are connected in cross-coupled style Basic Latch

Two inputs

Set Reset
Reset Set Q

A basic latch built with NOR gates

9 R Qa S 0 0 1 1 R 0 1 0 1 Qa Qb 0/1 0 1 0 1/0 (no change) 1 0 0

S (a) Circuit t1 1 R 0 1 S 0 1 t2 t3

Qb

(b) Truth table or characteristic table t4 t5 t6 t7 t8 t9 t 10

There will be an oscillation

Qa

? 0 1 ? 0 Time (c) Timing diagram

Qb

Timing Waveform
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R S R Q

Timing Waveform
Reset Hold Set Reset

\Q

Set
100

Race

R S Q \ Q

Forbidden State

Forbidden State

State Behavior of R-S R S Latch

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S R Q 0 0 hold 0 1 0 1 0 1 1 1 unstable
Truth Table Summary of R-S Latch Behavior

QQ 01

QQ 10

QQ 00

QQ 11

Theoretical R-S R S Latch State Diagram

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State Diagram

SR = 00, 01 SR = 1 0 QQ 01

SR = 00, 10

state: possible values transitions: changes based on inputs

QQ 10 SR = 0 1 SR = 0 1 SR = 1 0 SR = 11 SR = 1 1 QQ 00

SR = 1 1

SR = 0 1 SR = 0 0 SR = 0 0, 11 QQ 11

SR = 1 0

Observed R-S R S Latch Behavior

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SR = 00 00, 01 SR = 1 0 QQ 01

SR = 00, 10

QQ 10 SR = 0 1 SR = 0 1 SR = 1 0 SR = 11 SR = 1 1 QQ 00

SR = 1 1

SR = 0 0

SR = 0 0

Very difficult to observe R-S Latch in the 1-1 state Ambiguously returns to state 0-1 0 1 or 1 1-0 0 A so-called "race condition"

R-S R S Latch Analysis

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Truth T th Table: T bl Next State = F(S, R, Current State) R-S R S Latch Revisited S R Qt Q+
0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 x x

Derived K-Map:
SR Q( t ) 0 00 0 1 01 0 0 R 11 X X S 10 1 1

hold reset set 0 1

Characteristic Equation: Q+ = S + R Q t

not allowed

S R Q

R-S Latch

Q+

Problems of R-S R S Latch

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The slightest glitch on R or S could cause

change in value stored

R-S Latch has transparent outputs

Transparent outputs : when the memory elements outputs immediately change in response to input changes

Want to control when R and S inputs have

effect on value stored

E bl Si Enable Signal l( (or clock l k signal) i l) R and S inputs are active only when Enable = 1 Gated Latches or Level sensitive latches

Gated SR latch
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Control C t l when h R and dSi inputs t matters

\S \Q

the latch can be modified to respond to th i the input t signal i l S and d R only l when h Enable =1 output is changing

\R Q \enb

output is stable

Set

Reset

Gated SR Latch
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Gated SR latch with NAND gates

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S Q Clk Q R

Problems of the Gated S/R Latches

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1. Forbidden State and Race condition

How to eliminate the forbidden state and race condition When S=R=1, Q = Q = 0 (forbidden state) Oscillation (Race condition)

D-type Latch JK-Latch (toggling) The output toggles forever when J=K=1

2. When cascading level-sensitive Latches

Master/Slave F/Fs Edge-triggered F/Fs

1 How to eliminate the forbidden state? 1.

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G t d D-latch Gated D l t h

eliminate the troublesome situation where S=R=1

How to eliminate the forbidden state? contd

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Idea: use output feedback to guarantee that R and S are never both one J, K both one yields toggle J-K J K Latch J(t) K(t) Q(t)
0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1

R R-S latch

\Q

\Q

Q+
0 1 0 0 1 1 1 0

hold reset set toggle 0 1 Characteristic Equation: Q+ = Q K + Q J

J-K Latch: Toggles forever in the toggle mode

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Set

Reset
100

Toggle gg

J K Q \Q

Oscillation

Toggle Correctness: Single State change per clocking event Solution: Master/Slave Flipflop

Master/Slave J J-K K Flipflop

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Master Stage
K R Delay (d) S \Q R-S Latch Q P \P

Slave Stage
R R-S Latch S Q Q \Q \Q

Clk

Sample inputs while clock high

1's Catch

Sample inputs while clock low

Uses time to break feedback path from outputs to inputs!

Set J Reset Toggle 100

Delay (d)

K Clk P \P Q \Q Master outputs Slave outputs

Correct Toggle Operation

2 When cascading Latches 2.

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Qa

R S

Q Q

R S

Q Q

Qb

S clock

How to stop changes from racing through chain? h i ?

need to be able to control flow of data from one latch to the next move one latch per clock period have to worry about logic between latches that is too fast

Master/Slave D Flip Flip-Flop Flop

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Master D Clock D Q Qm Slave D Q Qs

D
Q Q

Q Q

Clk Q

Clk Q

(c) Graphical symbol (a) Circuit

Clock D Qm Q = Qs

(b) Timing diagram

D Clock Qa Qb

Q Q

Q Q

Positive-edge-triggered Positive edge triggered D flip flip-flop flop

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D 1 1 D D

P3

hold
P1

1
5

0
Clock

Clock = 0 Output of gate 2 and 3 are high -> P1,P2 high Output is maintained Clock = 1 P3 and P4 are transmitted through gate 2 and 3 to cause P1 = D and P2 = D. hold state This sets Q = D and Q = D Q P3 and P4 must be stable when the clock goes from D 0 to 1. After that, the changes in D have no effect.

=0 =1 1

D
3

P2 D

D
D Q

1 D

D
4 P4

D1

Clock

(a) Circuit

(b) Graphical symbol

Comparison of level-sensitive and edge-triggered D storage elements

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D Clock

D Q Clk Q D Q Q D Q Q

Q a Q a Q b Q b Q c Q c

Clock D Q a Q b Q c

(b) Timing diagram

(a) Circuit

Master-slave D flip-flop with Clear and Preset

28 Preset D Clock

0
Q

1 1 0

1
Q

1
Preset

Clear (a) Circuit Clear

Q Q

(b) Graphical symbol

Positive-edge-triggered D flip-flop with Clear and Preset

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Preset

Q Preset Clock D Q Clear Q Q

D Clear

(b) Graphical symbol

(a) Circuit

Synchronous reset for a D flip-flop flip flop

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Clear D Clock

Q Q

Q Q

T Flip-Flop Flip Flop

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T D T Q Q Q Q 0 1

Q(t + 1) Q(t ) Q(t )

Q Q

(b) Truth table

Clock

(c) Graphical symbol

(a) Circuit

Clock T Q

(d) Timing diagram

Realizing JK flip-flop flip flop with D flip-flop flip flop

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J D K Clock Q Q Q Q

(a) Circuit
J K Q ( t + 1) 0 0 1 1 0 1 0 1 Q (t) 0 1 Q (t ) J K Q Q

(b) Truth table

(c) Graphical symbol

Last time
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M Memory Cell C ll

SR Latch Glitch problems

Transparent output - the memory elements outputs immediately change in response to input changes Gated SR Latches (Enable signal or clock)

Problems of SR Latches

Another problems

Forbidden state and racing gp problem D-latches, , JK-latches When cascading latches How to stop changes from racing through chain? Mater slave F/Fs and Edge triggered F/Fs (clock signal) Memory elements change their states in response to a clock signal We call these Synchronous systems

Today
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Timing Methodologies

To guarantee the correct operation when cascading the M Memory blocks bl k

Comparison of Latches and F/Fs Registers store multiple bits

Storage registers Shift registers

Counters count events

Asynchronous counters Synchronous counters

Timing Methodologies
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Set of rules for interconnecting components and clocks

When followed, guarantee proper operation of system

Proper operation:
(1) The correct inputs, with respect to time, are provided to the FFs (2) no FF changes more than once per clocking event

Approach depends on building blocks used for memory elements

For systems with latches: Narrow Width Clocking Multiphase Clocking (e.g., Two Phase Non-Overlapping) For systems with edge-triggered flip-flops: Single Phase Clocking

Definition of Terms
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Tsu Input

Th

Clock: Periodic Event, causes state of memory element to change rising edge, falling edge, high level, low level Setup Time (Tsu) Minimum time before the clocking g event by y which the input must be stable Hold Time (Th) Minimum time after the clocking event during which the input must remain stable

Clock

There is a timing "window" around the clocking event during which the input must remain stable and unchanged in order to be recognized

Setup and Hold times for Latches

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t su th Clk D Q

tplh

tphl

Comparison of latch and F/F

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7474
D Q

Edge triggered device sample inputs on the event edge Transparent latches sample inputs as long as the clock l k is i asserted t d

Clk Positive edge-triggered flip-flop p p

Timing Diagram:
D

7476
D C Q

Clk Q 7474 7476

Clk Level-sensitive latch

Bubble here for negative edge triggered device

Behavior the same unless input changes while the clock is high

Comparison of latches and F/Fs

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Input/Output Behavior of Latches and Flipflops Type unclocked latch level sensitive latch positive edge flipflop negative edge flipflop master/slave flipflop When Inputs are Sampled always clock high (Tsu, Th around falling clock edge) clock lo-to-hi transition (Tsu, Th around rising clock edge) clock hi-to-lo transition (Tsu Th around (Tsu, falling clock edge) clock hi-to-lo transition (Tsu, Th around falling clock edge) When Outputs are Valid propagation delay from input change propagation delay from input change propagation delay from rising edge of clock propagation delay from falling edge of clock propagation delay from falling edge of clock

Typical Timing Specifications: Flipflops vs. Latches

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74LS74 Positive Edge Triggered D Flipflop

D

Tsu 20 ns

Th 5 ns Tw 25 ns Tplh 25 ns 13 ns

T su 20 ns

Th 5 ns

Setup time Hold time Clk Minimum clock width Propagation delays (low to high, high to low, max and d typical) t i l) Q

T phl 40 ns 25 ns

All measurements are made from the clocking event that is, the rising edge of the clock

Typical Timing Specifications: Flipflops vs. Latches

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74LS76 Transparent Latch

D

T su Th 20 5 ns ns Tw 20 ns Tplh C Q 27 ns 15 ns T plh D Q 27 ns 15 ns

Tsu 20 ns

Th 5 ns

Setup time Hold time Minimum Clock Width Propagation Delays: high to low, low to high, maximum, typical data to output clock to output

Clk

T phl C Q 25 ns 14 ns T phl D Q 16 ns 7 ns

Measurements from falling clock edge or rising or falling data edge

Timing Methodologies
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Two F/Fs are cascaded New value to first stage while second stage obtains current value of first stage Shift Register

IN

Q0

Q1

C Q CLK

C Q

Cascaded Flipflops and Setup/Hold/Propagation Delays

100 In

Correct Operation, assuming i positive ii edge triggered FF

Q0 Q1 Clk

Cascaded Flipflops and Setup/Hold/Propagation / / Delays

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Why this works: Propagation delays far exceed hold times; Clock width constraint exceeds setup time This guarantees following stage will latch current value before it is replaced by new value Assumes infinitely fast distribution of the clock
In Tsu 20 ns Q0 T plh 13 ns T plh 13 ns Tsu 20 ns

Timing Ti i constraints t i t guarantee proper operation of cascaded components p

Q1

Clk Th 5 ns Th 5 ns

The Problem of Clock Skew

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Correct behavior assumes next state of all storage g elements determined by all storage elements at the same time Not possible in real systems! logical clock driven from more than one physical circuit with timing behavior different wire delay to different points in the circuit Effect of Skew on Cascaded Flipflops:
FF0 samples IN FF1 samples Q 0 100

In Q0 Q1 Clk1 Clk2

CLK2 is a delayed version of CLK1

Original State: Q0 = 1, Q1 = 1, In = 0 Because of skew, next state becomes: Q0 = 0, Q1 = 0, not Q0 = 0, Q1 = 1

Design Strategies for Minimizing Clock Skew

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Typical propagation delays for LS FFs: 13 ns y( (on the order of 13 ns) ) for skew to Need substantial clock delay be a problem in this relatively slow technology Nevertheless, the following are good design practices: 9 distribute clock signals in general direction of data flows 9 wire carrying the clock between two communicating components should be as short as possible 9 for multiphase clocked systems, distribute all clocks in similar wire i paths; th this thi minimizes i i i the th possibility ibilit of f overlap l 9 for the non-overlap clock generate, use the phase feedback signals g from the furthest point p in the circuit to which the clock is distributed; this guarantees that the phase is seen as low everywhere before it allows the next phase to go high

Choosing a Flipflop
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R S Clocked Latch: R-S

used as storage element in narrow width clocked systems its use is not recommended! however, fundamental building block of other flipflop types versatile building block can be used to implement D and T FFs usually requires least amount of logic to implement but has two inputs with increased wiring complexity because of 1's catching, never use master/slave J-K FFs edge-triggered varieties exist

J-K Flipflop: (historically popular, but now not used)

D Flipflop: minimizes wires, much preferred in VLSI technologies

simplest design technique best choice for storage registers

T Flipflops: don't really exist, constructed from J-K FFs Preset and Clear inputs highly desirable!!

usually best choice for implementing counters

Registers
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Collection of Flip-Flops with similar controls and logic

stored values somehow related share clocks, reset, and set lines similar i il l logic i at t each h stage t

Ex Examples l

storage registers shift registers counters

Storage Register
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+ \clr
Q3
DS

Group of storage elements read/written as a unit 4-bit register constructed from 4 D FFs Shared clock and clear lines Schematic Shape

D3

Q2
DS

171
12 CLK 13 CLR Q3 Q3 Q2 Q2 Q1 Q1 Q0 Q0 9 10 7 6 2 3 1 15

D2

S R

Q1

D1 D0
D

11 5 4 14

D3 D2 D1 D0

S R

Q0

TTL 74171 Quad D-type D type FF with Clear (Small numbers represent pin #s on package)

clk

Kinds of Registers
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Input/Output Variations Selective Load Capability Tri-state or Open Collector Outputs True and Complementary Outputs

377
11 1 18 17 14 13 8 7 4 3 CLK EN D7 D6 D5 D4 D3 D2 D1 D0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q Q0 19 16 15 12 9 6 5 2

374
11 18 17 14 13 8 7 4 3 CLK H QH G QG QF F QE E D QD Q C QC B QB A QA OE 1 19 16 15 12 9 6 5 2

74377 Octal D-type FFs with input enable

74374 Octal D-type FFs p enable with output

EN enabled low and lo-to-hi clock transition to load new data into register

OE asserted low presents FF state to output pins; otherwise high impedence

A simple shift register

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In In Clock D Q Q Q1 D Q Q Q2 D Q Q Q3 D Q Q Q4 t0 Out t1 t2 t3 t4 1 0 1 1 1 0 0 0

Q1 0 1 0 1 1 1 0 0

Q2 0 0 1 0 1 1 1 0

Q3 0 0 0 1 0 1 1 1

Q4 = Out 0 0 0 0 1 0 1 1

(a) Circuit

t5 t6 t7

(b) A sample sequence

Parallel-access Parallel access shift register

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Parallel output Q3 Q2 Q1 Q0

Q Q

Q Q

Q Q

Q Q

Serial Shift/Load input

Parallel input

Clock

Shift Register I/O

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Serial S i l vs. Parallel P ll l Inputs I t Serial Inputs: LSI, RSI Serial vs. Parallel Outputs Parallel Inputs: D, C, B, A Shift Direction: Left vs. Right Parallel Outputs: QD, QC, QB, QA Clear Signal 10 S1 Positive Edge Triggered Devices
9 S0 7 LSI 6 D 5 C 194 4 B 3 A 2 RSI 12 13 14 15

11 CLK 1 CLR 74194 4-bit Universal Shift Register

S1,S0 determine the shift function S1 = 1, 1 S0 = 1: Load on rising clk edge synchronous load S1 = 1, S0 = 0: shift left on rising clk edge LSI replaces element D S1 = 0, S0 = 1: shift right on rising clk edge RSI replaces element A S1 = 0, S0 = 0: hold state Multiplexing logic on input to each FF!

Shifters well Shift ll suited it d for f serial-to-parallel i lt ll l conversions, i such as terminal to computer communications

Shift Register Application: Parallel to Serial Conversion

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Sender Receiver

Parallel Inputs

10 S1 9 S0 7 LSI 6D D7 5 C 194 D6 4 D5 D4 3B A 2 RSI Clock 11 CLK 1 CLR 10 S1 9 S0 7 LSI 6 D 5 C 194 4 3B A 2 RSI 11 CLK 1 CLR

12 13 14 15

10 S1 9 S0 7 LSI 6 D 5 C 194 4 3B A 2 RSI 11 CLK 1 CLR 10 S1 9 S0 7 LSI 6 D 5 C 194 4 3B A 2 RSI 11 CLK 1 CLR

12 D7 13 D6 14 D5 15 D4

Parallel Outputs
12D3 13D2 14D1 15D0

D3 D2 D1 D0

12 13 14 15

Serial transmission

Counters
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Counters
Proceed through a well-defined sequence of states in response to count signal 3 Bit Up-counter: 000, 001, 010, 011, 100, 101, 110, 111, 000, ... 3 Bit Down-counter: 111, 110, 101, 100, 011, 010, 001, 000, 111, ... Binary vs. BCD vs. Gray Code Counters A counter is a "degenerate" finite state machine/sequential circuit where the state is the only output

Types of counters Asynchronous vs. Synchronous Counters

Asynchronous counters
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Ripple counter
1 Clock
State transitions are not sharp! Can lead to "spiked outputs" from combinational logic decoding the counter's state

Q Q

Q Q

Q Q

Q0

Q1

Q2

(a) Circuit

Clock Q0 Q1 Q2 Count 0 1 2 3 4 5 6 7 0

A three-bit up-counter

(b) Timing diagram

Asynchronous counters counters, contd cont d

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1 Cl k Clock

Q Q

Q Q

Q Q

A three-bit down-counter

Q0

Q1

Q2

(a) Circuit
Clock Q0 Q1 Q2 Count 0 7 6 5 4 3 2 1 0

(b) Timing diagram

Synchronous counter
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A Asynchronous h counters

simple, but not very fast can build faster counters by clocking all FFs at the same time synchronous counter
Clock cycle Q2 Q1 Q0 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 Q1 changes Q2 changes 0 1 2 3 4 5 6 7 8

Synchronous counters with T F/F

T0=1 T1=Q0 T2=Q0Q1

A four four-bit bit synchronous up-counter up counter

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1 Clock

Q Q

Q0

Q Q

Q1

Q Q

Q2

Q Q

Q3

(a) Circuit
Clock Q0 Q1 Q2 Q3 Count 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1

(b) Timing diagram

Enable and Clear capability

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Enable Clock

Q Q

Q Q

Q Q

Q Q

Clear

A four four-bit bit counter with D FFs

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Enable

D Q Q

Q0

D Q Q

Q1

D Q Q

Q2

D Q Q Clock

Q3

Output carry

A counter with parallel-load capability

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Enable D0 0 1 D Q Q Q0

D1

0 1

Q Q

Q1

D2

0 1

Q Q

Q2

D3

0 1

Q Q

Q3

Load Clock

Output carry

Catalog Counter
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7 P 10 T 163 15 2 CLK RCO 6 5 4 3 9 1 D C B A LOAD CLR QD QC QB QA 11 12 13 14

Synchronous Load and Clear Inputs Positive Edge Triggered FFs Parallel Load Data from D, C, B, A P, T Enable Inputs: p both must be asserted to enable counting RCO: asserted when counter enters its highest state 1111 1111, used for cascading counters "Ripple Carry Output"

74163 Synchronous 4-Bit Upcounter 74161: similar in function, asynchronous load and reset

74163 Detailed Timing Diagram

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CLR LOAD A B C D CLK P T QA QB QC QD RCO Clear 12 Load 13 14 15 Count 0 1 2 Inhibit

A modulo-6 counter with synchronous reset

64 1 0 0 0 Enable D0 D1 D2 Load Clock

Q0 Q1 Q2

Clock

(a) Circuit

Clock Q0 Q1 Q2 Count 0 1 2 3 4 5 0 1

(b) Timing diagram

A modulo-6 counter with asynchronous reset

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1 Clock

Q Q

Q0

Q Q

Q1

Q Q

Q2

(a) Circuit

Clock Q0 Q1 Q2 Count 0 1 2 3 4 5 0 1 2

(b) Timing diagram

Other types of counters

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Two-digit BCD counters

Two modulo-10 counters, one for each digit Reset when the counter reaches 9

Ring counters

One bit is one while other bits are 0

one hot encoding

J h Johnson counter t

1000, 1100, 1110, 1111, 0111, 0011, 0001, 0000,

A two two-digit digit BCD counter

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1 0 0 0 0

Enable E bl D0 D1 D2 D3 Load Clock

Q0 Q1 Q2 Q3

BCD 0

Clock Clear 0 0 0 0 Enable D0 D1 D2 D3 Load Clock

Q0 Q1 Q2 Q3

BCD 1

Ring Counter
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Q0 Start Q1 Qn ? 1

Q Q

Q Q

Q Q

Clock

(a) An n -bit ring counter

Q0 Q1 Q2 Q3 y0 w1 y1 y2 y3 w0

2-to-4 decoder En

1 Q1 Q0

Clock

Clock

Two-bit up-counter Start Clear

(b) A four-bit ring counter

Johnson counter
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Q0

Q1

Qn 1

Q Q

Q Q

Q Q

Reset Clock